NXP Semiconductors MKL04Z8VFK4 Manuel utilisateur

KL04 Sub-Family Reference Manual

Supports: MKL04Z8VFK4, MKL04Z16VFK4, MKL04Z32VFK4,

MKL04Z8VLC4, MKL04Z16VLC4, MKL04Z32VLC4, MKL04Z8VFM4,

MKL04Z16VFM4, MKL04Z32VFM4, MKL04Z16VLF4, and

MKL04Z32VLF4

Document Number: KL04P48M48SF1RM

Rev. 3.1, November 2012

KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012

2 Freescale Semiconductor, Inc.

Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................29

1.1.1 Purpose.........................................................................................................................................................29

1.1.2 Audience......................................................................................................................................................29

1.2 Conventions..................................................................................................................................................................29

1.2.1 Numbering systems......................................................................................................................................29

1.2.2 Typographic notation...................................................................................................................................30

1.2.3 Special terms................................................................................................................................................30

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................31

2.2 Kinetis L Series.............................................................................................................................................................31

2.3 KL04 Sub-Family Introduction.....................................................................................................................................34

2.4 Module functional categories........................................................................................................................................35

2.4.1 ARM® Cortex™-M0+ Core Modules.........................................................................................................35

2.4.2 System Modules...........................................................................................................................................36

2.4.3 Memories and Memory Interfaces...............................................................................................................37

2.4.4 Clocks...........................................................................................................................................................37

2.4.5 Security and Integrity modules....................................................................................................................37

2.4.6 Analog modules...........................................................................................................................................38

2.4.7 Timer modules.............................................................................................................................................38

2.4.8 Communication interfaces...........................................................................................................................39

2.4.9 Human-machine interfaces..........................................................................................................................39

2.5 Orderable part numbers.................................................................................................................................................39

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................41

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3.2 Module to Module Interconnects..................................................................................................................................41

3.2.1 Module to Module Interconnects.................................................................................................................41

3.2.2 Analog reference options.............................................................................................................................43

3.3 Core Modules................................................................................................................................................................44

3.3.1 ARM Cortex-M0+ Core Configuration.......................................................................................................44

3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................46

3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................50

3.4 System Modules............................................................................................................................................................51

3.4.1 SIM Configuration.......................................................................................................................................51

3.4.2 System Mode Controller (SMC) Configuration...........................................................................................52

3.4.3 PMC Configuration......................................................................................................................................52

3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................53

3.4.5 MCM Configuration....................................................................................................................................55

3.4.6 Crossbar-Light Switch Configuration..........................................................................................................56

3.4.7 Peripheral Bridge Configuration..................................................................................................................57

3.4.8 DMA request multiplexer configuration......................................................................................................58

3.4.9 DMA Controller Configuration...................................................................................................................61

3.4.10 Computer Operating Properly (COP) Watchdog Configuration..................................................................61

3.5 Clock Modules..............................................................................................................................................................64

3.5.1 MCG Configuration.....................................................................................................................................64

3.5.2 OSC Configuration......................................................................................................................................65

3.6 Memories and Memory Interfaces................................................................................................................................66

3.6.1 Flash Memory Configuration.......................................................................................................................66

3.6.2 Flash Memory Controller Configuration.....................................................................................................68

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3.6.3 SRAM Configuration...................................................................................................................................69

3.7 Analog...........................................................................................................................................................................71

3.7.1 12-bit SAR ADC Configuration..................................................................................................................71

3.7.2 CMP Configuration......................................................................................................................................75

3.8 Timers...........................................................................................................................................................................77

3.8.1 Timer/PWM Module Configuration............................................................................................................77

3.8.2 PIT Configuration........................................................................................................................................79

3.8.3 Low-power timer configuration...................................................................................................................81

3.8.4 RTC configuration.......................................................................................................................................82

3.9 Communication interfaces............................................................................................................................................84

3.9.1 SPI configuration.........................................................................................................................................84

3.9.2 I2C Configuration........................................................................................................................................85

3.9.3 UART Configuration...................................................................................................................................85

3.10 Human-machine interfaces (HMI)................................................................................................................................87

3.10.1 GPIO Configuration.....................................................................................................................................87

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................91

4.2 System memory map.....................................................................................................................................................91

4.3 Flash Memory Map.......................................................................................................................................................92

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................92

4.4 SRAM memory map.....................................................................................................................................................93

4.5 Bit Manipulation Engine...............................................................................................................................................93

4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................94

4.6.1 Read-after-write sequence and required serialization of memory operations..............................................94

4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map..............................................................................................95

4.6.3 Modules Restricted Access in User Mode...................................................................................................98

4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................98

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Section number Title Page

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................101

5.2 Programming model......................................................................................................................................................101

5.3 High-Level device clocking diagram............................................................................................................................101

5.4 Clock definitions...........................................................................................................................................................102

5.4.1 Device clock summary.................................................................................................................................103

5.5 Internal clocking requirements.....................................................................................................................................105

5.5.1 Clock divider values after reset....................................................................................................................105

5.5.2 VLPR mode clocking...................................................................................................................................106

5.6 Clock Gating.................................................................................................................................................................106

5.7 Module clocks...............................................................................................................................................................106

5.7.1 PMC 1-kHz LPO clock................................................................................................................................107

5.7.2 COP clocking...............................................................................................................................................108

5.7.3 RTC clocking...............................................................................................................................................108

5.7.4 LPTMR clocking..........................................................................................................................................109

5.7.5 TPM clocking...............................................................................................................................................109

5.7.6 UART clocking............................................................................................................................................110

Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................111

6.2 Reset..............................................................................................................................................................................111

6.2.1 Power-on reset (POR)..................................................................................................................................112

6.2.2 System reset sources....................................................................................................................................112

6.2.3 MCU Resets.................................................................................................................................................115

6.2.4 Reset Pin .....................................................................................................................................................116

6.2.5 Debug resets.................................................................................................................................................117

6.3 Boot...............................................................................................................................................................................118

6.3.1 Boot sources.................................................................................................................................................118

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Section number Title Page

6.3.2 FOPT boot options.......................................................................................................................................118

6.3.3 Boot sequence..............................................................................................................................................119

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................121

7.2 Clocking Modes............................................................................................................................................................121

7.2.1 Partial Stop...................................................................................................................................................121

7.2.2 DMA Wakeup..............................................................................................................................................122

7.2.3 Compute Operation......................................................................................................................................123

7.2.4 Peripheral Doze............................................................................................................................................124

7.2.5 Clock Gating................................................................................................................................................125

7.3 Power modes.................................................................................................................................................................125

7.4 Entering and exiting power modes...............................................................................................................................127

7.5 Module Operation in Low Power Modes......................................................................................................................127

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................131

8.2 Flash Security...............................................................................................................................................................131

8.3 Security Interactions with other Modules.....................................................................................................................131

8.3.1 Security Interactions with Debug.................................................................................................................132

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................133

9.2 Debug Port Pin Descriptions.........................................................................................................................................133

9.3 SWD status and control registers..................................................................................................................................134

9.3.1 MDM-AP Control Register..........................................................................................................................135

9.3.2 MDM-AP Status Register............................................................................................................................136

9.4 Debug Resets................................................................................................................................................................138

9.5 Micro Trace Buffer (MTB)...........................................................................................................................................139

9.6 Debug in Low Power Modes........................................................................................................................................139

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9.7 Debug & Security.........................................................................................................................................................139

Chapter 10

Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................141

10.2 Signal Multiplexing Integration....................................................................................................................................141

10.2.1 Port control and interrupt module features..................................................................................................142

10.2.2 Clock gating.................................................................................................................................................143

10.2.3 Signal multiplexing constraints....................................................................................................................143

10.3 Pinout............................................................................................................................................................................143

10.3.1 KL04 signal multiplexing and pin assignments...........................................................................................143

10.3.2 KL04 Pinouts...............................................................................................................................................145

10.4 Module Signal Description Tables................................................................................................................................149

10.4.1 Core Modules...............................................................................................................................................149

10.4.2 System Modules...........................................................................................................................................150

10.4.3 Clock Modules.............................................................................................................................................150

10.4.4 Memories and Memory Interfaces...............................................................................................................150

10.4.5 Analog..........................................................................................................................................................150

10.4.6 Timer Modules.............................................................................................................................................151

10.4.7 Communication Interfaces...........................................................................................................................152

10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................152

Chapter 11

Port control and interrupts (PORT)

11.1 Introduction...................................................................................................................................................................153

11.2 Overview.......................................................................................................................................................................153

11.2.1 Features........................................................................................................................................................153

11.2.2 Modes of operation......................................................................................................................................154

11.3 External signal description............................................................................................................................................154

11.4 Detailed signal description............................................................................................................................................155

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Section number Title Page

11.5 Memory map and register definition.............................................................................................................................155

11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................158

11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................160

11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................161

11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................161

11.6 Functional description...................................................................................................................................................162

11.6.1 Pin control....................................................................................................................................................162

11.6.2 Global pin control........................................................................................................................................163

11.6.3 External interrupts........................................................................................................................................163

Chapter 12

System integration module (SIM)

12.1 Introduction...................................................................................................................................................................165

12.1.1 Features........................................................................................................................................................165

12.2 Memory map and register definition.............................................................................................................................165

12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................167

12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................167

12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................168

12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................170

12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................171

12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................172

12.2.7 System Device Identification Register (SIM_SDID)...................................................................................174

12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................176

12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................177

12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................179

12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................180

12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................181

12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................183

12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................184

12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................185

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12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................185

12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................186

12.2.18 COP Control Register (SIM_COPC)...........................................................................................................186

12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................187

12.3 Functional description...................................................................................................................................................188

Chapter 13

System Mode Controller (SMC)

13.1 Introduction...................................................................................................................................................................189

13.2 Modes of operation.......................................................................................................................................................189

13.3 Memory map and register descriptions.........................................................................................................................191

13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................191

13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................193

13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................194

13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................195

13.4 Functional description...................................................................................................................................................196

13.4.1 Power mode transitions................................................................................................................................196

13.4.2 Power mode entry/exit sequencing..............................................................................................................199

13.4.3 Run modes....................................................................................................................................................201

13.4.4 Wait modes..................................................................................................................................................203

13.4.5 Stop modes...................................................................................................................................................204

13.4.6 Debug in low power modes.........................................................................................................................207

Chapter 14

Power Management Controller (PMC)

14.1 Introduction...................................................................................................................................................................209

14.2 Features.........................................................................................................................................................................209

14.3 Low-voltage detect (LVD) system................................................................................................................................209

14.3.1 LVD reset operation.....................................................................................................................................210

14.3.2 LVD interrupt operation...............................................................................................................................210

14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................210

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