NXP Semiconductors Freescale K51 Series Manuel utilisateur

K51 Sub-Family Reference Manual

Supports: MK51DX256ZCMC10, MK51DN512ZCMC10

Document Number: K51P121M100SF2RM

Rev. 6, Nov 2011

K51 Sub-Family Reference Manual, Rev. 6, Nov 2011

2 Freescale Semiconductor, Inc.

Contents

Section Number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................53

1.1.1 Purpose.........................................................................................................................................................53

1.1.2 Audience......................................................................................................................................................53

1.2 Conventions..................................................................................................................................................................53

1.2.1 Numbering systems......................................................................................................................................53

1.2.2 Typographic notation...................................................................................................................................54

1.2.3 Special terms................................................................................................................................................54

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................55

2.2 K50 Family Introduction...............................................................................................................................................55

2.3 Module Functional Categories......................................................................................................................................55

2.3.1 ARM Cortex-M4 Core Modules..................................................................................................................57

2.3.2 System Modules...........................................................................................................................................57

2.3.3 Memories and Memory Interfaces...............................................................................................................58

2.3.4 Clocks...........................................................................................................................................................59

2.3.5 Security and Integrity modules....................................................................................................................59

2.3.6 Analog modules...........................................................................................................................................59

2.3.7 Timer modules.............................................................................................................................................60

2.3.8 Communication interfaces...........................................................................................................................61

2.3.9 Human-machine interfaces..........................................................................................................................62

2.4 Orderable part numbers.................................................................................................................................................62

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................65

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Section Number Title Page

3.2 Core modules................................................................................................................................................................65

3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................65

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................68

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................74

3.2.4 JTAG Controller Configuration...................................................................................................................75

3.3 System modules............................................................................................................................................................76

3.3.1 SIM Configuration.......................................................................................................................................76

3.3.2 Mode Controller Configuration...................................................................................................................77

3.3.3 PMC Configuration......................................................................................................................................77

3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................78

3.3.5 MCM Configuration....................................................................................................................................80

3.3.6 Crossbar Switch Configuration....................................................................................................................80

3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................82

3.3.8 Peripheral Bridge Configuration..................................................................................................................85

3.3.9 DMA request multiplexer configuration......................................................................................................87

3.3.10 DMA Controller Configuration...................................................................................................................90

3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................91

3.3.12 Watchdog Configuration..............................................................................................................................92

3.4 Clock Modules..............................................................................................................................................................93

3.4.1 MCG Configuration.....................................................................................................................................93

3.4.2 OSC Configuration......................................................................................................................................94

3.4.3 RTC OSC configuration...............................................................................................................................95

3.5 Memories and Memory Interfaces................................................................................................................................95

3.5.1 Flash Memory Configuration.......................................................................................................................95

3.5.2 Flash Memory Controller Configuration.....................................................................................................99

3.5.3 SRAM Configuration...................................................................................................................................100

3.5.4 SRAM Controller Configuration.................................................................................................................103

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Section Number Title Page

3.5.5 System Register File Configuration.............................................................................................................104

3.5.6 VBAT Register File Configuration..............................................................................................................105

3.5.7 EzPort Configuration...................................................................................................................................106

3.6 Security.........................................................................................................................................................................107

3.6.1 CRC Configuration......................................................................................................................................107

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3.7 Analog...........................................................................................................................................................................107

3.7.1 16-bit SAR ADC with PGA Configuration.................................................................................................107

3.7.2 CMP Configuration......................................................................................................................................115

3.7.3 12-bit DAC Configuration...........................................................................................................................117

3.7.4 Op-amp Configuration.................................................................................................................................118

3.7.5 TRIAMP Configuration...............................................................................................................................120

3.7.6 VREF Configuration....................................................................................................................................121

3.8 Timers...........................................................................................................................................................................122

3.8.1 PDB Configuration......................................................................................................................................122

3.8.2 FlexTimer Configuration.............................................................................................................................126

3.8.3 PIT Configuration........................................................................................................................................129

3.8.4 Low-power timer configuration...................................................................................................................130

3.8.5 CMT Configuration......................................................................................................................................132

3.8.6 RTC configuration.......................................................................................................................................133

3.9 Communication interfaces............................................................................................................................................134

3.9.1 Universal Serial Bus (USB) Subsystem.......................................................................................................134

3.9.2 SPI configuration.........................................................................................................................................139

3.9.3 I2C Configuration........................................................................................................................................142

3.9.4 UART Configuration...................................................................................................................................143

3.9.5 SDHC Configuration....................................................................................................................................145

3.9.6 I2S configuration..........................................................................................................................................146

3.10 Human-machine interfaces (HMI)................................................................................................................................148

3.10.1 GPIO configuration......................................................................................................................................148

3.10.2 TSI Configuration........................................................................................................................................149

3.10.3 Segment LCD Configuration.......................................................................................................................152

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................155

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Section Number Title Page

4.2 System memory map.....................................................................................................................................................155

4.2.1 Aliased bit-band regions..............................................................................................................................156

4.3 Flash Memory Map.......................................................................................................................................................157

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................158

4.4 SRAM memory map.....................................................................................................................................................158

4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................159

4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................159

4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................163

4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................167

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................169

5.2 Programming model......................................................................................................................................................169

5.3 High-Level device clocking diagram............................................................................................................................169

5.4 Clock definitions...........................................................................................................................................................170

5.4.1 Device clock summary.................................................................................................................................171

5.5 Internal clocking requirements.....................................................................................................................................173

5.5.1 Clock divider values after reset....................................................................................................................173

5.5.2 VLPR mode clocking...................................................................................................................................174

5.6 Clock Gating.................................................................................................................................................................174

5.7 Module clocks...............................................................................................................................................................174

5.7.1 PMC 1-kHz LPO clock................................................................................................................................176

5.7.2 WDOG clocking..........................................................................................................................................176

5.7.3 Debug trace clock.........................................................................................................................................177

5.7.4 PORT digital filter clocking.........................................................................................................................177

5.7.5 LPTMR clocking..........................................................................................................................................178

5.7.6 USB FS OTG Controller clocking...............................................................................................................178

5.7.7 UART clocking............................................................................................................................................179

5.7.8 SDHC clocking............................................................................................................................................179

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Section Number Title Page

5.7.9 I2S clocking.................................................................................................................................................180

5.7.10 TSI clocking.................................................................................................................................................180

Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................183

6.2 Reset..............................................................................................................................................................................183

6.2.1 Power-on reset (POR)..................................................................................................................................184

6.2.2 System resets................................................................................................................................................184

6.2.3 Debug resets.................................................................................................................................................187

6.3 Boot...............................................................................................................................................................................189

6.3.1 Boot sources.................................................................................................................................................189

6.3.2 Boot options.................................................................................................................................................189

6.3.3 FOPT boot options.......................................................................................................................................189

6.3.4 Boot sequence..............................................................................................................................................190

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................193

7.2 Power modes.................................................................................................................................................................193

7.3 Entering and exiting power modes...............................................................................................................................195

7.4 Power mode transitions.................................................................................................................................................196

7.5 Power modes shutdown sequencing.............................................................................................................................197

7.6 Module Operation in Low Power Modes......................................................................................................................197

7.7 Clock Gating.................................................................................................................................................................200

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................201

8.2 Flash Security...............................................................................................................................................................201

8.3 Security Interactions with other Modules.....................................................................................................................202

8.3.1 Security Interactions with EzPort................................................................................................................202

8.3.2 Security Interactions with Debug.................................................................................................................202

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Section Number Title Page

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................203

9.1.1 References....................................................................................................................................................205

9.2 The Debug Port.............................................................................................................................................................205

9.2.1 JTAG-to-SWD change sequence.................................................................................................................206

9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................206

9.3 Debug Port Pin Descriptions.........................................................................................................................................207

9.4 System TAP connection................................................................................................................................................207

9.4.1 IR Codes.......................................................................................................................................................207

9.5 JTAG status and control registers.................................................................................................................................208

9.5.1 MDM-AP Control Register..........................................................................................................................209

9.5.2 MDM-AP Status Register............................................................................................................................211

9.6 Debug Resets................................................................................................................................................................212

9.7 AHB-AP........................................................................................................................................................................213

9.8 ITM...............................................................................................................................................................................214

9.9 Core Trace Connectivity...............................................................................................................................................214

9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................214

9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................215

9.11.1 Performance Profiling with the ETB...........................................................................................................215

9.11.2 ETB Counter Control...................................................................................................................................216

9.12 TPIU..............................................................................................................................................................................216

9.13 DWT.............................................................................................................................................................................216

9.14 Debug in Low Power Modes........................................................................................................................................217

9.14.1 Debug Module State in Low Power Modes.................................................................................................218

9.15 Debug & Security.........................................................................................................................................................218

Chapter 10

Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................219

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10.2 Signal Multiplexing Integration....................................................................................................................................219

10.2.1 Port control and interrupt module features..................................................................................................220

10.2.2 Clock gating.................................................................................................................................................220

10.2.3 Signal multiplexing constraints....................................................................................................................220

10.3 Pinout............................................................................................................................................................................221

10.3.1 K51 Signal Multiplexing and Pin Assignments...........................................................................................221

10.3.2 K51 Pinouts..................................................................................................................................................226

10.4 Module Signal Description Tables................................................................................................................................227

10.4.1 Core Modules...............................................................................................................................................227

10.4.2 System Modules...........................................................................................................................................228

10.4.3 Clock Modules.............................................................................................................................................229

10.4.4 Memories and Memory Interfaces...............................................................................................................229

10.4.5 Analog..........................................................................................................................................................230

10.4.6 Communication Interfaces...........................................................................................................................232

10.4.7 Human-Machine Interfaces (HMI)..............................................................................................................236

Chapter 11

Port control and interrupts (PORT)

11.1 Introduction...................................................................................................................................................................237

11.1.1 Overview......................................................................................................................................................237

11.1.2 Features........................................................................................................................................................237

11.1.3 Modes of operation......................................................................................................................................238

11.2 External signal description............................................................................................................................................239

11.3 Detailed signal descriptions..........................................................................................................................................239

11.4 Memory map and register definition.............................................................................................................................239

11.4.1 Pin Control Register n (PORTx_PCRn).......................................................................................................246

11.4.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................248

11.4.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................249

11.4.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................249

11.4.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................250

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