NEC 78GK0S/K 1+ Series Instructions d'installation et d'utilisation

Application Note

78K0S/Kx1+

Sample Program (Watchdog Timer)

131 ms Interval Runaway Detection

This document describes an operation overview of the sample program, as well as how to use the sample program and

how to set and use the watchdog timer. In the sample program, a reset signal generated by an overflow of the

watchdog timer is generated at a 50% chance of occurrence during a switch input, by setting the runaway detection time

to 131 ms.

CONTENTS

CHAPTER 1 OVERVIEW ...................................................................................3

1.1 Main Contents of Initial Settings ..............................................................4

1.2 Contents Following the Main Loop...........................................................4

CHAPTER 2 CIRCUIT DIAGRAM ....................................................................6

2.1 Circuit Diagram ........................................................................................6

2.2 Peripheral Hardware................................................................................6

CHAPTER 3 SOFTWARE .................................................................................7

3.1 File Configuration.....................................................................................7

3.2 Internal Peripheral Functions to Be Used ................................................8

3.3 Initial Settings and Operation Overview...................................................8

3.4 Flow Chart..............................................................................................10

CHAPTER 4 SETTING METHODS ................................................................11

4.1 Watchdog Timer (WDT) Setting.............................................................11

CHAPTER 5 OPERATION CHECK USING THE DEVICE ..........................19

5.1 Building the Sample Program ................................................................19

5.2 Operation with the Device......................................................................21

CHAPTER 6 RELATED DOCUMENTS..........................................................23

APPENDIX A PROGRAM LIST......................................................................24

APPENDIX B REVISION HISTORY ...............................................................36

Target devices

78K0S/KA1+ microcontroller

78K0S/KB1+ microcontroller

78K0S/KU1+ microcontroller

78K0S/KY1+ microcontroller

Document No. U18847EJ1V0AN00 (1st edition)

Date Published October 2007 N

Printed in Japan

2007

The information in this document is current as of July, 2007. The information is subject to change

without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or

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Application Note U18847EJ1V0AN

CHAPTER 1 OVERVIEW

In this sample program, an example of using the watchdog timer (WDT) function is presented.

The system clock is set as the operation clock of the watchdog timer and the runaway detection time is set to about

131 ms.

After completion of the initial settings, LED1 out of the two LEDs (LED1, LED2) blinks about every 120 ms.

Either of the following operations is performed at a 50% chance of occurrence (see the figure below), depending on

the switch input timing.

•LED1 blinks about every 60 ms during switch input by executing interrupt servicing.

•A reset signal is generated by an overflow of the watchdog timer during interrupt servicing. After reset release,

LED2 lights and LED1 blinks about every 120 ms.

On (turned on for at least 10 ms)

<Input>

LED2 LED1

Blinks about

every 120 ms.

Lights.

LED2 LED1

Blinks about

every 60 ms.

<1>

<2>

Main processing

Interrupt

servicing

WDT clear WDT clear WDT clear

About 120 ms

X ms

About

10 ms

(Chattering

removal)

About 60 ms About 60 ms

Switch: on Switch: off

<1> X ms + 10 ms + 60 ms ≤131 ms

→No overflow occurs. →Interrupt servicing continues.

WDT overflow time = 2

= About 131 ms (f

= 8 MHz)

<2> X ms + 10 ms + 60 ms > 131 ms

→An overflow occurs. →A WDT reset is generated during interrupt

servicing.

The probability that an overflow occurs is 61 ms/120 ms,

which is about 50%, because an overflow occurs when X ms > 61 ms.

LED2 LED1

Blinks about

every 120 ms.

Interrupt

servicing

starts

About 120 ms

• • •

Application Note U18847EJ1V0AN 3

CHAPTER 1 OVERVIEW

1.1 Main Contents of Initial Settings

The contents of the initial settings are as follows.

• Selecting the high-speed internal oscillator (8 MHz (TYP.)) as the system clock sourceNote

• Setting so that oscillation of the low-speed internal oscillator can be stopped by using softwareNote

• Selecting the system clock (fX) for the watchdog timer operation clock, setting the overflow time to 220/fX(about

131 ms)

• Lighting LED2, when an internal reset signal is generated by the watchdog timer

• Setting VLVI (low-voltage detection voltage) to 2.85 V ±0.15 V

• Generating an internal reset (LVI reset) signal when it is detected that VDD is less than VLV I, after VDD (power

supply voltage) becomes greater than or equal to VLVI

• Setting the CPU clock frequency to 4 MHz

• Setting I/O ports

• Setting the valid edge of INTP1 (external interrupt) to the falling edge

• Enabling interrupt

Note This is set by using the option byte.

1.2 Contents Following the Main Loop

After completion of the initial settings, LED1 out of the two LEDs (LED1, LED2) blinks about every 120 ms, in the

main loop.

LED2 LED1

Blinks about

every 120 ms.

Interrupt servicing is performed by detecting the falling edge of the INTP1 pin generated by switch input. If INTP1

is at high level (switch is turned off) after about 10 ms have elapsed since the falling edge of the INTP1 pin was

detected, processing is identified as chattering and returned to the main loop. If INTP1 is at low level (switch is turned

on) after about 10 ms have elapsed since edge detection, the following processing is advanced.

[Column] Chattering

Chattering is a phenomenon in which the electric signal repeats turning on and off due to a mechanical

flip-flop of the contacts, immediately after the switch has been pressed.

Application Note U18847EJ1V0AN

CHAPTER 1 OVERVIEW

Either of the following operations is performed at a 50% chance of occurrence (see the figure below), depending on

the switch input timing.

<1> If an overflow is not caused by the watchdog timer during interrupt servicing

Due to the execution of interrupt servicing, LED1 blinks about every 60 ms during switch input. When INTP1

goes to high level (switch is turned off), LED1 blinks about every 120 ms.

<2> If an overflow is caused by the watchdog timer during interrupt servicing

A reset signal is generated by the watchdog timer. After reset release, LED2 lights and LED1 blinks about

every 120 ms.

Remark LED2 is turned off by a reset signal generated by other than the watchdog timer.

On (turned on for at least 10 ms)

<Input>

LED2 LED1

Blinks about

every 120 ms.

Lights.

LED2 LED1

Blinks about

every 60 ms.

<1>

<2>

Main processing

Interrupt

servicing

WDT clear WDT clear WDT clear

About 120 ms

X ms

About

10 ms

(Chattering

removal)

About 60 ms About 60 ms

Switch: on Switch: off

<1> X ms + 10 ms + 60 ms ≤131 ms

→No overflow occurs. →Interrupt servicing continues.

WDT overflow time = 2

= About 131 ms (f

= 8 MHz)

<2> X ms + 10 ms + 60 ms > 131 ms

→An overflow occurs. →A WDT reset is generated during interrupt

servicing.

The probability that an overflow occurs is 61 ms/120 ms,

which is about 50%, because an overflow occurs when X ms > 61 ms.

Interrupt

servicing

starts

About 120 ms

• • •

Set in the initial

settings.

Main loop

operation

Cautions 1. In this sample program, the watchdog timer is not cleared at the beginning of interrupt servicing

to generate a reset signal at a 50% chance of occurrence by the watchdog timer during interrupt

servicing. In general use, the watchdog timer is cleared at the beginning and end of interrupt

servicing so that no overflow occurs.

2. For cautions when using the device, refer to the user’s manual of each product (78K0S/KU1+,

78K0S/KY1+, 78K0S/KA1+, 78K0S/KB1+).

Application Note U18847EJ1V0AN 5

CHAPTER 2 CIRCUIT DIAGRAM

This chapter describes a circuit diagram and the peripheral hardware to be used in this sample program.

2.1 Circuit Diagram

A circuit diagram is shown below.

VDD

DDNote 1

INTP1

Note 2

RESET

P21

P20

VDD

LED2 VDD

LED1

78K0S/Kx1+

microcontroller

Notes 1. Use this in a voltage range of 3.0 V ≤VDD ≤5.5 V.

2. INTP1/P43: 78K0S/KA1+ and 78K0S/KB1+ microcontrollers

INTP1/P32: 78K0S/KY1+ and 78K0S/KU1+ microcontrollers

Cautions 1. Connect the AVREF pin directly to VDD (only for the 78K0S/KA1+ and 78K0S/KB1+

microcontrollers).

2. Connect the AVSS pin directly to GND (only for the 78K0S/KB1+ microcontroller).

3. Leave all unused pins open (unconnected), except for the pins shown in the circuit diagram

and the AVREF and AVSS pins.

2.2 Peripheral Hardware

The peripheral hardware to be used is shown below.

(1) Switch (SW)

A switch is used as an input to control the lighting of an LED.

(2) LEDs (LED1, LED2)

The LEDs are used as outputs corresponding to switch inputs and reset signals generated by the watchdog

timer.

Application Note U18847EJ1V0AN

CHAPTER 3 SOFTWARE

This chapter describes the file configuration of the compressed file to be downloaded, internal peripheral functions

of the microcontroller to be used, and initial settings and operation overview of the sample program, and shows a flow

chart.

3.1 File Configuration

The following table shows the file configuration of the compressed file to be downloaded.

Compressed (*.zip) File IncludedFile Name Description

main.asm

(Assembly language

version)

main.c

(C language version)

Source file for hardware initialization processing and main

processing of microcontroller

zNote zNote

op.asm Assembler source file for setting the option byte (sets the

system clock source)

wdt.prw Work space file for integrated development environment PM+ z

wdt.prj Project file for integrated development environment PM+ z

Note “main.asm” is included with the assembly language version, and “main.c” with the C language version.

Remark : Only the source files are included.

: The files to be used with integrated development environment PM+ are included.

Application Note U18847EJ1V0AN 7

CHAPTER 3 SOFTWARE

3.2 Internal Peripheral Functions to Be Used

The following internal peripheral functions of the microcontroller are used in this sample program.

•Program runaway detection: Watchdog timer

•VDD <VLV I detection: Low-voltage detector (LVI)

•Switch input: INTP1Note (external interrupt)

•LED outputs: P20, P21 (output ports)

Note INTP1/P43: 78K0S/KA1+ and 78K0S/KB1+ microcontrollers

INTP1/P32: 78K0S/KY1+ and 78K0S/KU1+ microcontrollers

3.3 Initial Settings and Operation Overview

In this sample program, setting of the watchdog timer and low-voltage detection function, selection of the clock

frequency, and setting of the I/O ports, interrupts, and the like are performed in the initial settings.

After completion of the initial settings, LED1 out of the two LEDs (LED1, LED2) blinks about every 120 ms, in the

main loop.

Interrupt servicing is performed by detecting the falling edge of the INTP1 pin generated by switch input. If INTP1

is at high level (switch is turned off) after about 10 ms have elapsed since the falling edge of the INTP1 pin was

detected, processing is identified as chattering and returned to the main loop. If INTP1 is at low level (switch is turned

on) after about 10 ms have elapsed since edge detection, the following processing is advanced.

Either of the following operations is performed at a 50% chance of occurrence, depending on the switch input

timing.

<1> If an overflow is not caused by the watchdog timer during interrupt servicing

Due to the execution of interrupt servicing, LED1 blinks about every 60 ms during switch input. When INTP1

goes to high level (switch is turned off), LED1 blinks about every 120 ms.

<2> If an overflow is caused by the watchdog timer during interrupt servicing

A reset signal is generated by the watchdog timer. After reset release, LED2 lights and LED1 blinks about

every 120 ms.

Caution In this sample program, the count of the watchdog timer is not cleared at the beginning of

interrupt servicing to generate a reset signal at a 50% chance of occurrence by the watchdog

timer during interrupt servicing. In general use, the count of the watchdog timer is cleared at the

beginning and end of interrupt servicing so that no overflow occurs.

Application Note U18847EJ1V0AN

CHAPTER 3 SOFTWARE

The details are described in the state transition diagram shown below.

Initial settings 1

Referencing the option byte

• Selecting the high-speed internal oscillator

(8 MHz (TYP.)) as the system clock source

• The low-speed internal oscillator can be

stopped by software

• The P34/RESET pin is used as the RESET

Stack pointer setting

Selecting the system clock (f

) for the

watchdog timer operation clock, setting the

overflow time to 2

Setting the CPU clock frequency to 2 MHz

Turning off LED1 and LED2

Reset source check 1

Initial settings 2

Setting the CPU clock frequency to 4 MHz

I/O port setting

• Setting only P43/INTP1

Note

as an input

port, and using an internal pull-up resistor

Interrupt setting

• Setting the valid edge of INTP1 (external

interrupt) to the falling edge

• Enabling interrupt

Setting V

LVI

to 2.85 V ±0.15 V

and starting low-voltage detection

operation

Setting so that an internal reset

signal is generated when

< V

LVI

≥

LVI

Clearing the watchdog timer

WDT reset

LVI reset

Lighting LED2

Reset other than by WDT

Reset source check 2

POC reset or external

reset

Blinking LED1 every 120 ms (main processing)

Blinking LED1 every 60 ms (interrupt servicing)

INTP1 =

Low level

INTP1 =

High level

10 ms wait

INTP1 falling edge

detection

INTP1 = High level

(chattering detection)

INTP1 = Low level

Clearing the INTP1

interrupt request

200 s wait

Reversing LED1 output

120 ms wait

Clearing the watchdog

timer

Reversing LED1 output

60 ms wait

Clearing the watchdog

timer

LVI

•

Note INTP1/P43: 78K0S/KA1+ and 78K0S/KB1+ microcontrollers

INTP1/P32: 78K0S/KY1+ and 78K0S/KU1+ microcontrollers

Application Note U18847EJ1V0AN 9

CHAPTER 3 SOFTWARE

3.4 Flow Chart

A flow chart for the sample program is shown below.

Interrupt servicing start

Saving the AX register data

10 ms wait

(chattering removal)

INTP1 pin input level

Low level

Reversing LED1 output

60 ms wait

Restoring the AX register data

Return

High level

Start

Watchdog timer setting

(overflow time:

= 131.07 ms)

Stack pointer setting

I/O port setting

Initial settings

Referencing the option byte

Note

Reversing LED1 output

Enabling interrupt

Setting the CPU clock

frequency to 2 MHz

INTP1 setting

LVI reset generation?

LVI

= 2.85 V ±0.15 V

200 ms

EGCg

≥V

LVI

Setting the CPU clock

frequency to 4 MHz

Yes

Setting so that an internal

reset signal is generated when

< V

LVI

WDT reset generation?

Yes

Lighting LED2

Turning off LED1 and LED2

Yes

Clearing the watchdog timer

200 s wait

120 ms wait

Clearing the watchdog timer

INTP1 pin input level

Low level

High level

Clearing the INTP1

interrupt request

Note Referencing the option byte is automatically performed by the microcontroller after reset release. In this

sample program, the following contents are set by referencing the option byte.

•Using the high-speed internal oscillation clock (8 MHz (TYP.)) as the system clock source

•The low-speed internal oscillator can be stopped by using software

•Using the P34/RESET pin as the RESET pin

Caution In this sample program, the watchdog timer is not cleared at the beginning of interrupt servicing

to generate a reset signal at a 50% chance of occurrence by the watchdog timer during interrupt

servicing. In general use, the watchdog timer is cleared at the beginning and end of interrupt

servicing so that no overflow occurs.

Application Note U18847EJ1V0AN

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