NXP Semiconductors KE17Z Series Manuel utilisateur
1 Introduction
Touch Sensing Interface (TSI) provides touch sensing detection on capacitive
touch sensors. The external capacitive touch sensor is typically formed on
PCB. The sensor electrodes are connected to TSI input channels through the
I/O pins in the device.
1.1 KE17Z dual TSI
KE17Z MCU has two TSI modules. It supports two kinds of touch
sensing methods: self-capacitance (also called self-cap) mode and mutual
capacitance (also called mutual-cap) mode.
The dual-TSI technology of KE17Z MCU supports up to 50 touch channels. The
two TSI modules not only increase the number of touch electrode, but also work
in parallel to increase the scanning efficiency of touch electrode and save the
scanning time.
To enhance the liquid tolerance and improve the driving ability, each TSI
module has three shield channels, up to 25 touch channels for self-cap mode,
and up to 6 × 6 touch channels for mutual-cap mode. Both mentioned methods
can be combined on one single PCB, while only the lower 12 TSI channels
TSI[0:11] can be used for mutual mode.
TSI[0:5] are TSI TX pins and TSI[6:11] are TSI RX pins in
mutual mode.
NOTE
• In the self-capacitive mode, developers can use these 50 channels to
design 50 (25 × 2) touch electrodes.
• In the mutual-capacitive mode, design options expand to up to 72 (6 × 6
× 2) touch electrodes.
In some use cases, such as, a multi-burner induction cooker with touch controls
or touch keyboards, the MCUs can support touchscreen designs scaling up
to 98 touch electrodes (26 electrodes using self-capacitance + 72 electrodes
using mutual channels).
1.2 TSI model comparison of KE17Z parts
Table 1 lists the number of TSI channels corresponding to different parts of
KE17Z. These parts all support dual TSI modules.
Contents
1 Introduction......................................1
1.1 KE17Z dual TSI............................1
1.2 TSI model comparison of KE17Z
parts.............................................1
1.3 TSI model comparison between
KE17Z parts and KE15Z parts.....3
1.4 KE17Z dual TSI evaluation board
.....................................................6
2 TSI self-cap mode introduction....... 7
2.1 Self-cap touch sensor.................. 7
2.2 Self-cap sensing mode................ 7
2.3 Clock generation..........................9
2.4 TSI scan time and scan result
accumulation..............................12
2.5 Scan time and sensitivity boost
tests in self-cap mode................15
3 TSI Mutual-cap mode....................18
3.1 Mutual-cap sensor..................... 18
3.2 Clock generation in mutual-cap
mode..........................................19
3.3 Mutual-cap sensing mode..........20
3.4 Sensitivity boost in mutual-cap
mode..........................................23
4 Shield channels.............................24
4.1 Principle of self-cap mode to
improve liquid tolerance by
enabling shield channels........... 24
4.2 Advantages of three shield
channels of KE17Z of each TSI. 25
4.3 Principle of mutual-cap mode to
improve liquid tolerance.............25
5 Hardware design guide................. 25
5.1 Electrode design........................ 26
5.2 PCB trace routing.......................26
5.3 Ground plane............................. 27
5.4 Overlay of the touch electrode...28
5.5 Electrodes placement................ 30
5.6 Hardware checklist.....................30
5.7 X-KE17Z-TSI-EVB touch electrode
patterns design.......................... 30
6 References....................................34
7 Revision history.............................34
Legal information.................................... 35
KE17ZDTSIUG
KE17Z Dual TSI User Guide
Rev. 0 — 05 May 2022 User Guide
Table 1. KE17Z parts supporting dual TSI modules
Product Memory Package IO and ADC channel HMI
Part number Flash
(kB)
SRAM
(kB) Pin count Package GPIOs GPIOs
(INT/HD)
ADC
channels TSI
MKE17Z256VLL7 256 48 100 LQFP 89 89/8 16 50 ch
MKE17Z256VLH7 256 48 64 LQFP 58 58/8 16 47 ch
MKE17Z256VLF7 256 48 48 LQFP 42 42/6 11 31 ch
MKE17Z128VLL7 128 32 100 LQFP 89 89/8 16 50 ch
MKE17Z128VLH7 128 32 64 LQFP 58 58/8 16 47 ch
MKE17Z128VLF7 128 32 48 LQFP 42 42/6 11 31 ch
Table 2. KE17Z dual TSI channels for different package
Product TSI TSI0 TSI1
KE17Z
100LQFP 50 ch 25
channels
TSI0[0: 24]
25
channels
TSI1[0: 24]
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
TX[0:5], RX[6:11] TX[0:5], RX[6:11]
KE17Z
64LQFP
47 ch 22
channels
TSI0[0: 12], [16: 24]
25
channels
TSI1[0: 24]
No CH13, CH14, CH15
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
TX[0:5], RX[6:11] TX[0:5], RX[6:11]
KE17Z
48LQFP
31 ch 15
channels
No CH2, CH3, CH4, CH5, CH13,
CH14, CH15, CH19, CH20,
CH21 16
channels
No CH8, CH9, CH10, CH13,
CH14, CH19, CH20, CH21, CH22
One shield channel: CH12 Two shield channels: CH4, CH12
TX[0:1], RX[6:11] TX[0:5], RX[7,11]
Figure 1 shows the assignment of dual TSI channels on the three packages of KE17Z. Compared with the KE17Z 100LQFP, the
TSI channels marked in yellow are not supported in the KE17Z 64 LQFP. The ones marked in yellow and red are TSI channels
not supported in K17Z 48 LQFP.
NXP Semiconductors
Introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
User Guide 2 / 37
Figure 1. TSI channel assignment of KE17Z 100 LQFP, KE17Z 64 LQFP, and KE17Z 48 LQFP
1.3 TSI model comparison between KE17Z parts and KE15Z parts
Table 3. KE17Z dual TSI channels for different package
Product TSI TSI0 TSI1
KE15Z
100LQFP
MKE15Z256VLL7
MKE15Z128VLL7
25 ch 25
channels
TSI0[0 : 24]
One shield channel: CH12
TX[0:5], RX[6:11]
KE17Z
100LQFP
MKE17Z256VLL7
50 ch 25
channels
TSI0[0: 24]
25
channels
TSI1[0: 24]
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
Table continues on the next page...
NXP Semiconductors
Introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
User Guide 3 / 37
Table 3. KE17Z dual TSI channels for different package (continued)
Product TSI TSI0 TSI1
MKE17Z128VLL7 TX[0:5], RX[6:11] TX[0:5], RX[6:11]
KE15Z
64LQFP
MKE15Z256VLH7
MKE15Z128VLH7
25 ch 25
channels
TSI0[0: 24]
One shield channel: CH12
TX[0:5], RX[6:11]
KE17Z
64LQFP
MKE17Z256VLH7
MKE17Z128VLH7
47 ch 22
channels
TSI0[0 : 12], [16 : 24]
25
channels
TSI1[0:24]
No CH13,CH14,CH15
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
TX[0:5], RX[6:11] TX[0:5], RX[6:11]
KE15Z/KE16Z
48LQFP
MKE16Z64VLF4
MKE15Z64VLF4
MKE16Z32VLF4
MKE15Z32VLF4
25 ch 25
channels
TSI0[0: 24]
One shield channel: CH12
TX[0:5], RX[6:11]
KE17Z
48LQFP
MKE17Z256VLF7
MKE17Z128VLF7
47 ch 22
channels
TSI0[0 : 12], [16 : 24]
25
channels
TSI1[0: 24]
No CH13, CH14, CH15
Three shield channels: CH4,
CH12, CH21
Three shield channels: CH4,
CH12, CH21
TX[0:5], RX[6:11] TX[0:5], RX[6:11]
For the KE17Z in 100LQFP, 64LQFP, and 48LQFP packages, its pin assignment is compatible with the KE15Z. That is, the
number and position of GPIO pins are the same. But the TSI channel assignment of KE17Z is different from KE15Z. To migrate
touch code from KE15Z to KE17Z, see Figure 2, Figure 3, and Figure 4 for the TSI channel assignment. For more migration details,
see
Migration Guide from KE15Z256 to KE17Z256
(document AN13429).
NXP Semiconductors
Introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
User Guide 4 / 37
Figure 2. TSI pin assignment comparison of 100 LQFP between KE15Z and KE17Z
Figure 3. TSI pin assignment comparison of 64 LQFP between KE15Z and KE17Z
NXP Semiconductors
Introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
User Guide 5 / 37
Figure 4. TSI pin assignment comparison of 48 LQFP between KE15Z/KE16Z and KE17Z
1.4 KE17Z dual TSI evaluation board
X-KE17Z-TSI-EVB is a touch sensing reference design including multiple touch patterns based on the 5 V Robust KE17Z MCU
of NXP. It has dual-TSI modules and supports up to 50 touch channels, all demonstrated on the board.
Figure 5. X-KE17Z-TSI-EVB, KE17Z dual TSI evaluation board
NXP Semiconductors
Introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
User Guide 6 / 37
2 TSI self-cap mode introduction
The sensor structure and electric field distribution between self-cap sensor and mutual-cap sensor are different.
2.1 Self-cap touch sensor
Ground Hatch
Electrode Ground Hatch
Ground Hatch
PCB
Dielectric Overlay
Cs Cs
ΔCs
via
Routing I/O pin
Self-cap
electrode
Ground hatch
Figure 6. Self-cap touch sensor structure and electric field
In self-cap mode, TSI requires only one pin for each touch sensor. As shown in Figure 6, capacitance exists between electrode
to system ground. Touch changes field through human body and creates extra capacitance.
Self-cap touch sensor structure:
• Cs: Intrinsic self-capacitance. 10 - 50 pF as usual.
• ΔCs: Touch generated self-capacitance. 0.3 - 2 pF as usual.
• Sensitivity of sensor: ΔCs/Cs. 1 - 10 % as usual.
2.2 Self-cap sensing mode
There are three modes of self-cap mode:
• Basic self-cap mode
• Noise cancellation mode
• Sensitivity boost mode
The noise cancellation mode and sensitivity boost mode cannot be enabled at same time. The following describes the
three modes.
NXP Semiconductors
TSI self-cap mode introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
User Guide 7 / 37
2.2.1 Basic self-cap sensing mode
sample
ph 1
Digital SINC
filter
Icx
Cx
XIN*Icx
ph 2
Vcx
current mirror: input
TSIx_MODE[S_XIN]
current mirror: charge
TSIx_MODE[S_XCH]
XCH*XIN*Icx
Ci 90pF
Transconductance Amplifier
charge
-
+
Vp
Vm
TSIx_GENC[DVOLT]
Counts
TSIx_DATA[TSICNT]
Vci
IN CHIP
OUT CHIP
I/O
Comparator
Cx = Cs + ΔCs,
Cx is the capacitance of self-cap electrode.
Cs is the self capacitance between touch electrode and ground.
ΔCs is touch generated capacitance.
If no touch happens, Cx = Cs.
TSIx_SINC[CUTOFF]
TSIx_SINC[ORDER]
TSIx_SINC[DECIMATION]
vddlv vdd3v
Figure 7. TSI basic self-cap mode HW architecture
Figure 8. TSI self-cap timing
Inside the TSI IP module, the TSI scan is operated by non-overlapping clock ph1/ph2 and trans-conductance amplifier.
There are two phases controlled by the ph1 and ph2 respectively for the TSI scan module:
• Sample phase: The switch ph1 controls the sample phase. When ph1 turns on, the external touch electrode Cx is charged
by vdd3v.
• Charge phase: The switch ph2 controls the charge phase. When ph1 turns off and then ph2 turns on, the charge on the
capacitor Cx flows to the internal integrated capacitor Ci, which generates the average current Icx.
Via the trans-conductance amplifier, the Icx are amplified to charge Ci and the voltage Vci ramps on Ci. Vci is detected by
comparator, when the Vci becomes larger than the pre-setting Vp, Ci is discharged to negative reference Vm. Then next scanning
cycle continues.
The digital SINC filter controls the scan cycle. The digital SINC filter is a digital decimation filter for filtering out the low frequency
noise from EMC. The digital SINC detects and accumulates the filter number of Vci ramp up steps in per cycle. Digital SINC filter
outputs totally counter which can be read from TSIx_DATA[TSICNT]. The software uses the counts to detect touch.
NXP Semiconductors
TSI self-cap mode introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
User Guide 8 / 37
When touch happens, input capacitance Cx increases. The charging current of Ci becomes larger and then the number of Vci ramp
up steps is reduced. The output count of digital SINC filter is reduced, so the value of TSIx_DATA[TSICNT] is decreased.
2.2.2 Noise cancellation mode of self-cap
If touch sensor encounters strong low frequency noise, noise cancellation can be activated by setting TSIx_MODE[S_NOISE].
In the noise cancellation mode, vdd3v, and vddlv (1.2 V) are dual sample voltages. Two phases exist in noise
cancellation architecture:
• Charging phase of Ci when vdd3v is on and vddlv is off
• Discharging phase of Ci when vdd3v is off and vddlv is on
Two switching clock cycles are cost to samples twice which includes charging phase (sampling vdd3v) and discharging phase
(sampling vddlv). The input current of Ci equal to charging phase current abstract discharging phase current. At the end of each
second phase, low frequency noise is subtracted. In a long integration period, the noise induced error can be canceled.
2.2.3 Sensitivity boost mode of self-cap
The larger parasitic capacitance causes the low sensitivity. The low sensitivity results in the difficulty to recognize the touch event.
For example, when the touch overlay is very thick, it becomes very hard to detect a touch event correctly.
To increase the sensitivity, enable sensitivity-boost feature by removing part parasitic capacitance virtually. So touch works well
under the thicker overlay with sensitivity boost enabled.
The capacitance to be removed cannot be configured more than the intrinsic capacitance of the touch key.
Otherwise, it causes the sensitivity invalid.
NOTE
2.3 Clock generation
The clock generation determines the TSI scan speed. The maximum frequency of TSI is about 10 MHz.
The TSI module is only clocked by the main clock, which is generated by TSI module itself without any other external clock source.
The main clock has four ranges of frequency. It can be divided into the switching clock which is used to control the ph1/ph2
switching speed and finally determines the whole scan time, as shown in Figure 9.
SSC
Main Clock
20.72MHz
16.65MHz
13.87MHz
11.91MHz
SSC_MODE
PRBS SSC
No SSC
Up-down
counter SSC
Touch Key
Switching Clock
SSC_MODE = 10b
SSC_MODE = 00b/01b
basic
advanced
1/ 2
Main Clock
Prescale + 1
Figure 9. Block diagram of clock generation
• When SSC_MODE = 10b, the switching clock is divided from main clock directly, as the basic clock generation.
• When SSC_MODE = 00b/01b, the switching clock is generated from SSC module, as the advanced clock generation.
2.3.1 Basic clock generation
Equation 1 si the basic clock generation, when TSIx_SSC0[SSC_MODE] = 10b.
NXP Semiconductors
TSI self-cap mode introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
User Guide 9 / 37
SwitcℎingClock= MainClock
SSC_PRESCALE_NUM + 1 × 1
2
Equation 1.
Table 4. Main clock setting
Register Value Main clock (MHz)
TSI_MODE[SETCLK]
00 20.72
01 16.65
10 13.87
11 11.91
Table 5. Divider setting
Register Value SSC_PRESCALE_NUM + 1
TSI_SSC0.SSC_PRESCALE_NUM[7:0]
00000000 divide 1
00000001 divide 2
… …
11111111 divide 256
There is an example of the basic clock generation, the main clock as 16.65 MHz, the divider as 16, and the result of switching clock
is 1.04 MHz.
To use no SSC switching clock with frequency of 1 MHz,
• Set SETCLK < 1:0 > to ‘01b’ to get main clock = 16.65 MHz.
• Set SSC_MODE < 1:0 > to ‘10b’ to disable SSC function.
• Set SSC_PRESCALE_NUM < 7:0 > to ‘00000111b’ to get division 8. When SSC mode is disabled, the frequency is
main
clock/[(SSC_PRESCALE_NUM+1) × 2]
.
• Keep other registers in TSIx_SSC0, TSIx_SSC1, and TSIx_SSC2 as default value.
SwitcℎingClock=MainClock
Divider × 1
2=16.65MHz
8 × 1
2 = 1.04MHz
2.3.2 Advanced clock generation, spread spectrum clocking
The Spread Spectrum Clocking (SSC) increases the noise immunity to RF interference and spreads the emissions.
With the SSC enabled (TSIx_SSC0[SSC_MODE] = 00/01b), the switching clock is generated by the SSC module, other than the
direct divided main clock.
In the Self-cap mode, changing the SSC charge time does not affect the final scan result. It changes the total scan time as it
changes the switching clock frequency.
If SSC mode is enabled, the timing of the switching clock generation is as shown in Figure 10.
NXP Semiconductors
TSI self-cap mode introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
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