NXP Semiconductors KE1xF Series Manuel utilisateur

Kinetis KE1xF Sub-Family Reference

Manual

Supports: MKE1xF512VLL16, MKE1xF512VLH16, MKE1xF256VLL16,

MKE1xF256VLH16

Document Number: KE1xFP100M168SF0RM

Rev. 4, 06/2019

Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019

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Contents

Section number Title Page

Chapter 1

About This Manual

1.1 Audience....................................................................................................................................................................... 47

1.2 Organization..................................................................................................................................................................47

1.3 Module descriptions......................................................................................................................................................47

1.3.1 Example: chip-specific information that supersedes content in the same chapter.......................................48

1.3.2 Example: chip-specific information that refers to a different chapter......................................................... 49

1.4 Register descriptions.....................................................................................................................................................50

1.5 Conventions.................................................................................................................................................................. 51

1.5.1 Numbering systems......................................................................................................................................51

1.5.2 Typographic notation................................................................................................................................... 51

1.5.3 Special terms................................................................................................................................................52

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................53

2.2 Block Diagram..............................................................................................................................................................53

2.3 Module Functional Categories......................................................................................................................................54

Chapter 3

Core Overview

3.1 ARM Cortex-M4 ..........................................................................................................................................................57

3.2 Core Buses and Interfaces.............................................................................................................................................58

3.3 Core Component Configuration....................................................................................................................................59

3.4 SysTick Clock Configuration....................................................................................................................................... 59

Chapter 4

Interrupts

4.1 Introduction...................................................................................................................................................................61

4.2 NVIC configuration...................................................................................................................................................... 61

4.2.1 Interrupt priority levels................................................................................................................................ 61

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4.2.2 Non-maskable interrupt................................................................................................................................62

4.3 Interrupt channel assignments.......................................................................................................................................62

4.3.1 Determining the bitfield and register location for configuring a particular interrupt.................................. 66

Chapter 5

System Integration Module (SIM)

5.1 Introduction...................................................................................................................................................................67

5.1.1 Features........................................................................................................................................................ 67

5.2 Memory map and register definition.............................................................................................................................67

5.2.1 Chip Control register (SIM_CHIPCTL)...................................................................................................... 68

5.2.2 FTM Option Register 0 (SIM_FTMOPT0)................................................................................................. 70

5.2.3 ADC Options Register (SIM_ADCOPT).................................................................................................... 72

5.2.4 FTM Option Register 1 (SIM_FTMOPT1)................................................................................................. 74

5.2.5 System Device Identification Register (SIM_SDID)...................................................................................76

5.2.6 Platform Clock Gating Control Register (SIM_PLATCGC).......................................................................77

5.2.7 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 78

5.2.8 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 81

5.2.9 Unique Identification Register High (SIM_UIDH)..................................................................................... 82

5.2.10 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................82

5.2.11 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 83

5.2.12 Unique Identification Register Low (SIM_UIDL)...................................................................................... 83

5.2.13 System Clock Divider Register 4 (SIM_CLKDIV4)...................................................................................84

5.2.14 Miscellaneous Control register (SIM_MISCTRL)...................................................................................... 85

Chapter 6

Miscellaneous Control Module (MCM)

6.1 Introduction...................................................................................................................................................................87

6.1.1 Features........................................................................................................................................................ 87

6.2 Memory map/register descriptions............................................................................................................................... 87

6.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................88

6.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 89

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6.2.3 Core Platform Control Register (MCM_CPCR)..........................................................................................89

6.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 91

6.2.5 Store Buffer Fault address register (MCM_FADR).................................................................................... 94

6.2.6 Store Buffer Fault Attributes register (MCM_FATR).................................................................................94

6.2.7 Store Buffer Fault Data Register (MCM_FDR).......................................................................................... 96

6.2.8 Process ID register (MCM_PID)................................................................................................................. 97

6.2.9 Compute Operation Control Register (MCM_CPO)................................................................................... 98

6.2.10 Local Memory Descriptor Register (MCM_LMDRn).................................................................................99

6.2.11 LMEM Parity & ECC Control Register (MCM_LMPECR)....................................................................... 103

6.2.12 LMEM Parity & ECC Interrupt Register (MCM_LMPEIR).......................................................................104

6.2.13 LMEM Fault Address Register (MCM_LMFAR).......................................................................................105

6.2.14 LMEM Fault Attribute Register (MCM_LMFATR)...................................................................................106

6.2.15 LMEM Fault Data High Register (MCM_LMFDHR)................................................................................ 107

6.2.16 LMEM Fault Data Low Register (MCM_LMFDLR)..................................................................................107

6.3 Functional description...................................................................................................................................................108

6.3.1 Interrupts...................................................................................................................................................... 108

Chapter 7

Crossbar Switch Lite (AXBS-Lite)

7.1 Chip-specific information for this module....................................................................................................................109

7.1.1 Instantiation Information..............................................................................................................................109

7.2 Introduction...................................................................................................................................................................110

7.2.1 Features........................................................................................................................................................ 110

7.3 Memory Map / Register Definition...............................................................................................................................110

7.4 Functional Description..................................................................................................................................................110

7.4.1 General operation.........................................................................................................................................111

7.4.2 Arbitration....................................................................................................................................................111

7.5 Initialization/application information........................................................................................................................... 113

Chapter 8

Memory Protection Unit (MPU)

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Section number Title Page

8.1 Chip-specific information for this module....................................................................................................................115

8.1.1 Instantiation Information..............................................................................................................................115

8.2 Introduction...................................................................................................................................................................116

8.3 Overview.......................................................................................................................................................................116

8.3.1 Block diagram..............................................................................................................................................116

8.3.2 Features........................................................................................................................................................ 117

8.4 Memory map/register definition................................................................................................................................... 118

8.4.1 Control/Error Status Register (MPU_CESR).............................................................................................. 120

8.4.2 Error Address Register, slave port n (MPU_EARn)....................................................................................121

8.4.3 Error Detail Register, slave port n (MPU_EDRn)....................................................................................... 122

8.4.4 Region Descriptor n, Word 0 (MPU_RGDn_WORD0).............................................................................. 123

8.4.5 Region Descriptor n, Word 1 (MPU_RGDn_WORD1).............................................................................. 124

8.4.6 Region Descriptor n, Word 2 (MPU_RGDn_WORD2).............................................................................. 124

8.4.7 Region Descriptor n, Word 3 (MPU_RGDn_WORD3).............................................................................. 127

8.4.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................128

8.5 Functional description...................................................................................................................................................130

8.5.1 Access evaluation macro..............................................................................................................................130

8.5.2 Putting it all together and error terminations............................................................................................... 132

8.5.3 Power management......................................................................................................................................133

8.6 Initialization information.............................................................................................................................................. 133

8.7 Application information................................................................................................................................................133

8.8 Usage Guide..................................................................................................................................................................135

8.8.1 MPU Access Violation Indications..............................................................................................................135

8.8.2 Reset Values for RGD0 Registers................................................................................................................136

8.8.3 Write Access Restrictions for RGD0 Registers........................................................................................... 136

Chapter 9

Peripheral Bridge (AIPS-Lite)

9.1 Chip-specific information for this module....................................................................................................................139

9.1.1 Peripheral slot assignment........................................................................................................................... 139

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9.2 Introduction...................................................................................................................................................................139

9.2.1 Features........................................................................................................................................................ 139

9.2.2 General operation.........................................................................................................................................140

9.3 Memory map/register definition................................................................................................................................... 140

9.3.1 Master Privilege Register A (AIPS_MPRA)............................................................................................... 141

9.3.2 Peripheral Access Control Register (AIPS_PACRn)...................................................................................144

9.3.3 Off-Platform Peripheral Access Control Register (AIPS_OPACRn)..........................................................149

9.3.4 Peripheral Access Control Register (AIPS_PACRU)..................................................................................154

9.4 Functional description...................................................................................................................................................155

9.4.1 Access support............................................................................................................................................. 155

Chapter 10

Trigger MUX Control (TRGMUX)

10.1 Chip-specific information for this module....................................................................................................................157

10.1.1 Module Interconnectivity.............................................................................................................................157

10.2 Introduction...................................................................................................................................................................162

10.2.1 Features........................................................................................................................................................ 162

10.3 Functional description...................................................................................................................................................162

10.4 Memory map and register definition.............................................................................................................................162

10.4.1 TRGMUX0 Register Descriptions...............................................................................................................162

10.4.2 TRGMUX1 Register Descriptions...............................................................................................................201

10.5 Usage Guide..................................................................................................................................................................207

10.5.1 ADC Trigger Source.................................................................................................................................... 207

10.5.2 CMP Window/Sample Input .......................................................................................................................208

10.5.3 FTM Fault Detection Input / Hardware Triggers and Synchronization.......................................................208

Chapter 11

Direct Memory Access Multiplexer (DMAMUX)

11.1 Chip-specific information for this module....................................................................................................................209

11.1.1 Instantiation Information..............................................................................................................................209

11.2 Introduction...................................................................................................................................................................212

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11.2.1 Overview......................................................................................................................................................212

11.2.2 Features........................................................................................................................................................ 212

11.2.3 Modes of operation...................................................................................................................................... 213

11.3 External signal description............................................................................................................................................213

11.4 Memory map/register definition................................................................................................................................... 213

11.4.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 214

11.5 Functional description...................................................................................................................................................215

11.5.1 DMA channels with periodic triggering capability......................................................................................215

11.5.2 DMA channels with no triggering capability...............................................................................................218

11.5.3 Always-enabled DMA sources.................................................................................................................... 218

11.6 Initialization/application information........................................................................................................................... 219

11.6.1 Reset.............................................................................................................................................................219

11.6.2 Enabling and configuring sources................................................................................................................219

Chapter 12

Enhanced Direct Memory Access (eDMA)

12.1 Introduction...................................................................................................................................................................223

12.1.1 eDMA system block diagram...................................................................................................................... 223

12.1.2 Block parts................................................................................................................................................... 224

12.1.3 Features........................................................................................................................................................ 225

12.2 Modes of operation....................................................................................................................................................... 226

12.3 Memory map/register definition................................................................................................................................... 227

12.3.1 TCD memory............................................................................................................................................... 227

12.3.2 TCD initialization........................................................................................................................................ 227

12.3.3 TCD structure...............................................................................................................................................227

12.3.4 Reserved memory and bit fields...................................................................................................................228

12.3.5 Control Register (DMA_CR).......................................................................................................................239

12.3.6 Error Status Register (DMA_ES)................................................................................................................ 242

12.3.7 Enable Request Register (DMA_ERQ)....................................................................................................... 244

12.3.8 Enable Error Interrupt Register (DMA_EEI)...............................................................................................246

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12.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 249

12.3.10 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 250

12.3.11 Clear Enable Request Register (DMA_CERQ)...........................................................................................250

12.3.12 Set Enable Request Register (DMA_SERQ)...............................................................................................251

12.3.13 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................252

12.3.14 Set START Bit Register (DMA_SSRT)...................................................................................................... 253

12.3.15 Clear Error Register (DMA_CERR)............................................................................................................254

12.3.16 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 255

12.3.17 Interrupt Request Register (DMA_INT)......................................................................................................256

12.3.18 Error Register (DMA_ERR)........................................................................................................................ 258

12.3.19 Hardware Request Status Register (DMA_HRS)........................................................................................ 261

12.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................264

12.3.21 Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 266

12.3.22 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................267

12.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................267

12.3.24 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................268

12.3.25 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 269

12.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)

(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................270

12.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)

(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 271

12.3.28 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................272

12.3.29 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................273

12.3.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................273

12.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_CITER_ELINKYES)...........................................................................................................274

12.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 275

12.3.33 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 276

12.3.34 TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 277

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12.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_BITER_ELINKYES)...........................................................................................................279

12.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 280

12.4 Functional description...................................................................................................................................................281

12.4.1 eDMA basic data flow................................................................................................................................. 281

12.4.2 Fault reporting and handling........................................................................................................................284

12.4.3 Channel preemption..................................................................................................................................... 287

12.4.4 Performance................................................................................................................................................. 287

12.5 Initialization/application information........................................................................................................................... 291

12.5.1 eDMA initialization..................................................................................................................................... 291

12.5.2 Programming errors..................................................................................................................................... 293

12.5.3 Arbitration mode considerations..................................................................................................................294

12.5.4 Performing DMA transfers.......................................................................................................................... 294

12.5.5 Monitoring transfer descriptor status........................................................................................................... 298

12.5.6 Channel Linking...........................................................................................................................................300

12.5.7 Dynamic programming................................................................................................................................ 301

12.5.8 Suspend/resume a DMA channel with active hardware service requests....................................................305

12.6 Usage Guide..................................................................................................................................................................306

Chapter 13

Memory and memory map

13.1 Introduction...................................................................................................................................................................307

13.2 Flash memory............................................................................................................................................................... 309

13.2.1 Flash memory types..................................................................................................................................... 309

13.2.2 Flash Memory Sizes.....................................................................................................................................309

13.3 SRAM memory.............................................................................................................................................................310

13.3.1 SRAM sizes..................................................................................................................................................310

13.3.2 SRAM retention in low power modes..........................................................................................................310

13.3.3 SRAM accesses............................................................................................................................................310

13.3.4 SRAM arbitration and priority control.........................................................................................................311

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