Texas Instruments AFE79 Series Manuel utilisateur

User’s Guide

AFE79xx SPI Bringup Guide With Xilinx FPGAs

ABSTRACT

This tutorial guides through the process of using Xilinx Vivado and Vitis development environments along

with Texas Instruments supplied custom IP to bring up Serial Peripheral Interface (SPI) and non-timing critical

General-Purpose Outputs (GPOs) for Texas Instruments AFE79xx EVM along with the companion LMK series

clocking chip, thereby enabling an easier integration of the AFE79xx device into a system design. This guide will

demonstrate how to use a Xilinx ZCU102 setup as an example.

Table of Contents

1 Introduction.............................................................................................................................................................................2

2 Prerequisites........................................................................................................................................................................... 2

3 Typical Bare-Metal Design Flow............................................................................................................................................ 3

4 Background.............................................................................................................................................................................4

5 AFE SPI IP Container Pinout..................................................................................................................................................5

6 TI AFE SPI IP Container..........................................................................................................................................................6

7 Create Block Designs With TI AFE SPI IP.............................................................................................................................7

8 Create New Platforms in Vitis ............................................................................................................................................. 11

9 Create New Application Projects in Vitis............................................................................................................................14

10 Build Application Projects................................................................................................................................................. 18

11 Configure the AXI GPIO......................................................................................................................................................19

11.1 Initializing the GPIO........................................................................................................................................................19

11.2 Setting the Direction....................................................................................................................................................... 19

11.3 Setting High or Low for Corresponding Bits................................................................................................................... 19

12 Configure the AXI SPI.........................................................................................................................................................20

13 Create Boot Images to Run on SD Card........................................................................................................................... 21

14 Set up and Power on Hardware.........................................................................................................................................23

15 Set up ZCU102 Board Interface for VADJ_FMC............................................................................................................... 24

16 Debug Application Projects and Set up Vitis Serial Terminal........................................................................................ 26

17 Execute the Application..................................................................................................................................................... 27

Trademarks

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AFE79xx SPI Bringup Guide With Xilinx FPGAs 1

1 Introduction

This user guide is a walk-through of complete hardware and software flow to bring up SPI and GPO with TI

supplied AFE SPI IP. The hardware in this case refers to the AFE SPI IP supplied by TI which uses a Microblaze

processor along with AXI SPI, AXI GPIO, and other required peripherals. Shielding end-customer from the

nuances of this setup is one of the core objectives in packaging these in a single custom IP container.

The specific step-wise objectives are as follows:

• Instantiate TI supplied AFE SPI IP in a Vivado project

• Map the supplied IP's required signals to FPGA IOs

• Import hardware design and building a new Vitis application project for software development

• Compile, link, and download C program to processor along with bit file for FPGA

2 Prerequisites

For effective use of this documentation, ensure to have the following prerequisites:

• Xilinx Vitis IDE v2020.1.0 (or higher)

• Xilinx Vivado v2020.1.0 (or higher)

• Xilinx FPGA board along with TI AFE EVM

• FPGA bit file download/debug programmer

• USB-UART cable for debug terminal

• TI supplied AFE SPI IP

• TI supplied C-APIs

Table 2-1. Prerequisites

TI AFE AFE79xx

Sample Configuration 2T-2R-1FB

Lanes 2 RX lanes (1RX, 1FB) and 2 TX lanes at 5 Gbps

AFE EVM AFE79xx EVM

FPGA Board Xilinx ZCU102 EVM

Introduction www.ti.com

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3 Typical Bare-Metal Design Flow

Create New Project

Add User HDL, Ips, and Constraints

Add TI AFE SPI IP

Interconnect AFE SPI IP with User HDL

Create HDL Wrapper

Generate Output Files

Generate Bit Stream

Export Hardware

Create New Platform Project

(Import Hardware and Create BSP)

Create New C Application

Write the system specific application code

Include C headers and source files from TI

Supplied C-APIs

Initialize AXI Peripherals of

TI AFE SPI IP

Build Application

Configure FPGA

Launch or Run on Hardware

Vivado

Environment

Vitis

Environment

Figure 3-1. Bare-Metal Design Flow

www.ti.com Typical Bare-Metal Design Flow

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AFE79xx SPI Bringup Guide With Xilinx FPGAs 3

4 Background

This example uses a soft core Microblaze because the Microblaze can be instantiated in most of the Xilinx FPGA

families. The SPI, UART, and GPIO AXI blocks run on relatively lower frequency AXI clocks. As seen in Figure

4-1, the AXI peripherals are controlled by a Microblaze block through smart interconnects.

Figure 4-1. Internal Block Diagram of TI AFE SPI IP

The interconnection of various submodules within this IP block diagram is similar to typical Microblaze

implementations. The HP port of the Microblaze drives AXI peripherals. The clocking of the entire IP is expected

from a 100-MHz differential clock source. This example uses a 100-MHz differential clock source because this

clock is typically available as ‘user clock’ in most FPGA EVMs. All other clock frequencies are derived internally

through a clocking wizard.

Background www.ti.com

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5 AFE SPI IP Container Pinout

Table 5-1. Pinout Signals and Connections

SIGNALS DIRECTION EXTERNAL CONNECTIONS

SPI0_SCLK, SPI0_SDO*, SPI0_SEN Output AFE SPI lines (_SDO* to SDI of AFE)

SPI0_SDI Input AFE SDO

SPI1_SCLK, SPI1_SDO, SPI1_SEN Output LMK SPI lines

RSTZ Output RESETn of AFE

JESD RSTn

JESD TXRST Output JESED IP Cores RSTn and TX Rst

RXD Input UART Terminal TX for debug

TXD Output UART Terminal RX for debug

diff_clock_rtl Input 100-Mhz differential clocking

Reset_rtl Input Reset (Active High) typically connected to FPGA board

reset

www.ti.com AFE SPI IP Container Pinout

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AFE79xx SPI Bringup Guide With Xilinx FPGAs 5

6 TI AFE SPI IP Container

By default, custom and user-added IPs are not visible in IP catalog of Vivado. The locations for these IPs must

be configured manually. To configure the IP locations manually, follow these steps:

1. Open the Project Manager menu and click Settings (see Figure 6-1).

Figure 6-1. Project Manager Settings

2. Click the + icon to add the location of TI provided IP (see Figure 6-2).

Figure 6-2. Adding IP Repository

TI AFE SPI IP Container www.ti.com

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7 Create Block Designs With TI AFE SPI IP

The IP is expected to be used only within a block design. Users can create a new block design or instantiate the

IP within an existing one. To create a new block design with the IP, follow these steps:

1. Open the IP INTEGRATOR menu and click Create Block Design (see Figure 7-1).

Figure 7-1. Creating Block Design

2. Enter the desired design name (see Figure 7-2) and keep the other two options as defaults. Click OK.

Figure 7-2. Naming of Block Design

3. Click the IP Catalog tab and notice the User Repository header (see Figure 7-3). The header appears only if

the inclusion of the IP repository is done correctly, as explained in previous steps.

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AFE79xx SPI Bringup Guide With Xilinx FPGAs 7

Figure 7-3. User Repository

4. Double-click AFE79xx SPI Configurator to launch the Add IP window.

5. Click Add IP to Block Design (see Figure 7-4).

Figure 7-4. Adding IP to Block Design

6. The AFE SPI IP shows up in the block design (see Figure 7-5) if the previous steps were followed correctly.

Create Block Designs With TI AFE SPI IP www.ti.com

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Figure 7-5. Final Diagram

The required IOs from the IP must be brought to the top-level file in the FPGA hdl design hierarchy. To do this,

first make the required IOs as external. To make the required IOs as external, right-click the individual IOs of

interest and select Make External (see Figure 7-6).

Figure 7-6. Making IOs External

In the above implementation example, the bare minimum required IOs are brought out as external.

The block design must then be validated for any errors and output products to generate. To validate the block

diagram, right-click the block design under the Design Sources header.

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AFE79xx SPI Bringup Guide With Xilinx FPGAs 9

Similarly, right-click the View Instantiation Template to use as a reference for wiring this block design on the top

level hdl (see Figure 7-7).

Figure 7-7. TI SPI Configurator Pinout

The IOs from the top level hdl which are connected to this IP must be declared in a Constraints file for them to

be mapped to the hardware design, specific FPGA pins, and the correct IO levels.

The above steps complete the hardware design using TI AFE SPI IP.

Create Block Designs With TI AFE SPI IP www.ti.com

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