Texas Instruments MSP430F4152IPM Manuel utilisateur

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

DLow Supply-Voltage Range, 1.8 V to 3.6 V

DUltralow Power Consumption

Active Mode: 220 Aat1MHz,2.2V

Standby Mode: 0.9 A

Off Mode (RAM Retention): 0.1 A

DFive Power-Saving Modes

DWake-Up From Standby Mode in Less

Than 6 s

-- Internal Very Low Power,

Low-Frequency Oscillator

D16-Bit RISC Architecture,

125-ns Instruction Cycle Time

D16-Bit Timer_A With Three

Capture/Compare Registers

D16-Bit Timer_A With Five Capture/Compare

Registers

DTwo Universal Serial Communication

Interfaces (USCIs)

USCI_A0

-- Enhanced UART Supporting

Auto-Baudrate Detection

-- IrDA Encoder and Decoder

-- Synchronous SPI

USCI_B0

-- I 2 C

-- Synchronous SPI

DSupply Voltage Supervisor/Monitor With

Programmable Level Detection

DIntegrated LCD Driver With Contrast

Control for Up to 144 Segments

DBasic Timer With Real Time Clock Feature

DBrownout detector

DOn-Chip Comparator for Analog Signal

Compare Function or Slope A/D

D10-Bit 200-ksps Analog-to-Digital (A/D)

Converter With Internal Reference,

Sample-and-Hold, Autoscan, and Data

Transfer Controller

DSerial Onboard Programming,

No External Programming Voltage Needed

Programmable Code Protection by Security

Fuse

DBootstrap Loader

DOn-Chip Emulation Module

DFamily Members Include:

MSP430F4152: 16KB+256B Flash Memory

512B RAM

MSP430F4132: 8KB+256B Flash Memory

512B RAM

DAvailable in 64-Pin QFP Package and

48-Pin QFN Package (See Available

Options)

DFor Complete Module Descriptions, See

The MSP430x4xx Family User’s Guide,

Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generator that contribute to maximum code

efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less

than 6 s.

The MSP430F41x2 is a microcontroller configuration with two 16-bit timers, a basic timer with a real--time clock,

a 10-bit A/D converter, a versatile analog comparator, two universal serial communication interfaces, up to 48

I/O pins, and a liquid crystal display driver.

Typical applications for this device include analog and digital sensor systems, remote controls, thermostats,

digital timers, hand-held meters, etc.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range

from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage

because very small parametric changes could cause the device not to meet its published specifications. These devices have limited

built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

2POST OFFICE BOX 655303 DALLAS, TEXAS 75265

AVAILABLE OPTIONS†

PACKAGED DEVICES‡

TAPLASTIC 64-PIN QFP (PM) PLASTIC 48-PIN QFN (RGZ)

-- 4 0 Cto85CMSP430F4152IPM

MSP430F4132IPM

MSP430F4152IRGZ

MSP430F4132IRGZ

†For the most current package and ordering information, see the Package Option

Addendum at the end of this document, or see the TI web site at www.ti.com.

‡Package drawings, thermal data, and symbolization are available at

www.ti.com/packaging.

DEVELOPMENT TOOL SUPPORT

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging

and programming through easy to use development tools. Recommended hardware options include the

following:

DDebugging and Programming Interface

-- MSP-FET430UIF (USB)

-- MSP-FET430PIF (Parallel Port)

DDebugging and Programming Interface with Target Board

-- MSP-FET430U64A (PM package)

DProduction Programmer

-- MSP-GANG430

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

pin designation, MSP430F41x2IPM (QFP)

64 63

P6.1/UCB0SOMI/UCB0SCL

P6.2/UCB0SIMO/UCB0SDA

P6.3/UCB0STE/UCA0CLK/A3/CA5/VeREF-/VREF-

XIN

XOUT

P4.6/S1

P4.5/S2

P4.4/S3

P4.3/S4

P4.2/S5

P4.1/S6

P4.0/S7

P2.7/S8

P2.6/S9

P2.5/S10

P2.4/S11

P2.3/TA1.4/S12

P2.2/TA1.3/S13

P2.1/TA1.2/S14

P2.0/TA1.1/S15

P3.7/S16

P3.6/S17

P3.5/S18

P3.4/CAOUT/S19

P3.3/TA0.0/TA1CLK/S20

P3.2/TA1.4/S21

P5.7/COM0

P5.6/COM1

P5.5/COM2

P5.4/COM3

P5.3/R03

P5.2/R13/LCDREF

P5.1/R23

R33/LCDCAP

AVCC

P6.0/TA1.2/A2/CA4

P7.5/TA1.3/A1/CA3

P7.4/TA1.4/A0/CA2

RST/NMI/SBWTDIO

P7.3/TCK/S35

P7.2/TMS/S34

P7.1/TDI/TCLK/S33

P7.0/TDO/TDI/S32

P1.0/TA0.0/S31

P1.1/TA0.0/MCLK/S30

62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

P3.1/TA1.3/S22

P3.0/TA1.2/S23

P5.0/TA1.1/S24

P4.7/ADC10CLK/S0

P1.4/TA1.0/S27

P1.2/TA0.1/S29

P1.3/TA1.0/SVSOUT/S28

P6.4/UCB0CLK/UCA0STE/A4/CA6/VeREF+/VREF+

P6.5/UCA0RXD/UCA0SOMI/A5

64-pin

PM PACKAGE

(TOP VIEW)

P6.7/A7/CA7/SVSIN

P7.6/TA0.2/S25

TEST/SBWTCLK

P6.6/UCA0TXD/UCA0SIMO/A6

AVSS

DVCC

DVSS

P1.7/TA0CLK/CAOUT/CA1

P1.5/TA0CLK/CAOUT/S26

P1.6/ACLK/CA0

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

4POST OFFICE BOX 655303 DALLAS, TEXAS 75265

pin designation, MSP430F41x2IRGZ (QFN)†

XIN

XOUT

P4.6/S1

P4.5/S2

P4.4/S3

P4.3/S4

P4.2/S5

P4.1/S6

P4.0/S7

P2.7/S8

P2.6/S9

P2.5/S10

P2.4/S11

P2.3/TA1.4/S12

P2.2/TA1.3/S13

P2.1/TA1.2/S14

P2.0/TA1.1/S15

P5.7/COM0

P5.6/COM1

P5.5/COM2

P5.4/COM3

P5.3/R03

P5.2/R13/LCDREF

P5.1/R23

R33/LCDCAP

AVCC

RST/NMI/SBWTDIO

P4.7/ADC10CLK/S0

TEST/SBWTCLK

AVSS

DVCC

DVSS 48-pin

RGZ PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

P6.0/TA1.2/A2/CA4

P7.5/TA1.3/A1/CA3

P7.4/TA1.4/A0/CA2

P1.0/TA0.0/S31

P1.7/TA0CLK/CAOUT/CA1

P1.6/ACLK/CA0

P6.1

P6.2

P6.7/A7/CA7/SVSIN

P7.3/TCK/S35

P7.2/TMS/S34

P7.1/TDI/TCLK/S33

P7.0/TDO/TDI/S32

P3.4/CAOUT/S19

P1.1/TA0.0/MCLK/S30

P1.5/TA0CLK/CAOUT/S26

†“Not available” pins in the 48-pin package should be initialized to output direction.

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

functional block diagram

Oscillators

FLL+

VLO

Brownout

Protection

SVS,

SVM

RST/NMI

DVCC DVSS

MCLK

Watchdog

WDT+

15--Bit

Timer _A5

5CC

Registers

CPU

64kB

incl. 16

Registers

EEM

JTAG

Interface

Basic

Timer &

Real--

Time

Clock

LCD_A

144

Segments

1,2,3,4

Mux

Comparator

_A+

AVCC AVSS P1.x/P2.x

2x8

P3.x/P4.x

2x8

SMCLK

ACLK

MDB

MAB

Ports

P1/P2

2x8 I/O

Interrupt

capability

XIN XOUT

RAM

512B

Flash

16kB

8kB

USCI A0

UART/

LIN,

IrDA, SPI

USCI B0

SPI, I2C

Ports

P3/P4

2x8 I/O

ADC10

10--bit

8 Channels

Autoscan

DTC

Timer _A3

3CC

Registers

Ports

P5/P6

2x8 I/O

P5.x/P6.x

2x8

S p y --B i --

Wire

Port

1x7 I/O

1x7

P7.x

NOTE: The USCI A0 and USCI B0 cannot be used in the 48-pin package options (RGZ).

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

6POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NO.

NAME 64

P1.0/TA0.0/S31 53 37 I/O

General-purpose digital I/O pin

Timer0_A3, capture: CCI0A input, compare: Out0 output

LCD segment output

P1.1/TA0.0/

MCLK/S30 52 36 I/O

General-purpose digital I/O pin

Timer0_A3, capture: CCI0B input

MCLK signal output

LCD segment output

P1.2/TA0.1/S29 51 -- I/O

General-purpose digital I/O pin

Timer0_A3, capture: CCI1A input, compare: Out1 output

LCD segment output

P1.3/TA1.0/

SVSOUT/S28 50 -- I/O

General-purpose digital I/O pin

Timer1_A5, capture: CCI0B input

SVS comparator output

LCD segment output

P1.4/TA1.0/S27 49 -- I/O

General-purpose digital I/O pin/

Timer1_A5, capture: CCI0A input, compare: Out0 output

LCD segment output

P1.5/TA0CLK/

CAOUT/S26 48 35 I/O

General-purpose digital I/O pin

Timer0_A3, clock signal TACLK input

Comparator_A output

LCD segment output

P1.6/ACLK/CA0 47 34 I/O

General-purpose digital I/O pin

Comparator_A input 0

ACLK signal output

P1.7/TA0CLK

CAOUT/CA1 46 33 I/O

General-purpose digital I/O pin

Timer0_A3, clock signal TACLK input

Comparator_A output

Comparator_A input 1

P2.0/TA1.1/S15 27 23 I/O

General-purpose digital I/O pin

Timer1_A5, compare: Out1 Output

LCD segment output

P2.1/TA1.2/S14 26 22 I/O

General-purpose digital I/O pin

Timer1_A5, compare: Out2 Output

LCD segment output

P2.2/TA1.3/S13 25 21 I/O

General-purpose digital I/O pin

Timer1_A5, compare: Out3 Output

LCD segment output

P2.3/TA1.4/S12 24 20 I/O

General-purpose digital I/O pin

Timer1_A5, compare: Out4 output

LCD segment output

P2.4/S11 23 19 I/O General-purpose digital I/O pin

LCD segment output

P2.5/S10 22 18 I/O General-purpose digital I/O pin

LCD segment output

P2.6/S9 21 17 I/O General-purpose digital I/O pin

LCD segment output

P2.7/S8 20 16 I/O General-purpose digital I/O pin

LCD segment output

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

NO.

NAME 64

P3.0/TA1.2/S23 35 -- I/O

General-purpose digital I/O pin

Timer1_A5, capture: CCI2A input, compare: Out2 output

LCD segment output

P3.1/TA1.3/S22 34 -- I/O

General-purpose digital I/O pin

Timer1_A5, capture: CCI3A input, compare: Out3 output

LCD segment output

P3.2/TA1.4/S21 33 -- I/O

General-purpose digital I/O pin

Timer1_A5, capture: CCI4A input, compare: Out4 output

LCD segment output

P3.3/TA0.0/

TA1CLK/S20 32 -- I/O

General-purpose digital I/O pin

Timer0_A3, compare: Out0 output

Timer1_A5, clock signal TACLK input

LCD segment output

P3.4/CAOUT/S19 31 24 I/O

General-purpose digital I/O pin

Comparator_A output

LCD segment output

P3.5/S18 30 -- I/O General-purpose digital I/O pin

LCD segment output

P3.6/S17 29 -- I/O General-purpose digital I/O pin

LCD segment output

P3.7/S16 28 -- I/O General-purpose digital I/O pin

LCD segment output

P4.0/S7 19 15 I/O General-purpose digital I/O pin

LCD segment output

P4.1/S6 18 14 I/O General-purpose digital I/O pin

LCD segment output

P4.2/S5 17 13 I/O General-purpose digital I/O pin

LCD segment output

P4.3/S4 16 12 I/O General-purpose digital I/O pin

LCD segment output

P4.4/S3 15 11 I/O General-purpose digital I/O pin

LCD segment output

P4.5/S2 14 10 I/O General-purpose digital I/O pin

LCD segment output

P4.6/S1 13 9I/O General-purpose digital I/O pin

LCD segment output

P4.7/ADC10CLK/

S0 12 8I/O

General-purpose digital I/O pin

ADC10, conversion clock

LCD segment output

P5.0/TA1.1/S24 44 -- I/O

General-purpose digital I/O pin

Timer1_A5, capture: CCI1A input, compare: Out1 output

LCD segment output

LCDCAP/R33 43 32 I/O Capacitor connection for LCD charge pump

input port of the most positive analog LCD level (V4)

P5.1/R23 42 31 I/O General-purpose digital I/O pin

input port of the second most positive analog LCD level (V3)

P5.2/LCDREF/

R13 41 30 I/O

General-purpose digital I/O pin

External LCD reference voltage input

input port of the third most positive analog LCD level (V3 or V2)

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

8POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

NO.

NAME 64

P5.3/R03 40 29 I/O General-purpose digital I/O pin

input port of the fourth most positive analog LCD level (V1)

P5.4/COM3 39 28 I/O General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

P5.5/COM2 38 27 I/O General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

P5.6/COM1 37 26 I/O General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

P5.7/COM0 36 25 I/O General-purpose digital I/O pin

common output, COM0--3 are used for LCD backplanes

P6.0/TA1.2/A2†/

CA4 63 47 I/O

General-purpose digital I/O pin

Timer1_A5, compare: Out2 output

ADC10 analog input A2†

Comparator_A input 4

P6.1/

UCB0SOMI†/

UCB0SCL†

1 1 I/O General-purpose digital I/O pin

USCI B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode†

P6.2/

UCB0SIMO†/

UCB0SDA†

2 2 I/O General-purpose digital I/O pin

USCI B0 slave in/master out in SPI mode, SDA I2CdatainI

2C mode†

P6.3/UCB0STE/

UCA0CLK/A3/

CA5/Veref--/Vref--

3-- I/O

General-purpose digital I/O pin

USCI B0 slave transmit enable/USCI A0 clock input/output

ADC10 analog input A3 / negative reference

Comparator_A input 5

P6.4/UCB0CLK/

UCA0STE/A4/

CA6/Veref+/Vref+

4-- I/O

General-purpose digital I/O pin

USCI B0 clock input/output, USCI A0 slave transmit enable

ADC10 analog input A4/ positive reference

Comparator_A input 6

P6.5/UCA0RXD/

UCA0SOMI/A5 5-- I/O

General-purpose digital I/O pin

USCI A0 receive data input in UART mode, slave data out/master in in SPI mode

ADC10 analog input A5

P6.6/UCA0TXD/

UCA0SIMO/A6 6-- I/O

General-purpose digital I/O pin

USCI A0 transmit data output in UART mode, slave data in/master out SPI mode

ADC10 analog input A6

P6.7/A7/CA7/

SVSIN 11 7I/O

General-purpose digital I/O pin

ADC10 analog input A7

Comparator_A input 7

SVS input

P7.0/TDO/TDI/

S32

54 38 I/O General-purpose digital I/O pin

JTAG test data output terminal or test data input in programming an test

LCD segment output

P7.1/TDI/TCLK/

S33

55 39 I/O General-purpose digital I/O pin

JTAG test data input or test clock input in programming an test

LCD segment output

P7.2/TMS/S34 56 40 I/O General-purpose digital I/O pin

JTAG test mode select, input terminal for device programming and test

LCD segment output

†64-pin package devices only

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

Terminal Functions (continued)

TERMINAL

NO.

NAME 64

P7.3/TCK/S35 57 41 I/O General-purpose digital I/O pin

Test clock input for device programming and test

LCD segment output

P7.4/TA1.4/

A0/CA2 60 44 I/O

General-purpose digital I/O pin

Timer1_A5, capture: CCI4B input, compare: Out4 output

ADC10 analog input A0

Comparator_A input 2

P7.5/TA1.3/

A1/CA3 61 45 I/O

General-purpose digital I/O pin

Timer1_A5, capture: CCI3B input, compare: Out3 output

ADC10 analog input A1

Comparator_A input 3

P7.6/TA0.2/S25 45 -- I/O

General-purpose digital I/O pin

Timer0_A3, capture: CCI2A input, compare: Out2 output

LCD segment output

AVCC 64 48 Analog supply voltage, positive terminal

AVSS 62 46 Analog supply voltage, negative terminal

DVCC 7 3 Digital supply voltage, positive terminal. Supplies all digital parts.

DVSS 10 6Digital supply voltage, negative terminal. Supplies all digital parts.

XOUT 9 5 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.

XIN 8 4 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

RST/NMI/

SBWTDIO

58 42 IReset or nonmaskable interrupt input

Spy-Bi-Wire test data input/output during programming and test

TEST/SBWTCLK 59 43 ISelects test mode for JTAG pins on Port7. The device protection fuse is connected to TEST.

Thermal Pad NA NA NA QFN package pad (RGZ package only). Connection to DVSS is recommended.

General-Purpose Register

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-Purpose Register

R10

R11

General-Purpose Register

R14

R15

MSP430F41x2

MIXED SIGNAL MICROCONTROLLER

SLAS648E -- APRIL 2009 -- REVISED MARCH 2011

10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

short-form description

CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator, respectively. The

remaining registers are general-purpose

registers.

Peripherals are connected to the CPU using data,

address, and control buses and can be handled

with all instructions.

instruction set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats; Table 2 shows the address

modes.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5

Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC

Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) —> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)

Absolute F F MOV&MEM,&TCDAT M(MEM) —> M(TCDAT)

Indirect FMOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)

Indirect

autoincrement FMOV @Rn+,Rm MOV @R10+,R11 M(R10) —> R11

R10+2—>R10

Immediate FMOV #X,TONI MOV #45,TONI #45 —> M(TONI)

NOTE: S = source, D = destination

Ce manuel convient aux modèles suivants

Table des matières

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