Texas Instruments AFE722 Series Manuel utilisateur

TSW1200

TSW3100

6V Power

Input

ADC Input for

ChA and ChB

DAC Outputs

for ChA and ChB

IQ Modulator

Output LO Input

Power Supply Jumpers

for LDO/DCDC, iQ Mod

and CDCE72010

Clock

Inputs

USB

AUX ADC and

DAC

User's Guide

SLOU330–December 2011

EVM Description

The AFE722x EVM includes a great level of flexibility to enable the user to test it in a more system like

environment. The individual power rails can be generated through LDOs or DC/DC converters from a 6 V

power source and the EVM clock architecture allows for external clock input as well as clock generation

using a low jitter PLL in combination with a VCXO. On the transmit side the EVM provides the option of

connecting directly to the DAC outputs or perform up-conversion via on board IQ modulator.

On the digital side the EVM provides a seamless interface to the TSW1200 capture card in order to

evaluate received data directly on a PC. The TSW3100 pattern generation card can be used to provide

data to the dual DAC of the AFE722x and the on board CDCE72010 generates the appropriate clock for

the TSW3100 for synchronous operation. Both AFE722x and CDCE72010 can be programmed via SPI

conveniently through the USB connection.

SLOU330–December 2011 EVM Description

Software Installation

www.ti.com

Contents

1 Software Installation ........................................................................................................ 2

2 AFE722x.ini file for TSW1200 ............................................................................................. 3

3 AFE722x EVM Software - SPI Control ................................................................................... 3

4 Initial EVM Setup and Basic Test Procedure ............................................................................ 4

4.1 CDCE72010 Configuration ....................................................................................... 4

4.2 RX Path Using TSW1200 ......................................................................................... 5

4.3 TX Path Using TSW3100 ......................................................................................... 6

5 Power Supply Options ...................................................................................................... 9

6 Clocking Configuration ..................................................................................................... 9

6.1 Non-VCXO Option (default) ..................................................................................... 10

6.2 System Level ...................................................................................................... 11

6.3 RX Only ............................................................................................................ 11

6.4 RX and TX Independent Clocking .............................................................................. 11

6.5 Interpolation on the DAC ........................................................................................ 11

6.6 Decimation on the ADC .......................................................................................... 12

7 RX Setup ................................................................................................................... 12

8 TX Setup .................................................................................................................... 13

9 Trouble Shooting of the EVM Setup .................................................................................... 15

List of Figures

List of Tables

1 Control Registers............................................................................................................ 6

2 Clock Delays for Listed DAC Sampling Rates .......................................................................... 7

3 IP Address Digit Selection Using SW2 ................................................................................. 17

1 Software Installation

1. Open folder named AFE722x_Installer_vxpx (xpx represents the latest version)

2. Run Setup.exe

3. Follow the on-screen instructions

4. Once installed, launch by clicking on the AFE722x_GUI_vxpx program in Start >Texas Instruments

ADCs.

5. When plugging in the USB cable for the first time, the user will be prompted to install the USB drivers

for ‘USB Serial Converter’and ‘USB Serial Port’(see ).

(a) Follow the on-screen instructions to install the USB drivers.

(b) If needed, you can access the drivers directly in the install directory

2EVM Description SLOU330–December 2011

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Tabs to control basic

setup, RX and TX

& SYNC registers as

well as CDCE72010

Individual control

registers

Control to send or read all registers

(AFE722x and CDCE72010) as well

as load or save register files.

Reset USB port on FTDI

chip – required after power

up of AFE722x EVM.

Summary of current registers being written showing 12bit

address & 8bit data in hex format as well as 8bit in binary format.

Warning indication that USB

communication is not established.

www.ti.com

AFE722x.ini file for TSW1200

2 AFE722x.ini file for TSW1200

The AFE722x software package comes with a new ini file for the TSW1200. This AFE722x.ini file should

be placed manually into the following directory in order for the TSW1200 to recognize it: C:\Program

Files\Texas Instruments\TSW1200\ADC Files

3 AFE722x EVM Software - SPI Control

The AFE722x EVM software controls the AFE722x and CDCE72010 on the EVM via SPI register writes

through a USB connection with the PC. Below is a snapshot of the GUI front panel highlighting the various

tabs to control the setup of AFE722x as well as CDCE72010.

It is required to perform a USB reset after applying power to the EVM to establish proper connection with

the PC. A warning sign on the bottom right will flash otherwise indicating USB communication failure.

The EVM software also provides the option to save all registers to a file or to load registers from a file.

SLOU330–December 2011 EVM Description

CDC

AUX IN

CDCE72010

AFE722x

TSW3100

368.64MHz

122.88MHz

92.16MHz

Initial EVM Setup and Basic Test Procedure

www.ti.com

4 Initial EVM Setup and Basic Test Procedure

The fastest way to get the AFE722x EVM up and running is to follow this operating procedure:

•Two signal generators should be connected to the clock and data input of the EVM - preferably with

band pass filter and 10MHz reference locked for coherency.

•Clock input should be connected to ‘CDC AUX IN’input for AUX clock setup and the clock generator

amplitude should be set to ~10-13dBm.

•TSW1200 (RX) capture card should be plugged in AFE722x EVM and connected to the PC via USB.

•TSW3100 (TX) pattern generation card plugged into AFE722x EVM and connected to PC via Ethernet

cable.

•All appropriate power supplies should be connected –blue LED (D2) on AFE722x EVM indicating

power good status.

•After performing USB reset in AFE722x EVM software, the flashing USB warning sign should

disappear indicating successful USB communication.

4.1 CDCE72010 Configuration

The initial EVM setup is configured so that the AFE722x can be operated at any desired sampling rate.

Since the TSW3100 requires an external clock at ¾of the AFE clock rate (see clocking section) the

external clock applied to the ‘CDC AUX IN’connector needs to be 3x the AFE sampling rate (e.g.

368.64MHz for 122.88MHz operation). Loading a preconfigured register file (‘AUX IN - div3 AFE div4

TSW.txt’) to the CDCE72010, it then sets the dividers so that a /3 copy of the input clock is routed to the

AFE722x clock input and a /4 copy to the TSW3100.

4EVM Description SLOU330–December 2011

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The section controls the setup of the digital

interface as well as test modes and digital

features such as decimation and loopback

The general setup tab includes

controls for the digital RX interface

www.ti.com

Initial EVM Setup and Basic Test Procedure

4.2 RX Path Using TSW1200

First the AFE722x digital interface needs to be configured to match the serial LVDS interface that the

TSW1200 is expecting. The following control registers need to be set in the ‘General Setup’tab of the

AFE722x programming software. Also the USB communication warning sign should be monitored after the

USB reset to ensure proper communication with the AFE722x EVM.

Interface Serial LVDS

Master Override Enabled

Format Offset Binary

Serial LVDS 2 Wire

Data Orientation MSB First

SDR Mode Disabled

Wordwise Output Disabled

Bitwise RX Disabled

Halfrx in 2wire Disabled

In the TSW1200 software, the AFE722x should be selected as the ADC. Next the sampling rate and ADC

input frequency need to be entered and the TSW1200 software will calculate the coherent frequency.

Performing a capture should yield:

Fs=122.88Msps

Fin= 9.98625MHz

SLOU330–December 2011 EVM Description

Select AFE722x

for ADC

Perform FFT

capture

Enter ADC

sampling rate

Enter desired

input frequency

DCLK

Data

Initial EVM Setup and Basic Test Procedure

www.ti.com

4.3 TX Path Using TSW3100

First the AFE722x digital interface needs to be configured to match the serial LVDS interface from the

TSW3100.

The following control registers need to be set in the ‘General Setup’tab of the AFE722x programming

software. Also the USB communication warning sign should be monitored after the USB reset to ensure

proper communication with the AFE722x EVM.

Table 1. Control Registers

Interface Serial LVDS

Master Override Enabled

Serial LVDS 2 Wire

Data Orientation MSB first

Format 2s Complement

Clock Delay Enabled

Clock Delay 300ps

Frame Clock Delay Disabled

Frame Clock Delay 0ps

The data coming from the TSW3100 is edge aligned while the AFE722x expects the serial LVDS data to

arrive edge centered. Here the programmable clock delay inside the AFE722x can be used to delay the

edge aligned clock closer towards the center of the data.

The table below shows clock delays for listed DAC sampling rates that showed proper operation.

6EVM Description SLOU330–December 2011

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The general setup tab includes

controls for the digital TX interface This section controls the setup of the digital

interface as well as the TX interpolation

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Initial EVM Setup and Basic Test Procedure

Table 2. Clock Delays for Listed DAC Sampling Rates

DAC Sampling Rate Suitable Clock Delay

130Msps 0ps to 900ps

122.88Msps 0ps to 900ps

100Msps 0ps to 1.2ns

80Msps 0ps to 1.8ns

65Msps 0ps to 2.1ns

40Msps 0ps to 2.1ns

For TX the output data of the TSW3100 needs to be properly configured for 6x serialization using Matlab.

1. Install Matlab runtime engine (MCRInstaller.exe)

2. Open one of the executable (.exe) TSW3100 GUIs – ‘TSW3100_MultitonePattern_v2p7.exe

3. Enter DAC sampling rate

4. Enter tone frequencies

SLOU330–December 2011 EVM Description

Specify DAC

sampling rate

Set tone output

frequency

Press ‘Create and

Save/Run

TSW3100’ to load

data into TSW3100

Specify serial LVDS

as data format

Ensure match on data format with

AFE722x setup (e.g. 2s complement) Select ‘Load and

Run’ option

Initial EVM Setup and Basic Test Procedure

www.ti.com

The DAC output should show something like this on the spectrum analyzer (example with sample rate =

122.88 MSPS, input tone = 10 MHz).

8EVM Description SLOU330–December 2011

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LDO

TPS7A4501

6V Input 5V

LDO

TPS79633

CDCE72010

DC/DC

TPS62291

3.3V

LDO

TPS79518

1.8V

JP10

JP19

JP11

JP12

JP18

JP20

JP14

JP13

JP4

DC/DC

TPS62231

TRF3703

I/Q Mod

VCXO

AFE722x

AFE7225

TSW3100

Pattern Generator

Serialized LVDS

6x DAC Rate

Synchronous Clock

@ 1/8 DAC Rate

www.ti.com

Power Supply Options

5 Power Supply Options

The AFE722x EVM is designed to operate from an external 6 V wall wart supply. A LDO generates a 5V

rail for the TRF3703 IQ modulator as well as for the low noise LDOs which are generating a 3.3 V and 1.8

V rail for the AFE722x and the CDCE72010. Alternatively the 3.3 V and 1.8 V rails can be generated using

DC/DC converters which operate directly from the 6 V input for maximum power efficiency.

The EVM provides options to disable unused circuits by means of pin headers. These headers can also

be used for accurate power measurements where external power supplies can be directly connected to

them.

Three pin headers allow a convenient change between powering the AFE722x and CDCE72010 either

from DC/DC converter or low noise LDO.

6 Clocking Configuration

The AFE722x EVM offers 3 different options for

providing the clock to the AFE722x as well as the

supporting circuitry. The biggest challenge arises

when using the DAC with the TSW3100 because

the TSW3100 expects an input clock at 1/8 of the

DAC input data rate. However since the AFE722x

is designed for the serial LVDS interface, the DAC

data rate is 6x the actual AFE722x clock frequency.

Hence the clock to the TSW3100 needs to 6/8 =

3/4x the AFE722x clock frequency.

SLOU330–December 2011 EVM Description

CDCE72010

SMA

Connector R112 0S

CLK IN

AFE722x

Clk In

DNI DNI

BPF DNI

Y0P Y1P Y1N

SMA

Connector

CDC AUX

IN AUX

SMA

Connector

REF IN Pri Ref TCXO

19.2 MHz

Sec Ref

PLL Lock

SMA

Connector

CLK IN-N

DNI

PLL Lock

Y2P

TSW3100

C70 22pF

DNI

C71 22pF

DNI

R74 0S

R76 0S

R144

R72

R79

DNI

R81

DNI

R86 0S

R161

DNI

Y2N

AUX IN

CDCE72010

AFE722x

TSW3100

Opt. BPF

Clocking Configuration

www.ti.com

The CDCE72010 clock buffer on the AFE722x is used to provide the clock to the TSW3100. Additional

dividers can be added to the clock output in order to divide the clock appropriately for optional

interpolation by 2x or 4x.

Preconfigured setup files:

AUX IN –INT2x –div3 AFE div8 TSW.txt ext 3x clock to CDC AUX IN (see 6.5)

AUX IN –div3 AFE div4 TSW.txt ext 3x clock to CDC AUX IN (see 6.1)

REF IN (10MHz) –div6 AFE div8 TSW.txt ext 10MHz clock on REF IN (see 6.2)

REF IN (10MHz) –INT2x –div6 AFE div16 TSW.txt ext 10MHz clock on REF IN (see 6.2/6.5)

REF IN (122.88MHz) –div6 AFE div8 TSW.txt ext 122.88MHz clock on REF IN (see 6.2)

6.1 Non-VCXO Option (default)

This setup is the default configuration and provides the

option to operate AFE722x and TSW3100 synchronous at

any arbitrary sampling rate without the use of a VCXO.

This setup is useful for testing the AFE722x at clock

frequencies where a VCXO is not immediately available.

10 EVM Description SLOU330–December 2011

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