Texas Instruments MSP430F6720A Manuel utilisateur

Errata

MSP430F6720A Microcontroller

ABSTRACT

This document describes the known exceptions to the functional specifications (advisories).

Table of Contents

1 Functional Advisories............................................................................................................................................................ 2

2 Preprogrammed Software Advisories.................................................................................................................................. 2

3 Debug Only Advisories.......................................................................................................................................................... 3

4 Fixed by Compiler Advisories............................................................................................................................................... 3

5 Nomenclature, Package Symbolization, and Revision Identification................................................................................ 4

5.1 Device Nomenclature.........................................................................................................................................................4

5.2 Package Markings..............................................................................................................................................................4

5.3 Memory-Mapped Hardware Revision (TLV Structure)....................................................................................................... 5

6 Advisory Descriptions............................................................................................................................................................6

7 Revision History................................................................................................................................................................... 24

www.ti.com Table of Contents

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MSP430F6720A Microcontroller 1

1 Functional Advisories

Advisories that affect the device's operation, function, or parametrics.

✓ The check mark indicates that the issue is present in the specified revision.

Errata Number

Rev B

ADC39 ✓

ADC42 ✓

ADC69 ✓

AUXPMM2 ✓

CPU36 ✓

CPU46 ✓

CPU47 ✓

DMA4 ✓

DMA7 ✓

DMA9 ✓

DMA10 ✓

LCDB5 ✓

LCDB6 ✓

PMM7 ✓

PMM11 ✓

PMM12 ✓

PMM14 ✓

PMM15 ✓

PMM18 ✓

PMM20 ✓

PMM26 ✓

PORT15 ✓

PORT19 ✓

SD3 ✓

UCS11 ✓

USCI36 ✓

USCI37 ✓

USCI41 ✓

USCI42 ✓

USCI47 ✓

USCI50 ✓

2 Preprogrammed Software Advisories

Advisories that affect factory-programmed software.

✓ The check mark indicates that the issue is present in the specified revision.

Errata Number

Rev B

BSL7 ✓

BSL14 ✓

Functional Advisories www.ti.com

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3 Debug Only Advisories

Advisories that affect only debug operation.

✓ The check mark indicates that the issue is present in the specified revision.

Errata Number

Rev B

EEM8 ✓

EEM17 ✓

EEM19 ✓

EEM23 ✓

JTAG26 ✓

JTAG27 ✓

4 Fixed by Compiler Advisories

Advisories that are resolved by compiler workaround. Refer to each advisory for the IDE and compiler versions

with a workaround.

✓ The check mark indicates that the issue is present in the specified revision.

Errata Number

Rev B

CPU21 ✓

CPU22 ✓

CPU40 ✓

Refer to the following MSP430 compiler documentation for more details about the CPU bugs workarounds.

TI MSP430 Compiler Tools (Code Composer Studio IDE)

•MSP430 Optimizing C/C++ Compiler: Check the --silicon_errata option

•MSP430 Assembly Language Tools

MSP430 GNU Compiler (MSP430-GCC)

•MSP430 GCC Options: Check -msilicon-errata= and -msilicon-errata-warn= options

•MSP430 GCC User's Guide

IAR Embedded Workbench

•IAR workarounds for msp430 hardware issues

www.ti.com Debug Only Advisories

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MSP430F6720A Microcontroller 3

5 Nomenclature, Package Symbolization, and Revision Identification

The revision of the device can be identified by the revision letter on the Package Markings or by the HW_ID

located inside the TLV structure of the device.

5.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP

MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These

prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully

qualified production devices (MSP).

XMS – Experimental device that is not necessarily representative of the final device's electrical specifications

MSP – Fully qualified production device

Support tool naming prefixes:

X: Development-support product that has not yet completed Texas Instruments internal qualification testing.

null: Fully-qualified development-support product.

XMS devices and X development-support tools are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated

fully. TI's standard warranty applies.

Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.

TI recommends that these devices not be used in any production system because their expected end-use failure

rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature

range, package type, and distribution format.

5.2 Package Markings

PZ100 LQFP (PZ) 100 Pin

Nomenclature, Package Symbolization, and Revision Identification www.ti.com

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PN80 LQFP (PN), 80 Pin

5.3 Memory-Mapped Hardware Revision (TLV Structure)

Die Revision TLV Hardware Revision

Rev B 11h

Further guidance on how to locate the TLV structure and read out the HW_ID can be found in the device User's

Guide.

www.ti.com Nomenclature, Package Symbolization, and Revision Identification

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6 Advisory Descriptions

ADC39 ADC Module

Category Functional

Function Erroneous ADC10 results in extended sample mode

Description If the extended sample mode is selected (ADC10SHP = 0) and the ADC10CLK is

asynchronous to the SHI signal, the ADC10 may generate erroneous results.

Workaround 1) Use the pulse sample mode (ADC10SHP=1)

2) Use a synchronous clock for ADC10 and the SHI signal.

ADC42 ADC Module

Category Functional

Function ADC stops converting when successive ADC is triggered before the previous conversion

ends

Description Subsequent ADC conversions are halted if a new ADC conversion is triggered while ADC

is busy. ADC conversions are triggered manually or by a timer. The affected ADC modes

are:

- sequence-of-channels

- repeat-single-channel

- repeat-sequence-of-channels (ADC12CTL1.ADC12CONSEQx)

In addition, the timer overflow flag cannot be used to detect an overflow

(ADC12IFGR2.ADC12TOVIFG).

Workaround 1. For manual trigger mode (ADC12CTL0.ADC12SC), ensure each ADC conversion

is completed by first checking ADC12CTL1.ADC12BUSY bit before starting a new

conversion.

2. For timer trigger mode (ADC12CTL1.ADC12SHP), ensure the timer period is greater

than the ADC sample and conversion time.

To recover the conversion halt:

1. Disable ADC module (ADC12CTL0.ADC12ENC = 0 and ADC12CTL0.ADC12ON = 0)

2. Re-enable ADC module (ADC12CTL0.ADC12ON = 1 and ADC12CTL0.ADC12ENC =

3. Re-enable conversion

ADC69 ADC Module

Category Functional

Function ADC stops operating if ADC clock source is changed from SMCLK to another source

while SMCLKOFF = 1.

Advisory Descriptions www.ti.com

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Description When SMCLK is used as the clock source for the ADC (ADC12CTL1.ADC12SSELx =

11) and CSCTL4.SMCLKOFF = 1, the ADC will stop operating if the ADC clock source is

changed by user software (e.g. in the ISR) from SMCLK to a different clock source. This

issue appears only for the ADC12CTL1.ADC12DIVx settings /3/5/7. The hang state can

be recovered by PUC/POR/BOR/Power cycle.

Workaround 1. Set CSCTL4.SMCLKOFF = 0 before switch ADC clock source.

2. Only use ADC12CTL1.ADC12DIVx as /1, /2, /4, /6, /8

AUXPMM2 AUXPMM Module

Category Functional

Function Latch-up in AUXPMM

Description Latch-up current can appear at the AUXPMM module supply pins in the following two

scenarios:

Scenario 1: When the AUXPMM is configured for hardware- or software-controlled

switching and the module switches from DVCC to AUXVCC2, latch-up current can

appear at AUXVCC2 at the switching point defined by SVSMHCTL.SVSMHRRL (or

AUXCTL2.AUX0LVLx). The probability for this event to occur depends on:

a) Operating temperature (higher temperatures increase probability)

b) External AUXVCC2 voltage level (higher voltages increase probability)

c) SVSMHRRL level (lower levels increase probability) defining the switching level in

hardware-controlled mode

d) AUX0LVLx level (lower levels increase probability) defining the switching level in

software-controlled mode (applicable to DVCC only)

Scenario 2: When a battery is connected to DVCC, AUXVCC1 or AUXVCC2 as the first

voltage supply, due to the low internal resistance of the battery a very fast rise time is

seen by the AUXPMM and latch-up current can appear at the connected supply if:

a) Rise times are in the range of 140 kV/s (faster rise times increase probability)

b) Device operates at temperatures of 75 deg C and above (higher temperatures increase

probability)

The latch-up current disappears after complete power cycles of all supply sources.

Workaround For scenario 1:

- Increase SVSMRRL to a level above maximum external voltage expected on AUXVCC2.

SVSMRRL = 6 or 7 (requires VCORE level of 3) is applicable for AUXVCC2 of up to

maximum voltage, 3.58V, while a lower SVSMRRL setting can be selected if a lower

voltage (e.g. 3.3V) is expected on AUXVCC2.

- Connect all 3 supplies via 3 external diodes to DVCC and realize the switching externally

without using the internal AUXPMM switches. See application report "Implementation of a

Three-Phase Electronic Watt-Hour Meter Using the MSP430F471xx" for details.

- Use AUXVCC1 instead of AUXVCC2 for backup supply

www.ti.com Advisory Descriptions

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MSP430F6720A Microcontroller 7

For scenario 2:

Limit the supply voltage ramp up time through a series resistor (e.g. 10 Ohm) in the critical

supply path. Side effects such as voltage dips due to high current consumption of the

device need to be considered.

BSL7 BSL Module

Category Software in ROM

Function BSL does not start after waking up from LPMx.5

Description When waking up from LPMx.5 mode, the BSL does not start as it does not clear the Lock

I/O bit (LOCKLPM5 bit in PM5CTL0 register) on start-up.

Workaround 1. Upgrade the device BSL to the latest version (see Creating a Custom Flash-Based

Bootstrap Loader (BSL) Application Note - SLAA450 for more details)

2. Do not use LOCKLPM5 bit (LPMx.5) if the BSL is used but cannot be upgraded.

BSL14 BSL Module

Category Software in ROM

Function BSL request to unlock the JTAG

Description The feature in the BSL to keep the JTAG unlocked by setting the bit

BSL_REQ_JTAG_OPEN in the return value has been disabled in this device.

Workaround None

CPU21 CPU Module

Category Compiler-Fixed

Function Using POPM instruction on Status register may result in device hang up

Description When an active interrupt service request is pending and the POPM instruction is used to

set the Status Register (SR) and initiate entry into a low power mode , the device may

hang up.

Workaround None. It is recommended not to use POPM instruction on the Status Register.

Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes

IAR Embedded Workbench Not affected

TI MSP430 Compiler Tools (Code

Composer Studio) v4.0.x or later

User is required to add the compiler

or assembler flag option below. --

silicon_errata=CPU21

MSP430 GNU Compiler (MSP430-

GCC) MSP430-GCC 4.9 build 167 or later

CPU22 CPU Module

Category Compiler-Fixed

Advisory Descriptions www.ti.com

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Function Indirect addressing mode with the Program Counter as the source register may produce

unexpected results

Description When using the indirect addressing mode in an instruction with the Program Counter (PC)

as the source operand, the instruction that follows immediately does not get executed.

For example in the code below, the ADD instruction does not get executed.

mov @PC, R7

add #1h, R4

Workaround Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes

IAR Embedded Workbench Not affected

TI MSP430 Compiler Tools (Code

Composer Studio) v4.0.x or later

User is required to add the compiler

or assembler flag option below. --

silicon_errata=CPU22

MSP430 GNU Compiler (MSP430-

GCC) MSP430-GCC 4.9 build 167 or later

CPU36 CPU Module

Category Functional

Function PC corruption when single-stepping through flash erase

Description When single-stepping over code that initiates an INFOD Flash memory erase, the

program counter is corrupted.

Workaround None.

NOTE: This erratum applies to debug mode only.

CPU40 CPU Module

Category Compiler-Fixed

Function PC is corrupted when executing jump/conditional jump instruction that is followed by

instruction with PC as destination register or a data section

Description If the value at the memory location immediately following a jump/conditional jump

instruction is 0X40h or 0X50h (where X = don't care), which could either be an instruction

opcode (for instructions like RRCM, RRAM, RLAM, RRUM) with PC as destination

RAM), then the PC value is auto-incremented by 2 after the jump instruction is executed;

therefore, branching to a wrong address location in code and leading to wrong program

execution.

For example, a conditional jump instruction followed by data section (0140h).

@0x8012 Loop DEC.W R6

@0x8014 DEC.W R7

www.ti.com Advisory Descriptions

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@0x8016 JNZ Loop

@0x8018 Value1 DW 0140h

Workaround In assembly, insert a NOP between the jump/conditional jump instruction and program

code with instruction that contains PC as destination register or the data section.

Refer to the table below for compiler-specific fix implementation information.

IDE/Compiler Version Number Notes

IAR Embedded Workbench IAR EW430 v5.51 or later

For the command line version add

the following information Compiler:

--hw_workaround=CPU40

Assembler:-v1

TI MSP430 Compiler Tools (Code

Composer Studio) v4.0.x or later

User is required to add the compiler

or assembler flag option below. --

silicon_errata=CPU40

MSP430 GNU Compiler (MSP430-

GCC) Not affected

CPU46 CPU Module

Category Functional

Function POPM peforms unexpected memory access and can cause VMAIFG to be set

Description When the POPM assembly instruction is executed, the last Stack Pointer increment is

followed by an unintended read access to the memory. If this read access is performed

on vacant memory, the VMAIFG will be set and can trigger the corresponding interrupt

(SFRIE1.VMAIE) if it is enabled. This issue occurs if the POPM assembly instruction is

performed up to the top of the STACK.

Workaround If the user is utilizing C, they will not be impacted by this issue. All TI/IAR/GCC pre-built

libraries are not impacted by this bug. To ensure that POPM is never executed up to the

memory border of the STACK when using assembly it is recommended to either

1. Initialize the SP to

a. TOP of STACK - 4 bytes if POPM.A is used

b. TOP of STACK - 2 bytes if POPM.W is used

2. Use the POPM instruction for all but the last restore operation. For the the last restore

operation use the POP assembly instruction instead.

For instance, instead of using:

POPM.W #5,R13

Advisory Descriptions www.ti.com

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