NXP Semiconductors MPC5777M Manuel utilisateur

NXP Semiconductors

Data Sheet: Technical Data Document Number: MPC5777M

Rev. 6, 06/2016

NXP reserves the right to change the detail specifications as may be required to permit

improvements in the design of its products.

MPC5777M

416 TEPBGA

27mm x 27 mm 512 TEPBGA

25 mm x 25 mm

• ThreemainCPUs,singleissue,32-bitCPUcorecomplexes

(e200z7), one of which is a dedicated lockstep core.

– Power Architecture®embedded specification

compliance

– Instruction set enhancement allowing variable length

encoding (VLE), encoding a mix of 16-bit and 32-bit

instructions, for code size footprint reduction

– Single-precision floating point operations

– 16 KB Local instruction RAM and 64 KB local data

RAM

– 16 KB I-Cache and 4 KB D-Cache

• I/O Processor, dual issue, 32-bit CPU core complex

(e200z4), with

– Power Architecture embedded specification compliance

– Instruction set enhancement allowing variable length

encoding (VLE), encoding a mix of 16-bit and 32-bit

instructions, for code size footprint reduction

– Single-precision floating point operations

– Lightweight Signal Processing Auxiliary Processing

Unit (LSP APU) instruction support for digital signal

processing (DSP)

– 16 KB Local instruction RAM and 64 KB local data

RAM

– 8 KB I-Cache

• 8640 KB on-chip flash

– Supports read during program and erase operations, and

multiple blocks allowing EEPROM emulation

• 404 KB on-chip general-purpose SRAM including 64 KB

standby RAM (+ 192 KB data RAM included in the

CPUs). Of this 404 KB, 64 KB can be powered by a

separate supply so the contents of this portion can be

preserved when the main MCU is powered down.

• Multichannel direct memory access controllers (eDMA): 2

x 64 channels per eDMA (128 channels total)

• Triple Interrupt controller (INTC)

– Dual phase-locked loops with stable clock domain for

peripherals and FM modulation domain for

computational shell

• Dual crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters with

end-to-end ECC

• Hardware Security Module (HSM) to provide robust

integrity checking of flash memory

• System Integration Unit Lite (SIUL)

• Boot Assist Module (BAM) supports factory programming

using serial bootload through ‘UART Serial Boot Mode

Protocol’. Physical interface (PHY) can be:

– UART/LIN

–CAN

• GTM104 — generic timer module

• Enhanced analog-to-digital converter system with

– Twelve separate 12-bit SAR analog converters

– Ten separate 16-bit Sigma-Delta analog converters

• Eight deserial serial peripheral interface (DSPI) modules

• Two Peripheral Sensor Interface (PSI5) controllers

• Three LIN and three UART communication interface

(LINFlexD) modules (6 total)

– LINFlexD_0 is a Master/Slave

– LINFlexD_1, LINFlexD_2, LINFlexD_14,

LINFlexD_15, and LINFlexD_16 are Masters

• Four modular controller area network (MCAN) modules

and one time-triggered controller area network

(M-TTCAN)

• External Bus Interface (EBI)

– Dual routing of accesses to EBI

– Access path determined by access address

– Access path downstream of PFLASH controller

– Allows EBI accesses to share buffer and prefetch

capabilities of internal flash

– Allows internal flash accesses to be remapped to

memories connected to EBI

MPC5777M Microcontroller

Data Sheet

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors2

Table of Contents

1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.3 Device feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . .10

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.2 Pin/ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.2.1 Power supply and reference voltage pins/balls .15

2.2.2 System pins/balls. . . . . . . . . . . . . . . . . . . . . . . .16

2.2.3 LVDS pins/balls . . . . . . . . . . . . . . . . . . . . . . . . .17

3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21

3.3 Electrostatic discharge (ESD). . . . . . . . . . . . . . . . . . . .23

3.4 Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.5 DC electrical specifications. . . . . . . . . . . . . . . . . . . . . .27

3.6 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . .30

3.6.1 I/O input DC characteristics. . . . . . . . . . . . . . . .31

3.6.2 I/O output DC characteristics. . . . . . . . . . . . . . .35

3.7 I/O pad current specification. . . . . . . . . . . . . . . . . . . . .42

3.8 Reset pad (PORST, ESR0) electrical characteristics . .45

3.9 Oscillator and FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . .48

3.10 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

3.10.1 ADC input description . . . . . . . . . . . . . . . . . . . .53

3.10.2 SAR ADC electrical specification. . . . . . . . . . . .54

3.10.3 S/D ADC electrical specification . . . . . . . . . . . .58

3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . .67

3.12 LVDS Fast Asynchronous Serial Transmission

(LFAST) pad electrical characteristics . . . . . . . . . . . . .67

3.12.1 LFAST interface timing diagrams . . . . . . . . . . .68

3.12.2 LFAST and MSC/DSPI LVDS interface

electrical characteristics . . . . . . . . . . . . . . . . . .69

3.12.3 LFAST PLL electrical characteristics. . . . . . . . .72

3.13 Aurora LVDS electrical characteristics . . . . . . . . . . . . .73

3.14 Power management: PMC, POR/LVD, sequencing . . .75

3.14.1 Power management electrical characteristics . .75

3.14.2 Power management integration . . . . . . . . . . . . 75

3.14.3 3.3 V flash supply. . . . . . . . . . . . . . . . . . . . . . . 76

3.14.4 Device voltage monitoring . . . . . . . . . . . . . . . . 77

3.14.5 Power up/down sequencing. . . . . . . . . . . . . . . 79

3.15 Flash memory electrical characteristics. . . . . . . . . . . . 80

3.15.1 Flash memory program and erase

specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.15.2 Flash memory FERS program and

erase specifications . . . . . . . . . . . . . . . . . . . . . 82

3.15.3 Flash memory Array Integrity and Margin

Read specifications . . . . . . . . . . . . . . . . . . . . . 83

3.15.4 Flash memory module life specifications . . . . . 84

3.15.5 Data retention vs program/erase cycles. . . . . . 84

3.15.6 Flash memory AC timing specifications . . . . . . 85

3.15.7 Flash read wait state and address pipeline

control settings. . . . . . . . . . . . . . . . . . . . . . . . . 85

3.16 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.16.1 Debug and calibration interface timing. . . . . . . 86

3.16.2 DSPI timing with CMOS and LVDS pads. . . . . 94

3.16.3 FEC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.16.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . 115

3.16.5 PSI5 timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 118

3.16.6 UART timing. . . . . . . . . . . . . . . . . . . . . . . . . . 118

3.16.7 External Bus Interface (EBI) Timing. . . . . . . . 119

3.16.8 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3.16.9 GPIO delay timing . . . . . . . . . . . . . . . . . . . . . 124

3.16.10Package characteristics. . . . . . . . . . . . . . . . . 124

3.17 416 TEPBGA (production) case drawing . . . . . . . . . 125

3.18 416 TEPBGA (emulation) case drawing. . . . . . . . . . 127

3.19 512 TEPBGA case drawing . . . . . . . . . . . . . . . . . . . 130

3.20 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . 132

3.20.1 General notes for specifications at

maximum junction temperature . . . . . . . . . . . 132

4 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 137

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors 3

— Access path via dedicated AXBS slave port

– Avoids contention with other memory accesses

• Two Dual-channel FlexRay controllers

• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard

• Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)

• Self-test capability

MPC5777M Microcontroller Data Sheet, Rev. 6

Introduction

NXP Semiconductors4

1 Introduction

1.1 Document overview

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5777M series of

microcontroller units (MCUs). For functional characteristics, see the MPC5777M Microcontroller Reference Manual.

1.2 Description

This family of MCUs is targeted at automotive powertrain controller and chassis control applications from single cylinder

motorcycles at the very bottom end; through 4 to 8 cylinder gasoline and diesel engines; transmission control; steering and

breaking applications; to high end hybrid and advanced combustion systems at the top end.

Many of the applications are considered to be functionally safe and the family is designed to achieve ISO26262 ASIL-D

compliance.

1.3 Device feature

Table 1. MPC5777M feature

Feature MPC5777M

Process 55 nm

Main processor Core e200z7

Number of main cores 2

Number of checker cores 1

Local RAM (per main core) 16 KB Instruction

64 KB Data

Single precision floating point Yes

LSP No

VLE Yes

Cache 16 KB Instruction

4 KB Data

I/O processor Core e200z4

Local RAM 16 KB instruction

64 KB Data

Single precision floating point Yes

LSP Yes

VLE Yes

Cache 8 KB instruction

Main processor frequency 300 MHz1

I/O processor frequency 200 MHz

MMU entries 0

MPU Yes

Semaphores Yes

Introduction

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors 5

CRC channels 2

Software watchdog timer

(Task SWT/Safety SWT) 4 (3/1)

Core Nexus class 3+

Sequence processing unit (SPU) Yes

Debug and calibration interface (DCI) / run control

module Yes

System SRAM 404 KB

Flash memory 8640 KB

Flash memory fetch accelerator 4 256 bit

Data flash memory (EEPROM) 8 64 KB

+ 2 16 KB

Flash memory overlay RAM 16 KB

External bus 32 bit

Calibration interface 64-bit IPS Slave

DMA channels 2 64

DMA Nexus Class 3+

LINFlex (UART/MSC) 6 (3/3)

MCAN/TTCAN 4/1

DSPI

(SPI/MSC/sync SCI) 8 (4/3/1)

Microsecond bus downlink Yes

SENT bus 15

I2C 2

PSI5 bus 5

PSI5-S UART-to-PSI5 interface Yes

FlexRay 2 dual channel

Ethernet MII / RMII

Zipwire(SIPI / LFAST2) Interprocessor Communication

Interface High speed

System timers 8 PIT channels

3 AUTOSAR®(STM)

64-bit PIT

BOSCHGTM Timer3Yes

GTM RAM 58 KB

Interrupt controller 727 sources

ADC (SAR) 12

Table 1. MPC5777M feature (continued)

Feature MPC5777M

MPC5777M Microcontroller Data Sheet, Rev. 6

Introduction

NXP Semiconductors6

ADC (SD) 10

Temperature sensor Yes

Self test controller Yes

PLL Dual PLL with FM

Integrated linear voltage regulator None

External power supplies 5 V

3.3 V7

1.2 V

Low-power modes Stop mode

Slow mode

Packages • 416 TEPBGA4

• 512 TEPBGA5

1Includes four user-programmable CPU cores and one safety core. The main computational shell consists of

dual e200z7 CPUs operating at 300 MHz with a third identical core running as a safety checker core in delayed

lockstep mode with one of the dual e200z7 cores. The I/O subsystem includes a CPU targeted at managing

the peripherals. This is an e200z4 CPU running at 200 MHz. The fifth CPU is an e200z0 running at 100 MHz

and is embedded in the Hardware Security Module. All CPUs are compatible with the Power Architecture.

2LVDS Fast Asynchronous Serial Transmission

3BOSCH®is a registered trademark of Robert Bosch GmbH.

4416 TEPBGA package supports development and production applications with the same package footprint.

5512 TEPBGA package supports development and production applications with the same package footprint.

Table 1. MPC5777M feature (continued)

Feature MPC5777M

MPC5777M Microcontroller Data Sheet, Rev. 6

Introduction

NXP Semiconductor s7

1.4 Block diagram

The figures below show the top-level block diagrams.

Introduction

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors 8

Figure 1. Block diagram

Package pinouts and signal descriptions

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors 9

Figure 2. Periphery allocation

2 Package pinouts and signal descriptions

See the MPC5777M Microcontroller Reference Manual for signal information.

Peripheral Bus (AIPS_0)

Peripheral

Cluster A

WKPU

LVIIO

LVIFLASH

LVI 1.2V

HVI 1.2V

PMC

PCU

RGM

CGM

RCOSC_DIG_0

OSC_DIG

CMU_PLL

SUIL2

2 x SIPI

2 x LFAST

CFLASH_0

PA S S

SSCM

BAF

PLL

PRAM

PFLASH

INTC_0

4 x SWT

3 x STM

2 x SMPU

3 x SAR ADC

PSI5_0

FLEXRAY_0

SENT_0

IIC_0

5 x DSPI

4 x LINFlexD

4 x MCAN

TTCAN_0

HSM INTERFACE

DTS

JDC

SRAM CAN

5 x SD ADC

2 x DMA

FEC

GTM

2 x LINFlexD 5 x SD ADC

9 x SAR ADC

PSI5_1

SENT_1

3 x DSPI

12 x CMU

CRC_1

FCCU

Peripheral Bus (AIPS_1)

Peripheral

Cluster B

JTAGM

STCU2 MEMU IMA CRC_0 10 x DMAMUX 2 x PIT_RTCAT X

SEMA4

FLEXRAY_1 IIC_1

TDM

PCM

2 x AXBS

EBI

2 x XBIC

TSENS

PSI5_S_0

Package pinouts and signal descriptions

MPC5777M Microcontroller Data Sheet, Rev. 6

NXP Semiconductors 10

2.1 Package pinouts

The BGA ballmap package pinouts for the 416 and 512 production and emulation devices are shown in the following figures.

Figure 3. 416-ball BGA production device pinout (top view)

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/Kͺ&>y s^^ͺ,s sͺ>s E sͺ,sͺ

/Kͺ&>y s^^ͺ,s Wd΀ϯ΁ Wd΀ϴ΁ Wd΀ϭϯ΁ $&

$' W΀ϰ΁ WZ΀Ϭ΁ W'΀ϳ΁ W<΀ϭϬ΁ W΀ϭ΁ sͺ,sͺ

ZͺϮ

W'΀ϱ΁ W΀ϳ΁ s^dz W>΀ϭϮ΁ W/΀ϭϮ΁ W&΀Ϭ΁ W>΀ϭϱ΁ W:΀ϲ΁ W΀ϭϭ΁ sͺ,sͺ

/KͺD/E

W&΀ϲ΁ W^΀Ϭ΁ W^΀ϯ΁ W^΀ϲ΁ W^΀ϵ΁ W^΀ϭϮ΁ W^΀ϭϰ΁ Wd΀ϰ΁ Wd΀ϵ΁ Wd΀ϭϰ΁ $'

$( WZ΀ϭ΁ W/΀ϳ΁ W'΀ϭϮ΁ W΀Ϯ΁ sͺ,sͺ

sͺ

WZ΀Ϯ΁ WZ΀ϰ΁ s^^ͺ,sͺ

Zͺ^

sͺ,sͺ

sͺ^

W>΀ϭϯ΁ W/΀ϭϭ΁ W΀ϵ΁ W:΀Ϭ΁ W΀ϵ΁ W΀ϴ΁ sͺ,sͺ

/KͺD/E

W:΀ϳ΁ W^΀ϭ΁ W^΀ϰ΁ W^΀ϳ΁ W^΀ϭϬ΁ W^΀ϭϯ΁ W^΀ϭϱ΁ Wd΀ϱ΁ Wd΀ϭϬ΁ Wd΀ϭϱ΁ $(

$) E W/΀ϲ΁ W'΀ϭϭ΁ W΀ϯ΁ s^^ͺ,sͺ

sͺ WZ΀ϯ΁ WZ΀ϱ΁ sͺ,sͺ

Zͺ^

s^^ͺ,sͺ

sͺ^ W>΀ϭϭ΁ W/΀ϭϬ΁ W΀ϭϬ΁ W:΀ϭ΁ W΀ϴ΁ W΀ϯ΁ sͺ,sͺ

/KͺD/E W:΀ϱ΁ W^΀Ϯ΁ W^΀ϱ΁ W^΀ϴ΁ W^΀ϭϭ΁ Wd΀Ϭ΁ Wd΀ϭ΁ Wd΀ϲ΁ Wd΀ϭϭ΁ E $)

                         

Autres manuels pour MPC5777M

Table des matières

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