NXP Semiconductors LPC11E Series Manuel utilisateur

UM10518

LPC11Exx User manual

Rev. 3.5 — 21 December 2016 User manual

Document information

Info Content

Keywords LPC11Exx, ARM Cortex-M0, microcontroller, LPC11E11, LPC11E12,

LPC11E14, LPC11E13, LPC11E3x, LPC11E37H, LPC11E35, I/O Handler.

Abstract LPC11Exx User manual.

User manual Rev. 3.5 — 21 December 2016 2 of 424

NXP Semiconductors UM10518

LPC11Exx User manual

Revision history

Rev Date Description

3.5 20161221 LPC11Exx User manual

Modifications:

•Updated Section 19.8.8 “RAM used by ISP command handler”, Section 19.8.9 “RAM used by IAP command

handler”, and Section 19.13 “IAP commands”: Added on-chip local ROM.

•Updated Table 317 “IAP Prepare sector(s) for write operation command”, Table 318 “IAP Copy RAM to flash

command”, Table 319 “IAP Erase Sector(s) command”: Deleted The boot sector can not be prepared by this

command.

3.4 20140908 LPC11Exx User manual

Modifications:

•Added part LPC11E35FHI33/501.

3.3 20140611 LPC11Exx User manual

Modifications:

•I/O Handler interrupt added in Table 48 “Connection of interrupt sources to the Vectored Interrupt Controller”.

•NVIC register description added. See Section 5.5.

3.2 20140401 LPC11Exx User manual

Modifications:

•Table 13 “Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit description” added.

•Watchdog interrupt flag polarity corrected: This flag is cleared by writing a 1 to the WDINT bit in the MOD register

(Section 15.8.1 “Watchdog mode register”).

•Use of IAP mode with power profiles clarified. Use power profiles in default mode when executing IAP

commands. See Section 19.13 “IAP commands” and Section 5.3.

•Section 5.3 added to clarify use of power profiles.

•Remark added to Section 3.9.4.3 “Wake-up from Deep-sleep mode” and Section 3.9.5.3 “Wake-up from

Power-down mode”: After wake-up, reprogram the clock source for the main clock.

•Pin description tables for RESET/PIO0_0 updated: In deep power-down mode, this pin must be pulled HIGH

externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is

not needed. See Chapter 8 “LPC11Exx Pin configuration”.

•Pin description notes relating to open-drain I2C-bus pins updated for clarity. Chapter 8 “LPC11Exx Pin

configuration”.

•Pin description of the WAKEUP pin updated for clarity. Chapter 8 “LPC11Exx Pin configuration”.

3.1 20131220 LPC11Exx User manual

Modifications:

•SYSAHBCLKCTRL reset value corrected. Table 5.

•Reserved function added to IOCON pin configuration registers PIO0_8 and PIO0_9. See Table 61 and Table 62.

3 20131125 LPC11Exx User manual

User manual Rev. 3.5 — 21 December 2016 3 of 424

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LPC11Exx User manual

Modifications:

•Boot loader description clarified. See Section 19.4.

•Part LPC11E37HFBD64/401 added.

•Clock for SRAM2 block added in SYSAHBCLKCTRL register. See Table 19.

•SRAM memory naming updated in Chapter 2 “LPC11Exx Memory mapping”.

•Description of ISP Go command: example added. See Section 19.12.8.

•API pointer structure updated in Figure 8 and Figure 64.

•Power Profiles API pointer definitions corrected. See Section 5.4.

•Chapter 22 “LPC11Exx I/O Handler” added.

•Chapter 18 “LPC11Exx I/O EEPROM” added to summarize the EEPROM functionality and features.

•Section 19.13 “IAP commands” updated.

2 20121025 LPC11Exx User manual

Modifications:

•SRAM use by boot loader specified in Section 18.2.

•Description of interrupt use with IAP calls updated (see Section 18.8.7).

•Description of ISP Go command updated (only Thumb mode allowed).

•Update EEPROM write command (see Section 18.13.11). The top 64 bytes are reserved for the 4 kB EEPROM

only.

•Figure 60 corrected.

•Remove the following step to execute before entering Deep power-down: Enable the IRC. This step is not longer

required. See Section 3.9.6 “Deep power-down mode”.

•Description of the BYPASS bit corrected in Table 11 “System oscillator control register (SYSOSCCTRL, address

0x4004 8020) bit description””.

•FREQSEL bit values updated in Table 12 “Watchdog oscillator control register (WDTOSCCTRL, address 0x4004

8024) bit description”.

•Editorial updates to Section 9.4.1 and Section 9.6.4.

•BOD interrupt level 0 removed. See Section 3.5.22 “BOD control register”.

•Explained use of interrupts with Power profiles in Section 5.3 “General description”.

•Remove instruction breakpoints from feature list for SWD. See Section 19.2.

•Register offset of the CR1 register corrected in timers CT16B0 and CT32B0. See Table 214 and Table 235.

•Bit position of the CAP1 interrupt flag corrected in the IR registers of timers CT16B0 and CT32B0. See Table 216

and Table 235.

•Bit positions of the CAP1 edge and interrupt control bits corrected in the CCR registers of timers CT16B0 and

CT32B0. See Table 224 and Table 245.

•Bit values of the CAP1 counter mode and capture input select bits corrected in the CTCR registers of timers

CT16B0 and CT32B0. See Table 231 and Table 252.

•Polarity of FILTR bit corrected in IOCON registers TDI_PIO0_11 to PIO0_16, and PIO0_21 and PIO0_22. See

Chapter 7 “LPC11Exx I/O configuration”.

•Parts LPC11E3x added.

Revision history …continued

Rev Date Description

User manual Rev. 3.5 — 21 December 2016 4 of 424

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

NXP Semiconductors UM10518

LPC11Exx User manual

1 20120208 LPC11Exx User manual

Revision history …continued

Rev Date Description

User manual Rev. 3.5 — 21 December 2016 5 of 424

1.1 Introduction

The LPC11Exx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC11Exx operate at CPU frequencies of up to 50 MHz. The peripheral complement

of the LPC11Exx includes up to 32 kB of flash memory, up to 8 kB of SRAM data memory,

one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 USART with support for

synchronous mode and smart card interface, two SSP interfaces, four general purpose

counter/timers, a 10-bit ADC, and up to 54 general purpose I/O pins.

The I/O Handler is a software library-supported hardware engine that can be used to add

performance, connectivity and flexibility to system designs. It is available on the

LPC11E37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,

I2C, and I2S with no or very low additional CPU load and can off-load the CPU by

performing processing-intensive functions like DMA transfers in hardware. Software

libraries for multiple I/O Handler applications are available on http://www.LPCware.com.

For additional documentation, see Section 24.2 “References”.

1.2 Features

•System:

–ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

–ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

–Non-Maskable Interrupt (NMI) input selectable from several input sources.

–System tick timer.

•Memory:

–Up to 32 kB on-chip flash program memory (LPC11E1x).

–Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase

(256 byte) access (LPC11E3x).

–Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.

–Up to 12 kB SRAM data memory.

–16 kB boot ROM.

–In-System Programming (ISP) and In-Application Programming (IAP) for flash and

EEPROM via on-chip bootloader software.

–ROM-based 32-bit integer division routines.

•Debug options:

–Standard JTAG test interface for BSDL.

–Serial Wire Debug.

UM10518

Chapter 1: LPC11Exx Introductory information

Rev. 3.5 — 21 December 2016 User manual

User manual Rev. 3.5 — 21 December 2016 6 of 424

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Chapter 1: LPC11Exx Introductory information

•Digital peripherals:

–Up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors, repeater mode, and open-drain mode.

–Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.

–Two GPIO grouped interrupt modules enable an interrupt based on a

programmable pattern of input states of a group of GPIO pins.

–High-current source output driver (20 mA) on one pin.

–High-current sink driver (20 mA) on true open-drain pins.

–Four general-purpose counter/timers with a total of up to 5 capture inputs and 13

match outputs.

–Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal

low-power WatchDog Oscillator (WDO).

•Analog peripherals:

–10-bit ADC with input multiplexing among eight pins.

•Serial interfaces:

–USART with fractional baud rate generation, internal FIFO, a full modem control

handshake interface, and support for RS-485/9-bit mode and synchronous mode.

USART supports an asynchronous smart card interface (ISO 7816-3).

–Two SSP controllers with FIFO and multi-protocol capabilities.

–I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with

a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.

•I/O Handler for hardware emulation of serial interfaces and DMA; supported through

software libraries.(LPC11E37HFBD64/401 only.)

•Clock generation:

–Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).

–12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as

a system clock.

–Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable

frequency output.

–PLL allows CPU operation up to the maximum CPU rate with the system oscillator

or the IRC as clock sources.

–Clock output function with divider that can reflect the crystal oscillator, the main

clock, the IRC, or the watchdog oscillator.

•Power control:

–Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, Power-down, and Deep power-down modes.

–Power profiles residing in boot ROM allow optimized performance and minimized

power consumption for any given application through one simple function call.

–Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

–Processor wake-up from Deep-sleep and Power-down modes via reset, selectable

GPIO pins, or a watchdog interrupt.

–Processor wake-up from Deep power-down mode using one special function pin.

User manual Rev. 3.5 — 21 December 2016 7 of 424

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Chapter 1: LPC11Exx Introductory information

–Power-On Reset (POR).

–Brownout detect with four separate thresholds for interrupt and forced reset.

•Unique device serial number for identification.

•Single 3.3 V power supply (1.8 V to 3.6 V).

•Temperature range 40 C to +85 C.

•Available as LQFP64, LQFP48, HVQFN33 (7x7), and HVQFN33 (5x5) packages.

User manual Rev. 3.5 — 21 December 2016 8 of 424

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Chapter 1: LPC11Exx Introductory information

1.3 Ordering information

[1] Top 64 byte are reserved for 4 kB EEPROM.

[2] This part includes I/O Handler; additional 2 kB of SRAM1 available for I/O Handler library only; see Table 3 “LPC11Exx memory

configuration”.

Table 1. Ordering information

Type number Package

Name Description Version

LPC11E35FHI33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33

terminals; body 550.85 mm n/a

LPC11E11FHN33/101 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33

terminals; body 7 7 0.85 mm n/a

LPC11E12FBD48/201 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2

LPC11E13FBD48/301 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2

LPC11E14FHN33/401 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33

terminals; body 7 7 0.85 mm n/a

LPC11E14FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2

LPC11E14FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2

LPC11E36FBD64/501 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2

LPC11E36FHN33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33

terminals; body 7 7 0.85 mm n/a

LPC11E37FBD48/501 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2

LPC11E37HFBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2

LPC11E37FBD64/501 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2

Table 2. Part ordering options

Part Number Flash EEPROM Total

general

purpose

SRAM

I2C-bus

FM+ USART SSP ADC

channels GPIO

LPC11E11FHN33/101 8 kB 512 B 4 kB 1 1 2 8 28

LPC11E12FBD48/201 16 kB 1 kB 6 kB 1 1 2 8 40

LPC11E13FBD48/301 24 kB 2 kB 8 kB 1 1 2 8 40

LPC11E14FHN33/401 32 kB 4 kB[1] 10 kB 1 1 2 8 28

LPC11E14FBD48/401 32 kB 4 kB[1] 10 kB 1 1 2 8 40

LPC11E14FBD64/401 32 kB 4 kB[1] 10 kB 1 1 2 8 54

LPC11E35FHI33/501 64 kB 4 kB[1] 12 kB 1 1 2 8 26

LPC11E36FBD64/501 96 kB 4 kB[1] 12 kB 1 1 2 8 54

LPC11E36FHN33/501 96 kB 4 kB[1] 12 kB 1 1 2 8 28

LPC11E37FBD48/501 128 kB 4 kB[1] 12 kB 1 1 2 8 40

LPC11E37HFBD64/401[2] 128 kB 4 kB[1] 10 kB 1 1 2 8 54

LPC11E37FBD64/501 128 kB 4 kB[1] 12 kB 1 1 2 8 54

User manual Rev. 3.5 — 21 December 2016 9 of 424

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Chapter 1: LPC11Exx Introductory information

1.4 Block diagram

(1) Not available on HVQFN33 packages.

(2) CT16B0/1_CAP1, CT32B1_CAP1 available on the LQFP64 package only. CT32B0_CAP1 available on the LQFP64 and

LQFP48 packages only.

Fig 1. Block diagram

SRAM

4/6/8/10 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

8/16/24/32 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

RESET

SWD, JTAG

LPC11E1x

slave

slave slave slave

ROM

16 kB

slave

AHB-LITE BUS

GPIO ports 0/1

CLKOUT

IRC, WDO

SYSTEM OSCILLATOR

POR

PLL0

BOD

10-bit ADC

USART/

SMARTCARD INTERFACE AD[7:0]

RXD

TXD

CTS, RTS, DTR

SCLK

GPIO INTERRUPTS

32-bit COUNTER/TIMER 0

CT32B0_MAT[3:0]

CT32B0_CAP[1:0](2)

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

CT32B1_CAP[1:0](2)

DCD, DSR(1), RI(1)

16-bit COUNTER/TIMER 1

WINDOWED WATCHDOG

TIMER

GPIO GROUP0 INTERRUPTS

CT16B1_MAT[1:0]

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP[1:0](2)

CT16B1_CAP[1:0](2)

GPIO pins

GPIO GROUP1 INTERRUPTS

GPIO pins

system bus

SSP0 SCK0, SSEL0,

MISO0, MOSI0

SSP1 SCK1, SSEL1,

MISO1, MOSI1

I2C-BUS

IOCON

SYSTEM CONTROL

PMU

SCL, SDA

XTALIN XTALOUT

002aag683

EEPROM

512 B

1/2/4 kB

User manual Rev. 3.5 — 21 December 2016 10 of 424

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Chapter 1: LPC11Exx Introductory information

(1) Not available on HVQFN33 packages.

(2) CT16B0_CAP1, CT16B1_CAP1 available on LQFP64 packages only; CT32B0_CAP1 available LQFP48, and LQFP64

packages only; CT32B1_CAP1 available in LQFP64 packages only.

(3) LPC11E37HFBD64/401 only.

Fig 2. Block diagram

SRAM

10/12 kB

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

FLASH

64/96/128 kB

HIGH-SPEED

GPIO

AHB TO APB

BRIDGE

CLOCK

GENERATION,

POWER CONTROL,

SYSTEM

FUNCTIONS

RESET

SWD, JTAG

LPC11E3x

slave

slave slave slave

ROM

16 kB

slave

AHB-LITE BUS

GPIO ports 0/1

CLKOUT

IRC, WDO

SYSTEM OSCILLATOR

POR

PLL0

BOD

10-bit ADC

USART/

SMARTCARD INTERFACE AD[7:0]

RXD

TXD

CTS, RTS, DTR

SCLK

GPIO INTERRUPTS

32-bit COUNTER/TIMER 0

CT32B0_MAT[3:0]

CT32B0_CAP[1:0](2)

32-bit COUNTER/TIMER 1

CT32B1_MAT[3:0]

CT32B1_CAP[1:0](2)

DCD, DSR(1), RI(1)

16-bit COUNTER/TIMER 1

WINDOWED WATCHDOG

TIMER

GPIO GROUP0 INTERRUPTS

CT16B1_MAT[1:0]

16-bit COUNTER/TIMER 0

CT16B0_MAT[2:0]

CT16B0_CAP[1:0](2)

CT16B1_CAP[1:0](2)

GPIO pins

GPIO GROUP1 INTERRUPTS

GPIO pins

system bus

SSP0 SCK0, SSEL0,

MISO0, MOSI0

SSP1 SCK1, SSEL1,

MISO1, MOSI1

I2C-BUS

IOCON

SYSTEM CONTROL

PMU

SCL, SDA

XTALIN XTALOUT

002aah401

EEPROM

4 kB

master

I/O

HANDLER(3)

IOH_[20:0]

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