Advantech EVA-X4300 Manuel utilisateur

User Manual

EVA-X4300

System Design Guide

EVA-X4300 System Design Guide ii

Advantech reserves the right to make changes without further notice to any products

or data herein to improve reliability, function, or design. Information furnished by

Advantech is believed to be accurate and reliable. However, Advantech does not

assure any liability arising out of the application or use of this information, nor the

application or use of any product or circuit described herein, neither does it convey

any license under its patent rights nor the rights of others.

Part No. 2006X43020 Edition 1

Printed in Taiwan August 2008

iii EVA-X4300 System Design Guide

Contents

Chapter 1 Overview...............................................1

1.1 Overview ................................................................................................... 2

Chapter 2 Layout Guide........................................3

2.1 BGA Layout Guideline............................................................................... 4

2.2 Package Outline........................................................................................ 6

2.3 Signal Arrangement .................................................................................. 8

2.4 EVA-X4300 Power Requirement............................................................. 11

2.5 General Layout Rule ............................................................................... 11

2.6 Crystal / External Oscillator..................................................................... 15

2.7 DDR2 Interface ....................................................................................... 16

2.8 Switching Power...................................................................................... 19

2.9 PCI Interface ........................................................................................... 20

2.10 USB 2.0................................................................................................... 21

2.11 IDE .......................................................................................................... 23

2.12 LPC Interface .......................................................................................... 24

2.13 10/100 LAN ............................................................................................. 25

Appendix A References .........................................29

A.1 References.............................................................................................. 30

EVA-X4300 System Design Guide iv

Chapter 1

1Overview

EVA-X4300 System Design Guide 2

1.1 Overview

The EVA-X4300 is a fully static 32-bit x86-based processor that is compatible with a

wide-range of PC peripherals, applications and operating systems, such as DOS,

WinCE, Linux, and most popular 32-bit RTOSs (Real Time OS). It enables maximum

software re-use based on its feature of legacy compatibility. The EVA-X4300 inte-

grates 32 KB write-through direct map L1 cache, a PCI bus interface at 33 MHz, an 8/

16-bit ISA bus interface, SDR SDRAM, DDR2 SDRAM, a ROM controller, IPC (Inter-

nal Peripheral Controller) with DMA and interrupt timer/counter included, FIFO UART,

SPI (Serial Peripheral Interface), LPC (low pin count), a USB 1.1/2.0 host controller,

LoC (LAN on Chip), an IDE controller, and 256 KB flash within a single 581-pin BGA

package to form a an SoC (System-on-Chip) processor. The EVA-X4300 integrates

comprehensive features and rich I/O flexibility within a single System-on-Chip, to

reduce board design complexity and shorten product development schedules. Taking

advantage of ultra low power consumption, the EVA-X4300 is able to operate in a

wide range of temperatures without additional thermal design. With the commitment

of long term supply guaranteed for the EVA-X4300, customers can extend product

life cycle and receive a maximum return on investment.

The EVA-X4300 provides an ideal solution for embedded systems and communica-

tion products (such as the thin client, NAT router, home gateway, access point and

tablet PC) producing optimal performance.

This system design guide provides detailed usage information of the highly inte-

grated EVA-X4300 SoC processor.

Chapter 2

2Layout Guide

EVA-X4300 System Design Guide 4

2.1 BGA Layout Guideline

The package of EVA-X4300 is 581-ball PBGA. The ball diameter is 0.6 mm (24 mil);

ball pitch is 1 mm (40 mil). There are 6 rows of balls arranged along the edge of the

package.

For 6-layer:

!Ball pad diameter: 24 mil

!Traces width/ spacing for Signals: 5.5/ 5 mil

!Trace width for Power and Ground: 20 mils

!Vias PAD/ Drill diameter for all Signals: 14/ 8 mil

!Via-to-via spacing (center to center): 40 mil

!Via-to-pad spacing (center to center): 30 mil

5 EVA-X4300 System Design Guide

Chapter 2 Layout Guide

For 4-layer:

!Ball pad diameter: 14 mil

!Traces width/ spacing for Signals: 5/ 5 mil

!Trace width for Power and Ground: 20 mils

!Vias PAD/ Drill diameter for all Signals: 22/ 12 mil

!Via-to-via spacing (center to center): 40 mil

!Via-to-pad spacing (center to center): 30 mil

Note! All the Vias must be covered by solder mask. To minimize inductance,

power vias should be as large as possible and take good care of the

inadvertently cut of the ground and power planes.

EVA-X4300 System Design Guide 6

2.2 Package Outline

Table des matières

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