Texas Instruments MSP430F663x Manuel utilisateur

PRODUCT PREVIEW

MSP430F663x

www.ti.com

SLAS566 –OCTOBER 2009

MIXED SIGNAL MICROCONTROLLER

1FEATURES

• Low Supply-Voltage Range, 1.8 V to 3.6 V • Two Universal Serial Communication

Interfaces

• Ultralow Power Consumption – USCI_A0 and USCI_A1 Each Supporting

– Active Mode (AM): TBD μA/MHz – Enhanced UART supporting

– Standby Mode (LPM3 WDT Mode): TBD μAAuto-Baudrate Detection

– Off Mode (LPM4 RAM Retention): TBD μA– IrDA Encoder and Decoder

– Shutdown Mode (LPM5 RTC Mode): TBD μA– Synchronous SPI

– Shutdown Mode (LPM5): TBD μA– USCI_B0 and USCI_B1 Each Supporting

• Wake-Up From Standby Mode in Less Than – I2CTM

5μs– Synchronous SPI

• 16-Bit RISC Architecture, Extended Memory,

up to 20-MHz System Clock • Full-Speed Universal Serial Bus (USB)

• Flexible Power Management System – Integrated USB-PHY

– Fully Integrated LDO With Programmable – Integrated 3.3-V/1.8-V USB Power System

Regulated Core Supply Voltage – Integrated USB-PLL

– Supply Voltage Supervision, Monitoring, – Eight Input, Eight Output Endpoints

and Brownout • 12-Bit Analog-to-Digital (A/D) Converter With

• Unified Clock System Internal Shared Reference, Sample-and-Hold,

– FLL Control Loop for Frequency and Autoscan Feature

Stabilization • Dual 12-Bit Digital-to-Analog (D/A) Converters

– Low Power/Low Frequency Internal Clock With Synchronization

Source (VLO) • Comparator

– Low Frequency Trimmed Internal Reference • Integrated LCD Driver With Contrast Control

Source (REFO) for up to 160 Segments

– 32-kHz Crystals (XT1) • Hardware Multiplier Supporting 32-Bit

– High-Frequency Crystals Up to 32 MHz Operations

(XT2) • Flash Memory

• 16-Bit Timer TA0, Timer_A With Five – Serial Onboard Programming, No External

Capture/Compare Registers Programming Voltage Needed

• 16-Bit Timer TA1, Timer_A With Three – Enhanced Data Integrity

Capture/Compare Registers • Six-Channel Internal DMA

• 16-Bit Timer TA2, Timer_A With Three • Real-Time Clock Module With Supply Voltage

Capture/Compare Registers Backup Switch

• 16-Bit Timer TB0, Timer_B With Seven • Family Members are Summarized in Table 1

Capture/Compare Shadow Registers • For Complete Module Descriptions, See the

MSP430x5xx/MSP430x6xx Family User's Guide

(SLAU208)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

formative or design phase of development. Characteristic data and

other specifications are design goals. Texas Instruments reserves

the right to change or discontinue these products without notice.

DRAFT ONLY

PRODUCT PREVIEW

MSP430F663x

SLAS566 –OCTOBER 2009

www.ti.com

DESCRIPTION

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 5 μs.

The MSP430F663x series are microcontroller configurations with four 16-bit timers, a high performance 12-bit

analog-to-digital (A/D) converter, two universal serial communication interfaces (USCI), hardware multiplier,

DMA, real-time clock module with alarm capabilities, comparator, USB 2.0, and up to 74 I/O pins.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote

controls, thermostats, digital timers, hand-held meters, etc.

Family members available are summarized in Table 1.

Table 1. Family Members

USCI

Flash SRAM Timer_A Timer_B ADC12_A DAC12_A Comp_B Package

Channel A: Channel B:

Device I/O

(KB) (KB) (1) (2) (3) (Ch) (Ch) (Ch) Type

UART/IrDA/ SPI/I2C

SPI

12 ext / 100 PZ,

MSP430F6638 256 16 + 2 5, 3, 3 7 2 2 2 12 74

4 int 113 ZQW

12 ext / 100 PZ,

MSP430F6637(4) 192 16 + 2 5, 3, 3 7 2 2 2 12 74

4 int 113 ZQW

12 ext / 100 PZ,

MSP430F6636(4) 128 16 + 2 5, 3, 3 7 2 2 2 12 74

4 int 113 ZQW

12 ext / 100 PZ,

MSP430F6635(4) 256 16 + 2 5, 3, 3 7 2 2 - 12 74

4 int 113 ZQW

12 ext / 100 PZ,

MSP430F6634(4) 192 16 + 2 5, 3, 3 7 2 2 - 12 74

4 int 113 ZQW

12 ext / 100 PZ,

MSP430F6633(4) 128 16 + 2 5, 3, 3 7 2 2 - 12 74

4 int 113 ZQW

100 PZ,

MSP430F6632(4) 256 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW

100 PZ,

MSP430F6631(4) 192 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW

100 PZ,

MSP430F6630(4) 128 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW

(1) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.

(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(3) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(4) Product Preview

DRAFT ONLY

PRODUCT PREVIEW

MSP430F663x

www.ti.com

SLAS566 –OCTOBER 2009

Ordering Information(1)

PACKAGED DEVICES (2)

TAPLASTIC 100-PIN TQFP (PZ) PLASTIC 113-BALL BGA (ZQW)

MSP430F6638IPZ MSP430F6638IZQW(3)

MSP430F6637IPZ(3) MSP430F6637IZQW(3)

MSP430F6636IPZ(3) MSP430F6636IZQW(3)

MSP430F6635IPZ(3) MSP430F6635IZQW(3)

–40°C to 85°C MSP430F6634IPZ(3) MSP430F6634IZQW(3)

MSP430F6633IPZ(3) MSP430F6633IZQW(3)

MSP430F6632IPZ(3) MSP430F6632IZQW(3)

MSP430F6631IPZ(3) MSP430F6631IZQW(3)

MSP430F6630IPZ(3) MSP430F6630IZQW(3)

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/package.

(3) Product preview.

DRAFT ONLY

PRODUCT PREVIEW

Unified

Clock

System

256KB

192KB

128KB

Flash

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN XOUT

JTAG/

Interface/

Port PJ

SBW

PA PB PC PD

DMA

6 Channel

XT2IN

XT OUT2

Power

Management

LDO

SVM/

Brownout

SVS

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

1×14 I/Os

1×8 I/Os

I/O Ports

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_B

Battery

Backup

System

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

ADC12_A

200 KSPS

16 Channels

(12 ext/4 int)

Autoscan

12 Bit

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

DAC12_A

12 bit

2 channels

voltage out

LCD_B

160

Segments

USB

Full-speed

Comp_B

EDI

Enhanced

Data

Integrity

PJ.x

16KB

RAM

+2KB RAM

USB Buffer

+8B Backup

RAM

Unified

Clock

System

256KB

192KB

128KB

Flash

16KB

RAM

+2KB RAM

USB Buffer

+8B Backup

RAM

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN XOUT

JTAG/

Interface/

Port PJ

SBW

PA PB PC PD

DMA

6 Channel

XT2IN

XT OUT2

Power

Management

LDO

SVM/

Brownout

SVS

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

1×14 I/Os

1×8 I/Os

I/O Ports

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

ADC12_A

200 KSPS

16 Channels

(12 ext/4 int)

Autoscan

12 Bit

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

LCD_B

160

Segments

USB

Full-speed

Comp_B

EDI

Enhanced

Data

Integrity

PJ.x

RTC_B

Battery

Backup

System

MSP430F663x

SLAS566 –OCTOBER 2009

www.ti.com

Functional Block Diagram, MSP430F6638, MSP430F6637, MSP430F6636

Functional Block Diagram, MSP430F6635, MSP430F6634, MSP430F6633

DRAFT ONLY

PRODUCT PREVIEW

Unified

Clock

System

256KB

192KB

128KB

Flash

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN XOUT

JTAG/

Interface/

Port PJ

SBW

PA PB PC PD

DMA

6 Channel

XT2IN

XT OUT2

Power

Management

LDO

SVM/

Brownout

SVS

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

1×14 I/Os

1×8 I/Os

I/O Ports

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

LCD_B

160

Segments

USB

Full-speed

Comp_B

EDI

Enhanced

Data

Integrity

PJ.x

RTC_B

Battery

Backup

System

16KB

RAM

+2KB RAM

USB Buffer

+8B Backup

RAM

MSP430F663x

www.ti.com

SLAS566 –OCTOBER 2009

Functional Block Diagram, MSP430F6632, MSP430F6631, MSP430F6630

DRAFT ONLY

PRODUCT PREVIEW

100

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2/R23

LCDCAP/R33

COM0

P5.3/COM1/S42

P9.7/S0

P9.6/S1

P9.5/S2

P9.4/S3

P9.3/S4

P9.2/S5

P9.1/S6

P9.0/S7

P8.7/S8

P8.6/UCB1SOMI/UCB1SCL/S9

P8.5/UCB1SIMO/UCB1SDA/S10

DVCC2

DVSS2

P2.0/P2MAP0

MSP430F6638

MSP430F6637

MSP430F6636

PZ PACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2/S36

P1.4/TA0.3/S35

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4/COM2/S41

P5.5/COM3/S40

P1.0/TA0CLK/ACLK/S39

P3.0/TA1CLK/CBOUT/S31

P3.1/TA1.0/S30

P3.2/TA1.1/S29

P1.6/TA0.1/S33

P1.7/TA0.2/S32

P1.1/TA0.0/S38

P1.2/TA0.1/S37

P1.5/TA0.4/S34

P3.3/TA1.2/S28

P3.4/TA2CLK/SMCLK/S27

P3.5/TA2.0/S26

P3.6/TA2.1/S25

P3.7/TA2.2/S24

P4.0/TB0.0/S23

P4.2/TB0.2/S21

P4.1/TB0.1/S22

P4.4/TB0.4/S19

P4.3/TB0.3/S20

P4.6/TB0.6/S17

P4.5/TB0.5/S18

P8.0/TB0CLK/S15

P4.7/TB0OUTH/SVMOUT/S16

P8.4 /S11/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6/R03

P2.7/P2MAP7/LCDREF/R13

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

MSP430F663x

SLAS566 –OCTOBER 2009

www.ti.com

Pin Designation, MSP430F6638IPZ, MSP430F6637IPZ, MSP430F6636IPZ

DRAFT ONLY

PRODUCT PREVIEW

100

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14

P7.7/CB11/A15

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2/R23

LCDCAP/R33

COM0

P5.3/COM1/S42

P9.7/S0

P9.6/S1

P9.5/S2

P9.4/S3

P9.3/S4

P9.2/S5

P9.1/S6

P9.0/S7

P8.7/S8

P8.6/UCB1SOMI/UCB1SCL/S9

P8.5/UCB1SIMO/UCB1SDA/S10

DVCC2

DVSS2

P2.0/P2MAP0

MSP430F6635

MSP430F6634

MSP430F6633

PZ PACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2/S36

P1.4/TA0.3/S35

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4/COM2/S41

P5.5/COM3/S40

P1.0/TA0CLK/ACLK/S39

P3.0/TA1CLK/CBOUT/S31

P3.1/TA1.0/S30

P3.2/TA1.1/S29

P1.6/TA0.1/S33

P1.7/TA0.2/S32

P1.1/TA0.0/S38

P1.2/TA0.1/S37

P1.5/TA0.4/S34

P3.3/TA1.2/S28

P3.4/TA2CLK/SMCLK/S27

P3.5/TA2.0/S26

P3.6/TA2.1/S25

P3.7/TA2.2/S24

P4.0/TB0.0/S23

P4.2/TB0.2/S21

P4.1/TB0.1/S22

P4.4/TB0.4/S19

P4.3/TB0.3/S20

P4.6/TB0.6/S17

P4.5/TB0.5/S18

P8.0/TB0CLK/S15

P4.7/TB0OUTH/SVMOUT/S16

P8.4 /S11/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6/R03

P2.7/P2MAP7/LCDREF/R13

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

MSP430F663x

www.ti.com

SLAS566 –OCTOBER 2009

Pin Designation, MSP430F6635IPZ, MSP430F6634IPZ, MSP430F6633IPZ

DRAFT ONLY

PRODUCT PREVIEW

100

P6.4/CB4

P6.5/CB5

P6.6/CB6

P6.7/CB7

P7.4/CB8

P7.5/CB9

P7.6/CB10

P7.7/CB11

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2/R23

LCDCAP/R33

COM0

P5.3/COM1/S42

P9.7/S0

P9.6/S1

P9.5/S2

P9.4/S3

P9.3/S4

P9.2/S5

P9.1/S6

P9.0/S7

P8.7/S8

P8.6/UCB1SOMI/UCB1SCL/S9

P8.5/UCB1SIMO/UCB1SDA/S10

DVCC2

DVSS2

P2.0/P2MAP0

MSP430F6632

MSP430F6631

MSP430F6630

PZ PACKAGE

(TOP VIEW)

P6.3/CB3

P6.2/CB2

P6.1/CB1

P6.0/CB0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2/S36

P1.4/TA0.3/S35

AVSS2

P5.6/DMAE0

P5.4/COM2/S41

P5.5/COM3/S40

P1.0/TA0CLK/ACLK/S39

P3.0/TA1CLK/CBOUT/S31

P3.1/TA1.0/S30

P3.2/TA1.1/S29

P1.6/TA0.1/S33

P1.7/TA0.2/S32

P1.1/TA0.0/S38

P1.2/TA0.1/S37

P1.5/TA0.4/S34

P3.3/TA1.2/S28

P3.4/TA2CLK/SMCLK/S27

P3.5/TA2.0/S26

P3.6/TA2.1/S25

P3.7/TA2.2/S24

P4.0/TB0.0/S23

P4.2/TB0.2/S21

P4.1/TB0.1/S22

P4.4/TB0.4/S19

P4.3/TB0.3/S20

P4.6/TB0.6/S17

P4.5/TB0.5/S18

P8.0/TB0CLK/S15

P4.7/TB0OUTH/SVMOUT/S16

P8.4 /S11/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6/R03

P2.7/P2MAP7/LCDREF/R13

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK/S14

P8.2/UCA1TXD/UCA1SIMO/S13

P8.3/UCA1RXD/UCA1SOMI/S12

MSP430F663x

SLAS566 –OCTOBER 2009

www.ti.com

Pin Designation, MSP430F6632IPZ, MSP430F6631IPZ, MSP430F6630IPZ

DRAFT ONLY

PRODUCT PREVIEW

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

C1 C2 C3 C11 C12

D1 D2 D4 D5 D6 D7 D8 D9 D11 D12

E1 E2 E4 E5 E6 E7 E8 E9 E11 E12

F1 F2 F4 F5 F8 F9 F11 F12

G1 G2 G4 G5 G8 G9 G11 G12

J1 J2 J4 J5 J6 J7 J8 J9 J11 J12

H1 H2 H4 H5 H6 H7 H8 H9 H11 H12

K1 K2 K11 K12

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12

M1 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12

ZQW PACKAGE

(TOP VIEW)

MSP430F663x

www.ti.com

SLAS566 –OCTOBER 2009

Pin Designation, MSP430F6638IZQW, MSP430F6637IZQW, MSP430F6636IZQW,

MSP430F6635IZQW, MSP430F6634IZQW, MSP430F6633IZQW, MSP430F6632IZQW,

MSP430F6631IZQW, MSP430F6630IZQW

DRAFT ONLY

PRODUCT PREVIEW

MSP430F663x

SLAS566 –OCTOBER 2009

www.ti.com

Terminal Functions

TERMINAL I/O

NO. DESCRIPTION

(1)

NAME PZ ZQW

General-purpose digital I/O

P6.4/CB4/A4 1 A1 I/O Comparator_B input CB4

Analog input A4 – ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O

P6.5/CB5/A5 2 B2 I/O Comparator_B input CB5

Analog input A5 – ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O

Comparator_B input CB6

P6.6/CB6/A6/DAC0 3 B1 I/O Analog input A6 – ADC (not available on '6632, '6631, '6630 devices)

DAC12.0 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)

General-purpose digital I/O

Comparator_B input CB7

P6.7/CB7/A7/DAC1 4 C2 I/O Analog input A7 – ADC (not available on '6632, '6631, '6630 devices)

DAC12.1 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)

General-purpose digital I/O

P7.4/CB8/A12 5 C1 I/O Comparator_B input CB8

Analog input A12 –ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O

P7.5/CB9/A13 6 C3 I/O Comparator_B input CB9

Analog input A13 – ADC (not available on '6632, '6631, '6630 devices)

General-purpose digital I/O

Comparator_B input CB10

P7.6/CB10/A14/DAC0 7 D2 I/O Analog input A14 – ADC (not available on '6632, '6631, '6630 devices)

DAC12.0 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)

General-purpose digital I/O

Comparator_B input CB11

P7.7/CB11/A15/DAC1 8 D1 I/O Analog input A15 – ADC (not available on '6632, '6631, '6630 devices)

DAC12.1 output (not available on '6635, '6634, '6633, '6632, '6631, '6630 devices)

General-purpose digital I/O

P5.0/VREF+/VeREF+ 9 D4 I/O Output of reference voltage to the ADC

Input for an external reference voltage to the ADC

General-purpose digital I/O

P5.1/VREF-/VeREF- 10 E4 I/O Negative terminal for the ADC's reference voltage for both sources, the internal

reference voltage, or an external applied reference voltage

E1,

AVCC1 11 Analog power supply

AVSS1 12 F2 Analog ground supply

XIN 13 F1 I Input terminal for crystal oscillator XT1

XOUT 14 G1 O Output terminal of crystal oscillator XT1

AVSS2 15 G2 Analog ground supply

General-purpose digital I/O

P5.6/ADC12CLK/DMAE0 16 H1 I/O Conversion clock output ADC (not available on '6632, '6631, '6630 devices)

DMA external trigger input