Texas Instruments TPS7A15 Manuel utilisateur
EVM User's Guide: TPS7A15EVM-096
TPS7A15EVM-096 Evaluation Module
Description
The TPS7A15 evaluation module (EVM) helps design
engineers evaluate the operation and performance
of the TPS7A15 linear regulator for use in their
own circuit application. The configuration of the
TPS7A15EVM-096 contains a single low-noise, small-
size, linear regulator for a wide range of applications.
The regulator is capable of delivering up to 400 mA
to the load with low VIN-to-VOUT dropout voltage. For
stability, use a minimum de-rated output capacitance
of 1.5 µF (or larger). An added high-performance
load transient circuit is included to improve the
measurement capability of the low-dropout (LDO)
regulator.
Get Started
1. Order the TPS7A15EVM-096 Evaluation Module
2. Download the TPS7A15EVM-096 User's Guide
Features
• Ultra-low input voltage range: 0.6 V to 2.2 V
• 1% accuracy over load, line and temperature
• High power-supply rejection ration (PSRR): 73 dB
at 1 kHz (VOUT = 0.8 V, IOUT = 400 mA)
• Available in fixed-output voltages: 0.5 V to 2.05 V
(in 25-mV steps)
• VBIAS range: Greater of 2.2 V or VOUT + 1.4 V to
5.5 V
• Active output discharge
Applications
•Camera modules
•Wireless headphones and ear buds
•Smart watches, fitness trackers
•Smart phones and tablets
•Portable medical devices
•Solid state drives (SSDs)
TPS7A15EVM-096 Hardware Board
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TPS7A15EVM-096 Evaluation Module 1
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1 Evaluation Module Overview
1.1 Introduction
This user's guide describes the operational use of the TPS7A15EVM-096 evaluation module (EVM) as a
reference design for engineering demonstration and evaluation of the TPS7A15 low-dropout linear regulator
(LDO). Included in this user's guide are setup and operating instructions, thermal and layout guidelines, a
printed-circuit board (PCB) layout, a schematic diagram, and a bill of materials (BOM).
Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous with the
TPS7A15EVM-096.
The Texas Instruments TPS7A15EVM-096 evaluation module (EVM) helps designers evaluate the operation and
performance of the TPS7A15 LDO voltage regulator. As shown in Table 1-1, the TPS7A15EVM-096 contains
one TPS7A15 LDO voltage regulator in the WSON package. An optional load transient circuit is also included
to assist the user with high-speed load transient testing. An input current loop is included that allows fast
measurements of the input current.
Required equipment and accessories:
1. TPS7A15EVM-096
2. VIN power supply rated to 2.2V. VENABLE rails.
3. VBIAS power supply rated to 5.5V.
4. VENABLE rated to 5.5V if not shorted to VIN
Optional equipment and accessories:
1. Power supply rated for Gate Driver IN+ and IN- rails.
2. Through hole RDC resistor.
3. 1210 RPULSE resistor.
4. Function generator to pulse the load transient circuit.
5. LeCroy™ AP015 or CP031 current probes.
6. SMA connectors for VIN and VOUT Sense lines for oscilloscope measurements.
1.2 Kit Contents
The package includes:
1. TPS7A15-096 evaluation module (EVM) version 1.0
2. EVM Disclaimer Read Me
3. Antistatic foam
What is Not Included
A TPS7A15-096 Evaluation User's Module. This PDF is available on ti.com.
1.3 Specification
The evaluation module provides banana cable input, output, and bias connections; along with SMA connections
for LDO Input and Output sense and driver VDD. Power supplies for VIN, VBIAS, VENABLE, IN+, IN-, and VDD
must be rated to meet the data sheet specifications. However, a function generator is recommended for the VDD
connection and the same specifications must be followed for the pulse waveform on VDD.
1.4 Device Information
Table 1-1. Device Information
EVM ORDERABLE NUMBER VOUT PART NAME PACKAGE
TPS7A15EVM-096 1.8 V TPS7A1518PDRVR 6-pin WSON
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2 Hardware
2.1 Setup
This section describes the jumpers and connectors on the EVM, and how to properly connect, set up, and use
the TPS7A15EVM-096. Section 2.1.1 and Section 2.1.3 describe the test setup and operation for the TPS7A15
LDO. Section 2.1.2 and Section 2.1.4 describe the test setup and operation of the optional load transient circuit.
2.1.1 LDO Input/Output Connector Descriptions
2.1.1.1 VIN and GND
VIN and GND are the connection terminals for the input supply. The VIN terminal is the positive connection, and
the GND terminal is the negative (that is, ground) connection.
2.1.1.2 BIAS and GND
BIAS and GND are the connection terminals for the bias supply. The BIAS terminal is the positive connection,
and the GND terminal is the negative (that is, ground) connection.
2.1.1.3 VOUT and GND
VOUT and GND are the connection terminals for the output load. The VOUT terminal is the positive connection,
and the GND terminal is the negative (that is, ground) connection.
2.1.1.4 EN
EN is a 3-pin header used to enable or disable the TPS7A15.
The center pin of the 3-pin header is tied to the TPS7A15 EN input. When the 2-pin shunt is placed across the
top two pins of the header, VIN is shorted to EN, and the TPS7A15 is enabled. When the 2-pin shunt is placed
across the bottom two pins of the header, GND is shorted to EN, and the TPS7A15 is disabled.
When driving the EN terminal with an off-board supply or signal generator, the applied voltage must be kept
between 0 V and 5.5 V.
2.1.2 Optional Load Transient Input/Output Connector Descriptions
2.1.2.1 VDD and GND
VDD and GND are the connection terminals for the input supply of the load transient circuit. The VDD terminal is
the positive connection, and the GND terminal is the negative (that is, ground) connection.
2.1.2.2 J13
J13 is an optional connection for the user to make measurements or apply loads to the output of the LDO.
2.1.2.3 J15
J15 is an optional connection to insert a damping circuit across the load transient MOSFET drain to source
voltage.
2.1.2.4 J16
J16 is an optional connection to insert capacitance or additional load across the drain to source of the load
transient MOSFET.
2.1.2.5 J18
J18 is the connection for the function generator to drive the gate driver device. J18 is terminated by the 50-Ω
resistor, R13.
2.1.2.6 J19
J19 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET
drain to source voltage.
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2.1.2.7 J22
J22 is a high-frequency kelvin connection that allows accurate measurements of the load transient MOSFET
gate to source voltage.
2.1.2.8 TP2, TP3, and TP4
TP2, TP3, and TP4 allow the user to measure the gate drive resistances R8 and R9 when power is turned off to
the EVM.
2.1.2.9 TP5
TP5 is the enable pin to enable the gate driver device. Tie this pin to GND to enable the gate driver.
2.1.3 TPS7A15 LDO Operation
The TPS7A15EVM-096 evaluation module contains the TPS7A15 LDO with input, bias, and output capacitors
installed. These four components provide the minimum required solution size, as illustrated by the white boxes
in Figure 1-1. Additional pads are available to test the LDO with additional input, bias, and output capacitors
beyond what is already installed on the EVM. The TPS7A15 LDO can be enabled or disabled by using the J7
3-pin header.
1. Place a 2-pin shunt across the header to tie VIN to EN to enable the device.
2. Place a 2-pin shunt across the header to tie GND to EN to disable the device.
Alternatively, by connecting an external function generator to TP1 (EN) and a nearby GND post (J11), the
user can enable or disable the TPS7A15 LDO after VIN is applied. Figure 2-1 shows the result of the
TPS7A15EVM-096 during turn on. The blue trace is the enable voltage, and the red trace is the output voltage.
Figure 2-1. TPS7A15EVM-096 Turn On
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If desired, a current probe can be inserted in the EVM as shown in Figure 2-2 to measure the input and output
current. The slots were sized to fit most current probes, such as the LeCroy™ AP015 or CP031 current probes.
Figure 2-2. TPS7A15EVM-096 With Current Probes Attached
The user has two options for providing a DC load on the output of the TPS7A15. J10 can be used to place a
DC load that flows through the current sense path on the output of the LDO. Alternatively, the J4 (VOUT) and
J12 (GND) banana connectors can be used for external measurements and loading; however, the IOUT loop
does not sense current flowing through these connectors. In cases where very fast transient tests are performed,
ringing can be observed on VIN or VOUT as a result of the parasitic inductance within the PCB of the EVM. A
strip of wire placed on the exposed copper in the current path can reduce this ringing. Select the correct size of
additional wire to fill the volume of the current probe. For most current probes, a 10 AWG wire can be used.
WARNING
The sensors of some current probes are tied to GND and cannot come into contact with energized
conductors. See the user manual of your current probe for details. If your current probe has this
limitation, use a thin strip of electrical or Kapton® tape to isolate the current sense path from the
current probe.
Optional kelvin sense points are provided using the SMA connectors J1 (VIN) and J2 (VOUT).
2.1.4 Optional Load Transient Circuit Operation
The TPS7A15EVM-096 evaluation module contains an optional high-performance load transient circuit to allow
efficient testing of the TPS7A15 LDO load transient performance. To use the optional load transient circuit, install
the correct components in accordance with the application. Modify the input and output capacitance connected
to the TPS7A15 LDO to match the expected operating conditions. Determine the desired peak current to test,
and modify the parallel resistor combination of R2, R3, R4, R5, and R6 as shown:
OUT
Peak
2 3 4 5 6
V
I
R R R R R
(1)
The slew rate of the load step can be adjusted by C11, R7, R8, and R9. In this section, only R8 and R9 is
adjusted to set the slew rate. For a 0-mA to 400-mA to 0-mA load step, use Table 2-1 to select a value of R8 and
R9 that results in the desired rise or fall time.
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Table 2-1. Suggested Ramp Rate Resistor Values
R8 R9 Rise/Fall Time
97.6 kΩ 86.6 kΩ 10 µs
52.3 kΩ 40.2 kΩ 5 µs
31.6 kΩ 20.5 kΩ 2.5 µs
12.4 kΩ 8.06 kΩ 1 µs
6.19 kΩ 4.02 kΩ 500 ns
3.74 kΩ 2.43 kΩ 300 ns
2.49 Ω 1.62 Ω 200 ns
806 Ω 806 Ω 100 ns
After the EVM is modified (if needed), connect a power supply to banana connectors J17 (VDD) and J21 (GND)
with a 5-V DC supply and a 1-A DC current limit. As illustrated in Figure 2-3, the TPS7A15 transient response is
very fast and the output voltage recovers in well under 1 ms after the initial load transient. Therefore, use a load
transient pulse duration limit of 1 ms to prevent excessive heating of the pulsed resistors (R2, R3, R4, R5, and
R6). Configure a function generator for the 50-Ω output, in a 0-V DC to 5-V DC square pulse. If necessary, burst
mode can be configured in the function generator for repetitive, low duty cycle, load transient testing.
A 10.7-kΩ resistor is installed on the EVM at R8, and a 10-kΩ resistor is installed on the EVM at R9. These
resistors provide approximately 1 A/μs slew rate from 0 mA to 400 mA. Figure 2-3 provides example test data
with R8 = 10.7 kΩ and R9 = 10 kΩ. The green trace is the output voltage and the blue trace is the output current.
J10 provides 1 mA of DC load current and R2, R3, R4, R5, and R6 provide 949 mA of pulsed load. The resulting
test data shows a 1-mA to 400-mA load step on VOUT of the LDO, with only a 2.2-μF capacitor on the output of
the LDO.
Figure 2-3. TPS7A15EVM-096 Load Transient Results: 1-mA to 400-mA Load Step
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3.1 Schematics
Figure 3-1 shows a schematic for the TPS7A15EVM-096.
Re vision History
Rev Note sAppro ve d byEC N # Appro ve d Da te
N/A N/A N/A N/A N/A
GND
10.0k
R9
1.00k
R10
1
2
3
J7
TP1
GND
GND
2.2µF
50V
C1
2.2µF
50V
C6
GND
2.2µF
10V
C4
2.2µF
10V
C7
10V
1uF
C5
10V
2.2uF
C8
J3 J4
J 12J 11
1
2
J8
1
2
3
4
5
J2
1
2
3
4
5
J1
VOUT
GND
VIN
Vin Re comm e nde d Max = 2.2V
Vout Ma x = 2.05V
Iout Max = 1A
1nF
100V
C16
TP2 TP4
VDD
A1 OUTH A2
OUTL B2
IN-
C2 GND B1
IN+
C1
LMG1020YFFR
U2
1
2
3
4
5
J18
J 17
VDD
J 21
GND
50V
10uF
C15
50V
10uF
C14
1.00k
R1
1
2
J 13
50V
0.1uF
C13
2.2µF
10V
C2
10V
2.2uF
C3
154
R5
154
R6
154
R4
154
R3
GND
EN
VIN
EN
VOUT
154
R2
100V
1pF
C11
0
R11
0
R7
3
5,6,84,7
1,2,
Q1
C S D173 13 Q2
1
2
3
4
5
J22 1nF
100V
C17
0
R12
J 15 J 16
1
2
3
4
5
J19
50V
0.015uF
C12
49.9
R13
GND
GND
J 20
TP5
1
2
J10
J6
J9
1 2
3 4
5 6
J 14
BIAS
BIAS SENSE
BIAS Re com me nde d Max = 5.5V
SENSE
J5
VDD
IN+
IN-
OUTL
10.7k
R8
OUTH
TP3
50V
0.1uF
C10
2.2µF
50V
C9
VDD Re c omm e nde d Max = 5.4V
R13 to be replaced with RMCF1206FT49R9
BIAS
4
EN
3
IN
6OUT 1
SENSE 2
Thermal_Pad 7
GND 5
TPS7A1518PDRVR
U1
Figure 3-1. Schematic
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3.2 Board Layout
Figure 3-2 through Figure 3-7 illustrate the board layout for the TPS7A15EVM-096 PCB.
The TPS7A15EVM-096 dissipates power, which can cause some components to experience an increase in
temperature. The TPS7A15 LDO, LMG1020YFFR gate driver, and pulsed resistors R2, R3, R4, R5, and R6 are
most at risk of raising to a high junction temperature during normal operation.
Figure 3-2. Top Assembly Layer and Silk Screen Figure 3-3. Top Layer Routing
Figure 3-4. Layer 2 Figure 3-5. Layer 3
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