Texas Instruments TIDA-070005 Mode d’emploi

TIDUEN1A–December 2018–Revised August 2019

3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

Load (POL) Reference Design

Design Guide: TIDA-070005

3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current

Sharing Point-of-Load (POL) Reference Design

Description

Some of the newest space grade FPGAs and ASICs

require low voltage and high currents for their core

power consumption, driving the need for a for space

grade DC/DC power conversion Point-of-Load POL

supply that provides a low voltage output and high

currents for their core power consumption. This

reference design provides a hardware example of POL

using four (4) TPS50601A-SP DC/DC converters in

quadrature to generate a 24-A supply, this reference

design guide also provides details on how to properly

configure, clock, and evaluate the reference design

hardware which includes one mother board and four

daughter boards.

Resources

TIDA-070005 Design Folder

TPS50601A-SP Product Folder

INA901-SP Product Folder

TPS7A4501-SP Product Folder

SE555-SP Product Folder

SN54HC74-SP Product Folder

SN54HC04-SP Product Folder

SN74AHC1G04 Product Folder

ASK Our E2E™ Experts

Features

• Stand-alone space rated clock generation

• Built-in current sense monitoring

• Multiple configurations to evaluate current sharing

of 2, 3, or 4 TPS50601A-SP POLs

• Built-in space-grade regulated power supply for

control logic and clocking

• Hardware support for mother and daughter board

• Ability for external clock generation and use

• Two board solution for ease of interchangeability of

design

• Guided design details for support to build

personalized solution for system needs

Applications

•Command and data handling

•Satellite electrical power system (EPS)

•Optical imaging payload

•Radar imaging payload

•Communications payload

Applications

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3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

Load (POL) Reference Design

An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other

important disclaimers and information.

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System Description

TIDUEN1A–December 2018–Revised August 2019

3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

Load (POL) Reference Design

1 System Description

The TIDA-070005 is a reference hardware example of a 24-A DC/DC power solution for space grade

applications. The newest space grade FPGAs and ASICs require high currents for their core power

consumption. These high current requirements drive a need for space grade DC/DC power conversion

circuitry. The TIDA-070005 design showcases the use of four TPS50601A-SP DC/DC converters in

quadrature to generate a 24-A supply. This design guide provides details on how to properly configure,

clock, and evaluate the TIDA-070005 which includes one mother board and four daughter boards.

The TPS50601A-SP DC/DC radiation hardened buck regulator is a 7-V, 6-A synchronous converter that

can be configured in master-slave mode to provide up to 12 A of output current using the sync pin while

sharing SS (soft-start), COMP (compensation), and EN (enable) pins.

The TIDA-070005 is a hardware reference design for the TPS50601A-SP. The design is intended to be

used as an example of how build and operate a solution with four TPS50601A-SP converters working in

quadrature to achieve a 24-A power solution while sharing the SS, COMP, and EN pins as described in

the TPS50601A-SP datasheet similar to parallel operation.

The TIDA-070005 hardware consists of two separate printed-circuit boards (PCBs). The first board is

referred to as the Mother Board and the second board is referred to as the daughter board. The Mother

board consists of the power management, clocking, and current sense capabilities on the design. The

daughter board consists of the TPS50601A-SP POL (point of load) buck converter, Vout settings, and

compensation networks for the design. In application four daughter boards connect to one mother board

via a set of individual headers for each board.

The design allows for a user to select between six different configurations to showcase the versatility of

combining the TPS50601A-SP in parallel and quadrature to generate a number of high current rails. The

TPS7A4501-SP LDO regulator provides the control circuitry power to the POL as well as the clocking

Integrated Circuits (IC) on the motherboard. The SE555-SP and 2 SN54HC74-SP work together to

generate a digital phase splitter, the digital phase splitter generates four clock signals all 90 degrees out of

phase to minimize noise in the system as well as maximize stability of the output current.

Current TI space rated solution only provide up to 6 A of output current. Large currents are needed to

drive future space grade FPGAs. This design provides a complete solution for providing up to 24 A of

current for the next gen FPGAs

1.1 Key System Specifications

Table 1. Mother Board Key System Specifications

PARAMETER DESCRIPTION SPECIFICATION

PVin Input power for the output stage of the switching regulators 3 to 7 V

Vin Input power for the control circuitry of the switching regulators 3 to 7 V

Vin_LDO_6V TPS7A4501-SP input power 2.5 to 20 V

Iout Load current 6 A/device - 24-A total

Table 2. Daughter Board Key System Specifications

PARAMETER DESCRIPTION SPECIFICATION

PVin Input power for the output stage of the switching regulators 3 to 7 V

Vin Input power for the control circuitry of the switching regulators 3 to 7 V

Iout Load current 6 A

System Description

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3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

Load (POL) Reference Design

1.2 Design Benefits

• Scalability

– Hardware can be used for evaluation of 1, 2, 3 or 4 buck regulators working together or separately

in multiple configurations.

– Hardware example can be scaled to greater current configurations with proper design and testing

• High Level of Integration

– All evaluation can be done with TIDA-070005 hardware, and external power supply/load

– Integrated current sense monitoring

– Integrated clocking and power management solution

• Multiple Clocking Options

– System design allows for externally generated clocking solutions

– System design allows for internally generated clocking solutions

TPS50601A-SP

MASTER

PHASE

VSENSE

COMP

SYNC

TPS50601A-SP

SLAVE

PHASE

VSENSE

COMP

SYNC

COMP1

SS1

VSENSE1

SS1

COMP1

VSENSE1

TPS50601A-SP

SLAVE

PHASE

VSENSE

COMP

SYNC

SS1

COMP1

VSENSE1

TPS50601A-SP

SLAVE

PHASE

VSENSE

COMP

SYNC

SS1

COMP1

VSENSE1

CLOCK, 0°

OUT OF

PHASE

CLOCK,

90° OUT

OF PHASE

CLOCK,

180° OUT

OF PHASE

CLOCK,

270° OUT

OF PHASE

VOUT

SE555M

SN54HC74-SP

CLOCK, 0° OUT OF PHASE

CLOCK, 90° OUT OF PHASE

CLOCK, 180° OUT OF PHASE

CLOCK, 270° OUT OF PHASE

TPS7A4501-SP

INA901-SP

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System Overview

TIDUEN1A–December 2018–Revised August 2019

3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

Load (POL) Reference Design

2 System Overview

2.1 Block Diagram

Figure 1. TIDA-070005 Block Diagram

2.2 Design Considerations

When using the TPS50601A-SP in master-slave mode (with either 1, 2 or 3 slaves), particular attention

must be paid to the passive component values calculation for the EN, SS and COMP pins. This is

because there is only set of passives (placed closely to the master) but they are connected to the

respective pins of all slave devices. Therefore, this factor (2, 3 or 4) must be taken into account depending

on the number of devices used in the configuration.

System Overview

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3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

Load (POL) Reference Design

2.3 Highlighted Products

The following section describes the important ICs that make up the TIDA-070005 24-A solution.

2.3.1 TPS50601A-SP

The TPS50601A-SP is a radiation hardened, 7-V, 6-A synchronous step-down converter, which is

optimized for small designs through high efficiency and integrating the high-side and low-side MOSFETs.

The device is offered in an ultra small, thermally enhanced 20-pin ceramic flatpack package.

The output voltage startup ramp is controlled by the SS/TR pin which allows operation as either a stand

alone power supply or in tracking situations. Power sequencing is also possible by correctly configuring

the enable and the open drain power good pins. In addition, the TPS50601A-SP can be configured in

master-slave mode to provide up to 12 A of output current.

Cycle-by-cycle current limiting on the high-side FET protects the device in overload situations and is

enhanced by a low-side sourcing current limit which prevents current runaway. There is also a low-side

sinking current limit which turns off the low-side MOSFET to prevent excessive reverse current. Thermal

shutdown disables the part when die temperature exceeds thermal shutdown temperature.

2.3.2 TPS7A4501-SP

The TPS7A4501-SP is a low-dropout (LDO) regulator optimized for fast-transient response. The 5962-

1222402VHA can supply 750 mA of output current with a dropout voltage of 300 mV. The

5962R1222403VXC can supply 1.5 A of output current with a dropout voltage of 320 mV. Quiescent

current is well controlled; it does not rise in dropout, as with many other regulators. In addition to fast

transient response, the TPS7A4501-SP regulator has very-low output noise, which makes it ideal for

sensitive RF supply applications.

Output voltage range is from 1.21 to 20 V. The TPS7A4501-SP is stable with output capacitance as low

as 10 µF. Small ceramic capacitors can be used without the necessary addition of ESR, as is common

with other regulators. Internal protection circuitry includes reverse-battery protection, current limiting,

thermal limiting, and reverse-current protection. The device is available as an adjustable device with a

1.21-V reference voltage. The 5962-1222402VHA is available in 10-pin CFP (U) package and

5962R1222403VXC is available in thermally-enhanced 10-pin CFP (HKU) package. Known good die

(KGD) option is available for both 5962-1222402V9A for non-RHA version and 5962R1222403V9A for

RHA

2.3.3 INA901-SP

The INA901-SP is a voltage-output, current-sense amplifier that can sense drops across shunt resistors at

common-mode voltages from –16 V to +80 V, independent of the supply voltage. The INA901-SP

operates from a single 2.7-V to 18-V supply, drawing 700 μA (typical) of supply current.

The gain of the INA901-SP is 20 V/V. The 130-kHz bandwidth simplifies use in current-control loops. The

pinouts readily enable filtering.

The device is specified over the extended operating temperature range of –55°C to 125°C and is offered

in an 8-pin CFP package.

2.3.4 SE555-SP

The SE555-SP is a precision timing circuit capable of producing accurate time delays or oscillation. In the

time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor

and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled

independently with two external resistors and a single external capacitor.

The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels

can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level,

the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold

input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can

override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-

flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between

discharge (DISCH) and ground.

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System Overview

TIDUEN1A–December 2018–Revised August 2019

3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

Load (POL) Reference Design

The output circuit is capable of sinking or sourcing current up to 100 mA. Operation is specified for

supplies of 4.5 to 16.5 V. With a 5-V supply, output levels are compatible with TTL inputs.

2.3.5 SN54HC74-SP

The SNx4HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at

the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other

inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time

requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock

triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-

time interval, data at the D input can be changed without affecting the levels at the outputs

2.3.6 SN54HC04-SP

The SNx4HC04 devices contain six independent inverters. They perform the Boolean function Y = A in

positive logic

2.3.7 SN74AHC1G04DCKR

The SN74AHC1G04 contains one inverter gate. The device performs the Boolean function Y = A.

Hardware, Software, Testing Requirements, and Test Results

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3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

Load (POL) Reference Design

3 Hardware, Software, Testing Requirements, and Test Results

3.1 Required Hardware

The TIDA-070005 consists of two boards, a mother board and 4 daughter boards. To get started with

using the hardware, see Section 3.2.

3.1.1 Hardware

3.1.1.1 Mother Board

The mother board consists of the system power, clocking circuitry, and current sense monitoring. The

mother board has four sockets in which four independent daughter boards can plug into via headers on

the board to be configured as desired by the user. The below sections detail the different subsystems

within the mother board.

3.1.1.1.1 System Power

The power stage of the mother board provides three different settings, each is described in the below

sections. The power stage is responsible for distributing three separate power rails. The first power rail is

PVin which is the input power rail to the output stage of the TPS50601A-SP DC/DC buck reg. The second

power rail is Vin which is the input power to the control logic for the TPS50601A-SP. The third power

stage is the input power rail to the output power stage of the TPS7A4501-SP LDO; the LDO's output

powers the ICs that make up the clocking stage of the mother board as well as the INA901-SP current

sense monitor.

Table 3. Mother Board Power Settings

Jumper Power Option 1 Power Option 1 Power Option 1

R143 Y Y DNP

R116 Y Y DNP

R144 Y DNP DNP

R200 Y DNP DNP

3.1.1.1.1.1 Pvin == Vin == Vin_LDO_6V = 6 V

In the simplest configuration R143, R116, R144, and R200 are all populated and a 6-V supply and its

respective ground is connected to the board via J100 and J103. The 6-V supply then powers the PVIn and

Vin of all TPS50601A-SP POLs on each daughter board plugged into the mother board. The 6-V rail also

supplies power to the TPS7A4501-SP and the downstream clocking ICs on the mother board

3.1.1.1.1.2 PVin == Vin = Desired Input Voltage to POL; Vin_LDO_6V = 6 V

In the second configuration R143 and R116 are populated and R144 and R200 are DNP (Do Not

Populate). This configuration allows for more flexibility as the input voltage to the POLs in the system can

now be altered to specific design specifications for evaluation. The range for PVin and Vin is 3- to 7-V DC.

A power supply and its respective ground is connected to the board by J100 and J10 to provide the power

to PVin and Vin via banana cables. A 6-V power supply is then connected to J113 for power to the

TPS7A4501-SP with the positive and negative terminals connected to pin 1 and pin 2, respectively.

3.1.1.1.1.3 All Rails Independently Powered

In the third configuration each of the three power rails are independently supplied their respected power

and R143, R116, R144, and R200 are all DNP. In this configuration banana cables are connected to J100

and J103 for the PVin power of the converters. Pins 4 and 3 are Vin and GND for the POL converters

respectively and should be connected to a power supply. Pins 1 and 2 are Vin_LDO_6V and GND

respectively for the inputs to the TPS7A4501-SP and will also need their own power supply.

Figure 2 shows the configuration of the TPS7A4501-SP in the system.

J201

5V IC power power

20V

47uF

C205

25V

10uF

C204

50V

0.1uF

C206

49.9

R201

10.0k

R204

3.20k

R238

100V

470pF

C203 20V

22uF

C201

50V

0.1uF

C202

5Vdc

GND

Vin_LDO

OFF

ENABLE

SHDN

OUT 6

OUT 7

OUT 8

SENSE/ADJ 9

GND 10

PAD 11

TPS7A4501HKU/EM

U200

Power_Nets

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Hardware, Software, Testing Requirements, and Test Results

TIDUEN1A–December 2018–Revised August 2019

3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

Load (POL) Reference Design

Figure 2. TPS7A4501-SP Design Schematic

The TPS7A4501-SP has an adjustable output voltage range of 1.21 to 20 V. The output voltage is set by

the ratio of two external resistors, R1 and R2, as shown in the device datasheet. The device maintains the

voltage at the ADJ pin at 1.21 V referenced to ground. The current in R1 is then equal to (1.21 V/R1), and

the current in R2 is the current in R1 plus the ADJ pin bias current. The ADJ pin bias current, 3 µA at

25°C, flows through R2 into the ADJ pin. Calculate the output voltage using Equation 2 of the datasheet

shown below.

The value of R1 should be less than 4.17 kΩto minimize errors in the output voltage caused by the ADJ

pin bias current. Note that in shutdown the output is turned off, and the divider current is zero.

3.1.1.1.2 System Clocking

There are three clocking configurations available in the TIDA-070005 discussed as follows.

3.1.1.1.2.1 Quadrature Clocking

This configuration implements a digital phase splitter to generate the quadrature clock. A 555 timer must

be set to output at 2×f the desired end switching frequency of the POL. With the output connected to the

gate terminal of an N type FET, we can capture two square wave clock signals operating at 2×f and 180°

out of phase with one another. These signals are called 555_clock_2fa and 555_clock2fb as shown in

Figure 3. Both of these signals are fed to two separate D flip flops. Note that the D flip flops only latch on

the rising edge of the clock. The clock 2×f frequency that is 180° out of phase with another generates two

individual rising clock signals to the two respective D flip flops 90° shifted with respect to the desired

frequency of the POLs which is 1/2 the 2×f frequency being fed to the flip flops. Capturing the Q and Qnot

output of each of the D flip flops will then result in 4 outputs 90° out of phase with one another and

operating at the desired switching frequency of the POLs as shown in Section 2.2.

D Q

CLK

D Q

CLK

0°

90°

Input2f

0°

90°

Q200

2N7002E-T1-E3

5Vdc

1000pF

C208

0.01uF

C207

GND

1.00k

R203

555_clock_2fa 555_clock_2fb

GND 1

TRIG

OUT 3

RESET

CONT 5

THRES

DISCH 7

VCC

SE555MU201

453

R205

453

R202

D200

BAT54-7-F

Power_Nets

Hardware, Software, Testing Requirements, and Test Results

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3- to 7-VIN, 24-A IOUT, 0.95-VOUT, Space-Grade Current Sharing Point-of-

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Figure 3. SE555-SP Design Schematic

Figure 4. Quadrature Clock

As shown in Figure 3, adding R205 to the circuit and connecting the trigger input to the threshold input

causes the timer to self-trigger and run as a multivibrator. The capacitor C208 charges through R202 and

R205 and then discharges through R205 only. Therefore, the duty cycle is controlled by the values of

R202 and R205

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