Texas Instruments OMAP5912 Manuel utilisateur

OMAP5912 Multimedia Processor

Device Overview and Architecture

Reference Guide

Literature Number: SPRU748A

March 2004

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OMAP5912SPRU748A

Preface

Read This First

About This Manual

This document introduces the setup, components, and features of the

OMAP5912 multimedia processor and provides a high-level view of the device

architecture.

Notational Conventions

This document uses the following conventions.

-Hexadecimal numbers are shown with the suffix h. For example, the

following number is 40 hexadecimal (decimal 64): 40h.

Related Documentation From Texas Instruments

The following documents describe the OMAP5910 device and related

peripherals. Copies of these documents are available on the Internet at

www.ti.com. Tip: Enter the literature number in the search box provided at

www.ti.com.

OMAP5912 Multimedia Processor Device Overview and Architecture

Reference Guide (literature number SPRU748) introduces the setup,

components, and features of the OMAP5912 multimedia processor and

provides a high-level view of the device architecture.

OMAP5912 Multimedia Processor OMAP 3.2 Subsystem Reference

Guide (literature number SPRU749) introduces and briefly defines the

main features of the OMAP3.2 subsystem of the OMAP5912 multimedia

processor.

OMAP5912 Multimedia Processor DSP Sybsystem Reference Guide (lit-

erature number SPRU750) describes the OMAP5912 multimedia proc-

essor DSP subsystem. The digital signal processor (DSP) subsystem is

built around a core processor and peripherals that interface with: 1) The

ARM926EJS via the microprocessor unit interface (MPUI); 2) Various

standard memories via the external memory interface (EMIF); 3) Various

system peripherals via the TI peripheral bus (TIPB) bridge.

Related Documentation From Texas Instruments

4OMAP5912 SPRU748A

OMAP5912 Multimedia Processor Clocks Reference Guide (literature

number SPRU751) describes the clocking mechanisms of the

OMAP5912 multimedia processor. In OMAP5912, various clocks are

created from special components such as the digital phase locked loop

(DPLL) and the analog phase-locked loop (APLL).

OMAP5912 Multimedia Processor Initialization Reference Guide (litera-

ture number SPRU752) describes the reset architecture, the configura-

tion, the initialization, and the boot ROM of the OMAP5912 multimedia

processor.

OMAP5912 Multimedia Processor Power Management Reference Guide

(literature number SPRU753) describes power management in the

OMAP5912 multimedia processor. The ultralow-power device (ULPD)

generates and manages clocks and reset signals to OMAP3.2 and to

some peripherals. It controls chip-level power-down modes and handles

chip-level wake-up events. In deep sleep mode, this module is still active

to monitor wake-up events.This book describes the ULPD module and

outline architecture.

OMAP5912 Multimedia Processor Security Features Reference Guide

(literature number SPRU754) describes the security features of teh

OMAP5912 multimedia processor. The OMAP5912 security scheme re-

lies on the OMAP3.2 secure mode. The distributed security on the

OMAP3.2 platform is a Texas Instruments solution to address m-com-

merce and security issues within a mobile phone environment. The

OMAP3.2 secure mode was developed to bring hardware robustness to

the overall OMAP5912 security scheme.

OMAP5912 Multimedia Processor Direct Memory Access (DMA) Support

Reference Guide (literature number SPRU755) describes the direct

memory access support of the OMAP5912 multimedia processor. The

OMAP5912 processor has three DMAs:

JThe system DMA is embedded in OMAP3.2. It handles DMA

transfers associated with MPU and shared peripherals.

JThe DSP DMA is embedded in OMAP3.2. It handles DMA

transfers associated with DSP peripherals.

JThe generic distributed DMA (GDD) is an OMAP5912 resource

attached to the SSI peripheral. It handles only DMA transfers

associated with the SSI peripheral.

Related Documentation From Texas Instruments

OMAP5912SPRU748A

OMAP5912 Multimedia Processor Memory Interfaces Reference Guide

(literature number SPRU756) describes the memory interfaces of the

OMAP5912 multimedia processor.

JSDRAM (external memory interface fast, or EMIFF)

JAsynchronous and synchronous burst memory (external

memory interface slow, or EMIFS)

JNAND flash (hardware controller or software controller)

JCompactFlash on EMIFS interface

JInternal static RAM

OMAP5912 Multimedia Processor Interrupts Reference Guide (literature

number SPRU757) describes the interrupts of the OMAP5912 multime-

dia processor. Three level 2 interrupt controllers are used in

OMAP5912:

JOne MPU level 2 interrupt handler (also referred to as MPU

interrupt level 2) is implemented outside of OMAP3.2 and can

handle 128 interrupts.

JOne DSP level 2 interrupt handler (also referred to as DSP

interrupt level 2.1) is instantiated outside of OMAP3.2 and can

handle 64 interrupts.

JOne OMAP3.2 DSP level 2 interrupt handler (referenced as DSP

interrupt level 2.0) can handle 16 interrupts.

OMAP5912 Multimedia Processor Peripheral Interconnects Reference

Guide (literature number SPRU758) describes various periperal inter-

connects of the OMAP5912 multimedia processor.

OMAP5912 Multimedia Processor Timers Reference Guide (literature

number SPRU759) describes various timers of the OMAP5912 multime-

dia processor.

OMAP5912 Multimedia Processor Serial Interfaces Reference Guide (lit-

erature number SPRU760) describes the serial interfaces of the

OMAP5912 multimedia processor.

OMAP5912 Multimedia Processor Universal Serial Bus (USB) Reference

Guide (literature number SPRU761) describes the universal serial bus

(USB) host on the OMAP5912 multimedia processor. The OMAP5912

processor provides several varieties of USB functionality. Flexible multi-

plexing of signals from the OMAP5912 USB host controller, the

OMAP5912 USB function controller, and other OMAP5912 peripherals

allow a wide variety of system-level USB capabilities. Many of the

OMAP5912 pins can be used for USB-related signals or for signals from

other OMAP5912 peripherals. The OMAP5912 top-level pin multiplexing

Related Documentation From Texas Instruments

6OMAP5912 SPRU748A

controls each pin individually to select one of several possible internal pin

signal interconnections. When these shared pins are programmed for

use as USB signals, the OMAP5912 USB signal multiplexing selects how

the signals associated with the three OMAP5912 USB host ports and the

OMAP5912 USB function controller can be brought out to OMAP5912

pins.

OMAP5912 Multimedia Processor Multi-channel Buffered Serial Ports

(McBSPs) Reference Guide (literature number SPRU762) describes

the three multi-channel buffered serial ports (McBSPs) available on the

OMAP5912 device. The OMAP5912 device provides multiple high-

speed multichannel buffered serial ports (McBSPs) that allow direct in-

terface to codecs and other devices in a system.

OMAP5912 Multimedia Processor Camera Interface Reference Guide (lit-

erature number SPRU763) describes two camera inerfaces implement-

ed in the OMAP5912 multimedia processor: compact serial camera port

and camera parallel interface.

OMAP5912 Multimedia Processor Display Interface Reference Guide (lit-

erature number SPRU764) describes the display interface of the

OMAP5912 multimedia processor.

JLCD module

JLCD data conversion module

JLED pulse generator

JDisplay interface

OMAP5912 Multimedia Processor Multimedia Card (MMC/SD/SDIO) (liter-

ature number SPRU765) describes the multimedia card (MMC) interface

of the OMAP5912 multimedia processor. The multimedia card/secure

data/secure digital IO (MMC/SD/SDIO) host controller provides an inter-

face between a local host, such as a microprocessor unit (MPU) or digital

signal processor (DSP), and either an MMC or SD memory card, plus up

to four serial flash cards. The host controller handles MMC/SD/SDIO or

serial port interface (SPI) transactions with minimal local host interven-

tion.

OMAP5912 Multimedia Processor Keyboard Interface Reference Guide

(literature number SPRU766) describes the keyboard interface of the

OMAP5912 multimedia processor. The MPUIO module enables direct

I/O communication between the MPU (through the public TIPB) and ex-

ternal devices. Two types of I/O can be used: specific I/Os dedicated for

8 x 8 keyboard connection, and general-purpose I/Os.

OMAP5912 Multimedia Processor General-Purpose Interface Reference

Guide (literature number SPRU767) describes the general-purpose in-

Related Documentation From Texas Instruments

OMAP5912SPRU748A

terface of the OMAP5912 multimedia processor. There are four GPIO

modules in the OMAP5912. Each GPIO peripheral controls 16 dedicated

pins configurable either as input or output for general purposes. Each pin

has an independent control direction set by a programmable register.

The two−edge control registers configure events (rising edge, falling

edge, or both edges) on an input pin to trigger interrupts or wake−up re-

quests (depending on the system mode). In addition, an interrupt mask

the set and clear capabilities on the data output registers and the inter-

rupt mask registers. After detection, all event sources are merged and

a single synchronous interrupt (per module) is generated in active mode,

whereas a unique wake−up line is issued in idle mode. Eight data output

lines of the GPIO3 are ORed together to generate a global output line at

the OMAP5912 boundary. This global output line can be used in conjunc-

tion with the SSI to provide a CMT−APE interface to the OMAP5912.

OMAP5912 Multimedia Processor VLYNQ Serial Communications Inter-

face Reference Guide (literature number SPRU768) describes the

VLYNQ of the OMAP5912 multimedia processor.

VLYNQ is a serial communications interface that enables the extension

of an internal bus segment to one or more external physical devices. The

external devices are mapped into local, physical address space and ap-

pear as if they are on the internal bus of the OMAP 5912. The external

devices must also have a VLYNQ interface. The VLYNQ module serial-

izes bus transactions in one device, transfers the serialized data be-

tween devices via a VLYNQ port, and de-serializes the transaction in the

external device.

OMAP5912 includes one VLYNQ module connected on OCPT2 target

port and OCPI initiator port. These connections are configured via a stat-

ic switch, which selects either SSI or VLYNQ module. This switch, for-

bids the simultaneous use of GDD/SSI and VLYNQ. The switch is con-

trolled by the VLYNQ_EN bit in the OMAP5912 configuration control reg-

ister (CONF_5912_CTRL).

OMAP5912 Multimedia Processor Pinout Reference Guide (literature

number SPRU769) provides the pinout of the OMAP5912 multimedia

processor. After power-up reset, the user can change the configuration

of the default interfaces. If another interface is available on top of the de-

fault, it is possible to enable a new interface for each ball by setting the

corresponding 3-bit field of the associated FUNC_MUX_CTRL register.

It is also possible to configure on-chip pullup/pulldown. This document

Trademarks

8OMAP5912 SPRU748A

also describes the various power domains so that the user can apply the

different interfaces seamlessly with external components.

OMAP5912 Multimedia Processor Window Tracer (WT) Reference Guide

(literature number SPRU770) describes the window tracer module used

to capture the memory transactions from four interfaces: EMIFF, EMIFS,

OCP-T1, and OCP-T2. This module is located in the OMAP3.2 traffic

controller (TC).

OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (lit-

erature number SPRUxxx) describes the real-time clock of the

OMAP5912 multimedia processor. The real-time clock (RTC) block is an

embedded real-time clock module directly accessible from the TIPB bus

interface.

Trademarks

OMAP and the OMAP symbol are trademarks of Texas Instruments.

Contents

OMAP5912SPRU748A

Contents

1 Overview 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Subsystems 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 SDRAM/DDRAM Memory Interface 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Synchronous/Asynchronous Burst Memory Interface 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 CompactFlash 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Other Memory Types 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Serial Interfaces 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 Camera and Display Interfaces 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.8 Emulation and Test Interfaces 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.9 General-Purpose Interfaces 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.10 Interfaces Multiplexing 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.11 OMAP5912 Interface Usage Examples 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.11.1 Audio Interfaces 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.11.2 Bluetooth Interface 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.11.3 Modem Connection 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 OMAP5912 Description 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 OMAP3.2 Gigacell 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 OMAP5912 Module Descriptions 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Clock and Reset Generation 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32-kHz Oscillator 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12-MHz Oscillator 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ultralow-Power Device (ULPD) 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OMAP5912 Clock and Reset Architecture 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Peripherals Subsystem 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LDCONV 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CompactFlash Controller 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Frame Adjustment Counter (FAC) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Light Pulse Generator (LPG) 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SHA-1/MD5 Accelerator 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DES_3DES Accelerator 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Random Number Generator 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Camera Interface 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Real-Time Counter 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OS Timer 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulse Width Time (PWT) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

10 OMAP5912 SPRU748A

Pulse Width Length (PWL) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HDQ/1-Wire Battery Monitoring Serial Interface 33. . . . . . . . . . . . . . . . . . . . . . . . . .

MCSI1 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MCSI2 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

mWire 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MPU GPIOs 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Keyboard 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UARTs 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

UART Clocking Scheme 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Available I/Os per UART 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP1 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP2 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

McBSP3 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Port Interface (SPI) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Inter-Integrated Circuit (I2C) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

USB On-The-Go (OTG) 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GPIO 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32-Bit Dual-Mode Timer 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32-kHz Synchronization Counter 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Watchdog 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Compact Camera Port (CCP) 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Synchronous Serial Interconnect 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SoSSI 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MMC/SDIO 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VLYNQ 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Other Modules 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG TAP Controller 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

eFuse Modules 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Boot Device Configuration 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Boot ROM 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Security Layer 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Generic Distributed DMA (GDD) 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 OMAP5912 Wake-up Capabilities 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 OMAP5912 Pin Description 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table des matières

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