NXP Semiconductors MPC5746R Manuel utilisateur

MPC5746R

SPC5746R Microcontroller

Data Sheet

Features

• This document provides electrical specifications, pin

assignments, and package diagrams for the MPC5746R

series of microcontroller units (MCUs).

• For functional characteristics, see the MPC5746R

Microcontroller Reference Manual.

NXP Semiconductors Document Number MPC5746R

Data Sheet: Technical Data Rev. 6, 06/2017

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Table of Contents

1 Introduction........................................................................................3

1.1 Block diagram......................................................................... 3

2 Package pinouts and signal descriptions............................................5

3 Absolute maximum ratings................................................................ 6

4 Electromagnetic Compatibility (EMC)..............................................7

5 Electrostatic discharge (ESD)............................................................ 7

6 Operating conditions.......................................................................... 8

7 DC electrical specifications................................................................11

8 I/O pad specification.......................................................................... 12

8.1 Input pad specifications...........................................................12

8.2 Output pad specifications........................................................15

8.3 I/O pad current specifications................................................. 17

9 Reset pad (PORST, RESET) electrical characteristics...................... 18

10 Oscillator and FMPLL....................................................................... 22

11 ADC modules.....................................................................................26

11.1 ADC input description............................................................ 26

11.2 SAR ADC................................................................................26

11.3 S/D ADC................................................................................. 29

12 Temperature sensor............................................................................ 39

13 LVDS fast asynchronous serial transmission (LFAST) pad

electrical characteristics..................................................................... 40

13.1 LFAST interface timing diagrams...........................................40

13.2 LFAST and MSC /DSPI LVDS interface electrical

characteristics..........................................................................42

14 LFAST PLL electrical characteristics................................................45

15 Aurora LVDS electrical characteristics............................................. 46

16 Power management PMC POR LVD sequencing..............................47

16.1 Power management electrical characteristics..........................47

16.1.1 Recommended power transistors............................47

16.1.2 Power management integration.............................. 48

16.1.3 Regulator example for the NJD2873 transistor...... 50

16.1.4 Regulator example for the 2SCR574d transistor.... 51

16.1.5 Device voltage monitoring......................................51

16.1.6 Power up/down sequencing.................................... 53

17 Flash memory specifications..............................................................54

17.1 Flash memory program and erase specifications.................... 54

17.2 Flash memory Array Integrity and Margin Read

specifications...........................................................................55

17.3 Flash memory module life specifications................................55

17.4 Data retention vs program/erase cycles...................................56

17.5 Flash memory AC timing specifications.................................57

17.6 Flash read wait state and address pipeline control settings.....58

18 AC specifications............................................................................... 58

18.1 Debug and calibration interface timing...................................58

18.1.1 JTAG interface timing............................................ 58

18.1.2 Nexus interface timing............................................61

18.1.3 Aurora LVDS interface timing............................... 63

18.2 DSPI timing with CMOS and LVDS...................................... 65

18.2.1 DSPI master mode full duplex timing with CMOS

and LVDS pads.......................................................66

18.2.2 DSPI CMOS slave mode........................................ 78

18.3 FEC timing.............................................................................. 80

18.3.1 MII-lite receive signal timing (RXD[3:0],

RX_DV, RX_ER, and RX_CLK)...........................80

18.3.2 MII-lite transmit signal timing (TXD[3:0],

TX_EN, TX_ER, TX_CLK)...................................81

18.3.3 MII-lite async inputs signal timing (CRS and

COL)....................................................................... 82

18.3.4 MII-lite serial management channel timing

(MDIO and MDC).................................................. 82

18.3.5 RMII serial management channel timing (MDIO

and MDC)............................................................... 83

18.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)84

18.3.7 RMII transmit signal timing (TXD[1:0], TX_EN). 85

18.4 UART timings.........................................................................86

18.5 eMIOS timing..........................................................................86

19 Obtaining package dimensions.......................................................... 86

20 Thermal characteristics...................................................................... 87

20.1 General notes for specifications at maximum junction

temperature..............................................................................89

21 Ordering information......................................................................... 90

22 Revision history................................................................................. 91

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

2 NXP Semiconductors

1 Introduction

The MPC5746R family of 32-bit microcontrollers is the latest achievement in integrated

automotive application controllers. It belongs to an expanding range of automotive-

focused products designed for flexibility to support a variety of applications. The

advanced and cost-efficient host processor core of the MPC5746R automotive controller

family complies with the Power Architecture embedded category. It operates at speeds as

high as 200 MHz and offers high-performance processing optimized for low power

consumption. It capitalizes on the available development infrastructure of current Power

Architecture devices and is supported with software drivers, operating systems, and

configuration code to assist with users' implementations. This section contains detailed

information on power considerations, DC/AC electrical characteristics, and AC timing

specifications.

Note

Within this document, VDD_HV_IO refers to supply pins VDD_HV_IO_MAIN,

VDD_HV_IO_JTAG, VDD_HV_IO_FEC, and VDD_HV_IO_MSC

Introduction

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 3

1.1 Block diagram

MPC5746R

Safety Lake

Ethernet

LFAST & SIPI

64ch. eDMA

w/ E2E Ecc

DMACHMUX

w/ E2E Ecc

64ch. eDMA

Delay RCCU

Concentrator

w/ E2E Ecc

50 MHz

Nexus Data

Trace

Concentrator

w/ E2E Ecc

100 MHz

Nexus Data Trace

32 ADD

32 DATA

32 ADD

32 DATA

Slow Cross Bar Switch (AMBA 2.0 v6 AHB) - 32 bit - 100 MHz

System Memory Protection Unit (SMPU_1)

M3 M4

M1M2

AIPS PBridge_0

E2E Ecc

Decorate Storage

50MHz

AIPS PBridge_1

E2E Ecc

Decorate Storage

50MHz

32 ADD

32 DATA

32 ADD

32 DATA

Peripheral

Cluster A Peripheral

Cluster B

Peripherals allocation to the bridges is

based on safety and pinout

requirements

Double INTC

SWT_1

STM_1

E200 z425 - 200 MHz

Main Core_1

DSP

VLE

Scalar

SP-FPU

Nexus3p

I -Mem ctrl

I-Cache ctrl

16kB

IMEM

8kB - 2way

D -Mem ctrl

32kB

DMEM

Core Memory Protection Unit (CMPU)

BIU with E2E ECC

32 ADD

64 DATA

Instruction

32 ADD

64 DATA

Load/

Store

32 ADD

64 DATA

Instruction Load/

Store

32 ADD

64 DATA

M3 M0

S1 S4

Fast Cross Bar Switch (AMBA 2.0 v6 AHB) - 64 bit - 200 MHz

System Memory Protection Unit (SMPU_0)

SWT_0

STM_0

E200 z425 - 200 MHz

Main Core_0

DSP

VLE

Scalar

SP-FPU

Nexus3p

I -Mem ctrl

I-Cache ctrl

16kB

IMEM

8kB - 2way

D -Mem ctrl

32kB

DMEM

Core Memory Protection Unit (CMPU)

BIU with E2E ECC

w/ E2E Ecc

Unified Backdoor I/F

w/ E2E Ecc

Unified Backdoor I/F

DSP

VLE

Scalar

SP-FPU

I -Mem ctrl

I-Cache ctrl

D -Mem ctrl

Core Memory Protection Unit (CMPU)

BIU with E2E ECC

w/ E2E Ecc

Unified Backdoor I/F

Nexus RWA

E200 z424 - 200 MHz

Checker Core_0s

Computational Shell - Fast Domain 200MHz

32 ADD

64 DATA

32 ADD

64 DATA

32 ADD

64 DATA

SRAM Ctrl

w/ E2E Ecc

Decorated

access

Intelligent

Bridging

Bus gasket

Standby

Supply

FLASH Controller

Dual Ported

Incl. Set-Associative

Prefetch Buffers

w/ E2E Ecc

Overlay

Backdoor

for

system

RAM

SRAM

224KB

Standby

SRAM

32KB

Standby

Regulator

Overlay

RAM

16kB

Flash

4MB

EEPROM

256k

256 Page Line

2 stage Pipeline

NVM (Single Module)

Calibration

Bus

Buddy

Device

Interface

JTAGM JTAGC DCI SPU

Nexus

Aurora

Router

Delayed Lock-step

with Redundnacy

Checkers

Delay

RCCU

Safety Lake

Peripheral Domain - 50 MHz

Figure 1. Core block diagram

Introduction

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

4 NXP Semiconductors

DMAMUX_3

FlexCAN_3

FlexCAN_1

CRC_1

CMU

FCCU

eMIOS_1

DSPI_M1

DSPI_3

DSPI_1

SENT_1

LINFlex_M1

LINFlex_3

LINFlex_1

ADC_SD_1

ADC_SAR_3

ADC_SAR_1

LINFlex_M0

LINFlex_2

LINFlex_0

FlexCAN_2

FlexCAN_0

PMC

PCU

DECFILTER_1

BAR

SSCM

PASS

CFLASH

LFAST

Zipwire

SIUL2

CGM

BCTU

PLLs

XOSC

RCOSC

RGM

PIT

DMAMUX_0

DMAMUX_1

DMAMUX_2

WKPU

DSPI_M0

DSPI_4

DSPI_2

DSPI_0

DECFILTER_0

PIT_RTI

ATX

MEMU

JTAGM

STCU2

JDC

TDM

ADC_SD_2

ADC_SD_0

ADC_SAR_2

ADC_SAR_0

SENT_0

DTS

CRC_0

REACM

eTPU_0 Reg.

eTPU_0 Code.

RAM

eTPU_0 Par.

eMIOS_0

FEC

eDMA

3x SWT

2x STM

INTC

SEMA4

PFLASH

PCM

PRAM

2 x SMPU

2x XBIC

PERIPHERAL CLUSTER B

PERIPHERAL CLUSTER A

IGF

PBRIDGE_1

2x XBAR

PBRIDGE_0

EIM

Figure 2. Peripherals allocation

2Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual.

Package pinouts and signal descriptions

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 5

3 Absolute maximum ratings

Functional operating conditions are given in the DC electrical specifications. Absolute

maximum voltages are stress ratings only, and functional operation at the maxima is not

guaranteed. Stress beyond listed maxima may affect device reliability or cause permanent

damage to the device.

Table 1. Absolute maximum ratings

Symbol Parameter Conditions1Value Unit

Min Max

Cycle Lifetime power cycles — 1000k —

VDD_LV 1.2 V core supply voltage 2, 3, 4— –0.3 1.5 V

VDD_LV_BD Emulation module voltage2, 3, 4— –0.3 1.5 V

VDD_HV_IO_MAIN I/O supply voltage5— –0.3 6.0 V

VDD_HV_IO_JTAG Crystal oscillator and JTAG supply Reference to VSS –0.3 6.0 V

VDD_HV_IO_FEC FEC supply voltage Not using Ethernet Reference to

VSS

–0.3 6.0 V

VDD_HV_IO_MSC MSC supply voltage Reference to VSS –0.3 6.0 V

VDD_HV_PMC Power Management Controller supply

voltage 6—–0.3 6.0 V

VDD_HV_FLA Decoupling pin for flash regulator6— –0.3 — V

VDDSTBY RAM standby supply voltage6— –0.3 6.0 V

VSS_HV_ADV_SD S/D ADC ground voltage Reference to VSS –0.3 0.3 V

VSS_HV_ADV_SAR SAR ADC ground voltage Reference to VSS –0.3 0.3 V

VDD_HV_ADV_SAR SAR ADC supply voltage Reference to VSS_HV_ADV_SAR –0.3 6.0 V

VDD_HV_ADV_SD S/D ADC supply voltage Reference to VSS_HV_ADV_SD –0.3 6.0 V

VSS_HV_ADR_SD S/D ADC ground reference Reference to VSS –0.3 0.3 V

VSS_HV_ADR_SAR SAR ADC ground reference Reference to VSS –0.3 0.3 V

VDD_HV_ADR_SAR SAR ADC alternate reference Reference to VSS_HV_ADR_SAR –0.3 6.0 V

VDD_HV_ADR_SD S/D ADC alternate reference Reference to VSS_HV_ADR_SD –0.3 6.0 V

VDD_LV_BD - VDD_LV Emulation module supply differential to 1.2

V core supply —–0.3 1.5 V

VSS – VSS_HV_ADR_SAR VSS_HV_ADR_SAR differential voltage — –0.3 0.3 V

VSS – VSS_HV_ADR_SD VSS_HV_ADR_SD differential voltage — –0.3 0.3 V

VSS – VSS_HV_ADV_SAR VSS_HV_ADV_SAR differential voltage — –0.3 0.3 V

VSS – VSS_HV_ADV_SD VSS_HV_ADV_SD differential voltage — –0.3 0.3 V

VIN I/O input voltage range7— –0.3 6.0 V

Relative to VSS_HV_IO, 8, 9–0.3 —

Relative to VDD_HV_IO8, 9— 0.3

IINJD Maximum DC injection current for digital

pad

Per pin, applies to all digital pins –5 5 mA

Table continues on the next page...

Absolute maximum ratings

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

6 NXP Semiconductors

Table 1. Absolute maximum ratings (continued)

Symbol Parameter Conditions1Value Unit

Min Max

IINJA Maximum DC injection current for analog

pad

Per pin, applies to all analog pins –5 5 mA

IMAXSEG10, 11 Maximum current per I/O segment — –120 120 mA

TSTG Storage temperature range and non-

operating times —–55 175 °C

STORAGE Maximum storage time, assembled part

programmed in ECU

No supply; storage temperature

in range –40 °C to 60 °C

— 20 yrs

TSDR Maximum solder temperature12

Pb-free package —— 260 °C

MSL Moisture sensitivity level13 — — 3 —

1. Voltage is referenced to VSS unless otherwise noted.

2. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ= 150 °C, remaining time as defined in note -1 and

note -1.

3. Allowed 1.375 – 1.45 V for 10 hours cumulative time at maximum TJ= 150 °C, remaining time as defined in note -1.

4. 1.32 – 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at

maximum TJ= 150 °C.

5. Allowed 5.5 – 6.0 V for 10 hours cumulative time at maximum TJ= 150 °C, remaining time at or below 5.0 V +10%.

6. Allowed 3.6 – 4.5 V for 10 hours cumulative time at maximum TJ= 150 °C, remaining time at or below 3.3 V +10%. This is

an internally regulated supply. Values given are for reference only.

7. The maximum input voltage on an I/O pin tracks with the associated I/P supply maximum. For the injection current

condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin

to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominal

calculations.

8. Relative value can be exceeded, if design measures are taken to ensure injection current limitation (parameters IINJD and

IINJA).

9. VDD_HV_IO/VSS_HV_IO refers to supply pins and corresponding grounds: VDD_HV_IO_MAIN, VDD_HV_IO_JTAG, VDD_HV_IO_FEC,

VDD_HV_IO_MSC.

10. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDD_HV_IO power segment is

defined as one or more GPIO pins located between two VDD_HV_IO supply pins.

11. The average current values given in the "I/O pad current specifications" section should be used to calculate total I/O

segment current.

12. Solder profile per IPC/JEDEC J-STD-020D.

13. Moisture sensitivity per JEDEC test method A112.

4 Electromagnetic Compatibility (EMC)

EMC measurements to IC-level IEC standards are available from NXP on request.

5Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device.

Electromagnetic Compatibility (EMC)

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 7

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for

Automotive Grade Integrated Circuits.

Device failure is defined as: "If after exposure to ESD pulses, the device does not meet

the device specification requirements, which includes the complete DC parametric and

functional testing at room temperature and hot temperature. Maximum DC parametrics

variation within 10% of maximum specification."

Table 2. ESD ratings

Parameter Conditions Value Unit

ESD for Human Body Model (HBM)1All pins 2000 V

ESD for field induced Charged Device Model (CDM)2All pins 500 V

1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing

2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level

6 Operating conditions

The following table describes the operating conditions for the device, and for which all

specifications in the data sheet are valid, except where explicitly noted.

The device operating conditions must not be exceeded in order to guarantee proper

operation and reliability.

NOTE

All power supplies need to be powered up to ensure normal

operation of the device.

Table 3. Device operating conditions

Symbol Parameter Conditions Value Unit

Min Typ Max

Frequency

fSYS Device operating frequency1TJ-40 °C to 150 °C — — 200 MHz

Temperature

TJOperating temperature range -

junction

–40.0 — 150.0 °C

TA(TLto TH) Operating temperature range -

ambient

–40.0 — 125.0 °C

Voltage

VDD_LV External core supply voltage2, 3LVD/HVD enabled 1.2 — 1.32 V

LVD/HVD disabled4, 5, 61.18 — 1.38

VDD_HV_IO_MAIN I/O supply voltage 73.5 — 5.5 V

Table continues on the next page...

Operating conditions

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

8 NXP Semiconductors

Table 3. Device operating conditions (continued)

Symbol Parameter Conditions Value Unit

Min Typ Max

VDD_HV_IO_FEC FEC I/O supply voltage85 V range 3.5 — 5.5 V

3.3 V range 3.0 — 3.6

VDD_HV_IO_MSC MSC I/O supply voltage95 V range 3.5 — 5.5 V

3.3 V range 3.0 — 3.6

VDD_HV_IO_JTAG10 JTAG I/O supply voltage11 5 V range 3.5 — 5.5 V

3.3 V range 3.0 — 3.6

VDD_HV_PMC12 Power Management Controller

(PMC) supply voltage

Full functionality 3.5 — 5.5 V

VDDSTBY13 RAM standby supply voltage14 — 1.3 — 5.9 V

VSTBY_BO Standby RAM brownout voltage — — — 0.9 V

VDD_LV_STBY_SW Standby RAM switch VDD_LV voltage

threshold —0.95 — — V

VDD_HV_ADV_SD S/D ADC supply voltage15, 16 — 4.5 — 5.5 V

VDD_HV_ADV_SAR SAR ADC supply voltage

17 —3.0 — 5.5 V

VDD_HV_ADR_SD S/D ADC reference — 3.0 — 5.5 V

VDD_HV_ADR_SD –

VDD_HV_ADV_SD

S/D ADC reference differential

voltage —— — 25 mV

VSS_HV_ADR_SD –

VSS_HV_ADV_SD

VSS_HV_ADR_SD differential voltage —–25 — 25 mV

VDD_HV_ADR_SAR SAR ADC reference — 3.0 — 5.5 V

VDD_HV_ADR_SAR –

VDD_HV_ADV_SAR

SAR ADC reference differential

voltage —— — 25 mV

VSS_HV_ADR_SAR –

VSS_HV_ADV_SAR

VSS_HV_ADR_SAR differential voltage —–25 — 25 mV

VSS_HV_ADV_SD – VSS VSS_HV_ADV_SD differential voltage — –25 — 25 mV

VSS_HV_ADV_SAR – VSS VSS_HV_ADV_SAR differential voltage — –25 — 25 mV

VRAMP_VDD_LV Slew rate on power supply pins

(VDD_LV)

Ramp up 0.069 — 100 V/ms

Ramp down 0.0345 — 100

VRAMP_VDD_HV_IO_MAIN,

VRAMP_VDD_HV_PMC

Slew rate on power supply pins

(VDD_HV_IO_MAIN,

VDD_HV_PMC)

Ramp up 0.148 — 100 V/ms

Ramp down 0.125 — 100

Injection current

IIC DC injection current (per pin)18, 19, 20 Digital pins and analog pins –3.0 — 3.0 mA

IMAXSEG Maximum current per power

segment21, 22 —–80 — 80 mA

1. Maximum operating frequency is applicable to the computational cores and platform for the device.

2. Core voltage as measured on device pin to guarantee published silicon performance.

3. During power ramp, voltage measured on silicon might be lower. maximum performance is not guaranteed, but correct

silicon operation is guaranteed. See power management and reset management for description.

4. Maximum core voltage is not permitted for entire product life. See absolute maximum rating.

5. When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor

externally supply voltage may result in erroneous operation of the device.

Operating conditions

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 9

6. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during the

reset sequence, and the LVD/HVD are active until that point.

7. The pad are operative till 3.0V full performance. The IRC oscillator is supplied by this pin and it is setting the min voltage

limit.

8. FEC will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of

IO_MAIN.

9. MSC will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of

IO_MAIN.

10. If XOSC is enabled via DCF_UTEST_Miscellaneous[XOSC_EN], VDD_HV_IO_JTAG must be within the operating range

before RESET pin is released.

11. JTAG will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of

IO_MAIN.

12. The startup of flash regulator and memory initialization immediately after Phase0 of reset sequence could cause a drop of

the PMC supply. No LVD event will be generated as during this time the LVD monitors are not enabled.

13. VDDSTBY supply must be present before and after power up/down of the device supplies and the ramp rate should be less

than 33.3 kV/s.

14. RAM retention is not guaranteed below 1.3 V, but no effect on RAM operation for voltages below 1.3 V when VDD_LV is

above the minimum value.

15. For supply voltages between 3.6V and 4.5V there will be no guaranteed precision of ADC (accuracy/linearity). ADC will

recover to a fully functional state when the voltage rises above 4.5V.

16. VDD_HV_ADV_SD must be higher or equal than the VDD_HV_ADV_SAR supply to guarantee full performance. It is recommended

to connect the VDD_HV_ADV_SD to VDD_HV_ADV_SAR at board level.

17. Temperature Sensor and its associated Band-Gap reference are supplied by this pin. The temperature sensor

performance is guaranteed only between 4.5 V and 5.5 V.

18. Full device lifetime without performance degradation.

19. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the

absolute maximum ratings table for maximum input current for reliability requirements.

20. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is

above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network

calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. For more

information, see the device characterization report.

21. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A VDD_HV_IO power segment is

defined as one or more GPIO pins located between two VDD_HV_IO supply pins.

22. The average current values given in the "I/O pad current specifications" section should be used to calculate total I/O

segment current.

Table 4. Emulation (buddy) device operating conditions

Symbol Parameter Conditions Value Unit

Min Typ Max

Frequency

— Standard JTAG 1149.1/1149.7 frequency — — — 50 MHz

— High-speed debug frequency — — — 320 MHz

— Data trace frequency — — — 1250 MHz

Temperature

TJ_BD Device junction operating temperature range Packaged devices –40.0 — 150.0 °C

TA _BD Ambient operating temperature range Packaged devices –40.0 — 125.0 °C

Voltage

VDD_LV_BD Buddy core supply voltage — 1.18 — 1.32 V

VDD_HV_IO_B

Buddy I/O supply voltage — 3.0 — 5.5 V

VRAMP_BD Buddy slew rate on power supply pins — — — 500 V/ms

Operating conditions

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

10 NXP Semiconductors

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Cypress

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Texas Instruments

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CYPRES

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Texas Instruments

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Espressif Systems

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Abov

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Laird

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