NXP Semiconductors Freescale K22 Manuel utilisateur

K22 Sub-Family Reference Manual

Supports: MK22FX512VLK12, MK22FN1M0VLK12

Document Number: K22P80M120SF5RM

Rev. 4, November 2014

K22 Sub-Family Reference Manual, Rev. 4, November 2014

2 Freescale Semiconductor, Inc.

Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................53

1.1.1 Purpose.........................................................................................................................................................53

1.1.2 Audience......................................................................................................................................................53

1.2 Conventions..................................................................................................................................................................53

1.2.1 Numbering systems......................................................................................................................................53

1.2.2 Typographic notation...................................................................................................................................54

1.2.3 Special terms................................................................................................................................................54

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................55

2.2 Module Functional Categories......................................................................................................................................55

2.2.1 ARM® Cortex™-M4 Core Modules...........................................................................................................56

2.2.2 System Modules...........................................................................................................................................57

2.2.3 Memories and Memory Interfaces...............................................................................................................58

2.2.4 Clocks...........................................................................................................................................................59

2.2.5 Security and Integrity modules....................................................................................................................59

2.2.6 Analog modules...........................................................................................................................................59

2.2.7 Timer modules.............................................................................................................................................60

2.2.8 Communication interfaces...........................................................................................................................61

2.2.9 Human-machine interfaces..........................................................................................................................62

2.3 Orderable part numbers.................................................................................................................................................62

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................65

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Section number Title Page

3.2 Core modules................................................................................................................................................................65

3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................65

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................67

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................73

3.2.4 JTAG Controller Configuration...................................................................................................................74

3.3 System modules............................................................................................................................................................75

3.3.1 SIM Configuration.......................................................................................................................................75

3.3.2 System Mode Controller (SMC) Configuration...........................................................................................76

3.3.3 PMC Configuration......................................................................................................................................76

3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................77

3.3.5 MCM Configuration....................................................................................................................................79

3.3.6 Crossbar Switch Configuration....................................................................................................................80

3.3.7 Memory Protection Unit (MPU) Configuration...........................................................................................82

3.3.8 Peripheral Bridge Configuration..................................................................................................................85

3.3.9 DMA request multiplexer configuration......................................................................................................86

3.3.10 DMA Controller Configuration...................................................................................................................88

3.3.11 External Watchdog Monitor (EWM) Configuration....................................................................................89

3.3.12 Watchdog Configuration..............................................................................................................................91

3.4 Clock modules..............................................................................................................................................................92

3.4.1 MCG Configuration.....................................................................................................................................92

3.4.2 OSC Configuration......................................................................................................................................93

3.4.3 RTC OSC configuration...............................................................................................................................94

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Section number Title Page

3.5 Memories and memory interfaces.................................................................................................................................94

3.5.1 Flash Memory Configuration.......................................................................................................................94

3.5.2 Flash Memory Controller Configuration.....................................................................................................98

3.5.3 SRAM Configuration...................................................................................................................................99

3.5.4 System Register File Configuration.............................................................................................................102

3.5.5 VBAT Register File Configuration..............................................................................................................103

3.5.6 EzPort Configuration...................................................................................................................................104

3.5.7 FlexBus Configuration.................................................................................................................................105

3.6 Security.........................................................................................................................................................................108

3.6.1 CRC Configuration......................................................................................................................................108

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3.7 Analog...........................................................................................................................................................................109

3.7.1 16-bit SAR ADC Configuration..................................................................................................................109

3.7.2 CMP Configuration......................................................................................................................................115

3.7.3 12-bit DAC Configuration...........................................................................................................................117

3.7.4 VREF Configuration....................................................................................................................................118

3.8 Timers...........................................................................................................................................................................119

3.8.1 PDB Configuration......................................................................................................................................120

3.8.2 FlexTimer Configuration.............................................................................................................................123

3.8.3 PIT Configuration........................................................................................................................................127

3.8.4 Low-power timer configuration...................................................................................................................128

3.8.5 CMT Configuration......................................................................................................................................130

3.8.6 RTC configuration.......................................................................................................................................131

3.9 Communication interfaces............................................................................................................................................132

3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................132

3.9.2 CAN Configuration......................................................................................................................................138

3.9.3 SPI configuration.........................................................................................................................................140

3.9.4 I2C Configuration........................................................................................................................................143

3.9.5 UART Configuration...................................................................................................................................144

3.9.6 SDHC Configuration....................................................................................................................................147

3.9.7 I2S configuration..........................................................................................................................................148

3.10 Human-machine interfaces...........................................................................................................................................151

3.10.1 GPIO configuration......................................................................................................................................151

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................153

4.2 System memory map.....................................................................................................................................................153

4.2.1 Aliased bit-band regions..............................................................................................................................154

4.3 Flash Memory Map.......................................................................................................................................................155

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................156

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4.4 SRAM memory map.....................................................................................................................................................157

4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory map....................................................................................157

4.5.1 Read-after-write sequence and required serialization of memory operations..............................................157

4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................158

4.5.3 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................161

4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................165

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................167

5.2 Programming model......................................................................................................................................................167

5.3 High-Level device clocking diagram............................................................................................................................167

5.4 Clock definitions...........................................................................................................................................................168

5.4.1 Device clock summary.................................................................................................................................169

5.5 Internal clocking requirements.....................................................................................................................................171

5.5.1 Clock divider values after reset....................................................................................................................171

5.5.2 VLPR mode clocking...................................................................................................................................172

5.6 Clock Gating.................................................................................................................................................................172

5.7 Module clocks...............................................................................................................................................................172

5.7.1 PMC 1-kHz LPO clock................................................................................................................................174

5.7.2 WDOG clocking..........................................................................................................................................174

5.7.3 Debug trace clock.........................................................................................................................................175

5.7.4 PORT digital filter clocking.........................................................................................................................175

5.7.5 LPTMR clocking..........................................................................................................................................176

5.7.6 USB FS OTG Controller clocking...............................................................................................................176

5.7.7 FlexCAN clocking.......................................................................................................................................177

5.7.8 UART clocking............................................................................................................................................177

5.7.9 SDHC clocking............................................................................................................................................178

5.7.10 I2S/SAI clocking..........................................................................................................................................178

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Section number Title Page

Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................181

6.2 Reset..............................................................................................................................................................................182

6.2.1 Power-on reset (POR)..................................................................................................................................182

6.2.2 System reset sources....................................................................................................................................182

6.2.3 MCU Resets.................................................................................................................................................186

6.2.4 Reset Pin .....................................................................................................................................................188

6.2.5 Debug resets.................................................................................................................................................188

6.3 Boot...............................................................................................................................................................................189

6.3.1 Boot sources.................................................................................................................................................189

6.3.2 Boot options.................................................................................................................................................190

6.3.3 FOPT boot options.......................................................................................................................................190

6.3.4 Boot sequence..............................................................................................................................................191

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................193

7.2 Power Modes Description.............................................................................................................................................193

7.3 Entering and exiting power modes...............................................................................................................................195

7.4 Power mode transitions.................................................................................................................................................196

7.5 Power modes shutdown sequencing.............................................................................................................................197

7.6 Module Operation in Low Power Modes......................................................................................................................198

7.7 Clock Gating.................................................................................................................................................................201

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................203

8.2 Flash Security...............................................................................................................................................................203

8.3 Security Interactions with other Modules.....................................................................................................................204

8.3.1 Security interactions with FlexBus..............................................................................................................204

8.3.2 Security Interactions with EzPort................................................................................................................204

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8.3.3 Security Interactions with Debug.................................................................................................................204

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................207

9.1.1 References....................................................................................................................................................209

9.2 The Debug Port.............................................................................................................................................................209

9.2.1 JTAG-to-SWD change sequence.................................................................................................................210

9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................210

9.3 Debug Port Pin Descriptions.........................................................................................................................................211

9.4 System TAP connection................................................................................................................................................211

9.4.1 IR Codes.......................................................................................................................................................211

9.5 JTAG status and control registers.................................................................................................................................212

9.5.1 MDM-AP Control Register..........................................................................................................................213

9.5.2 MDM-AP Status Register............................................................................................................................215

9.6 Debug Resets................................................................................................................................................................216

9.7 AHB-AP........................................................................................................................................................................217

9.8 ITM...............................................................................................................................................................................218

9.9 Core Trace Connectivity...............................................................................................................................................218

9.10 Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................218

9.11 Coresight Embedded Trace Buffer (ETB)....................................................................................................................219

9.11.1 Performance Profiling with the ETB...........................................................................................................219

9.11.2 ETB Counter Control...................................................................................................................................220

9.12 TPIU..............................................................................................................................................................................220

9.13 DWT.............................................................................................................................................................................220

9.14 Debug in Low Power Modes........................................................................................................................................221

9.14.1 Debug Module State in Low Power Modes.................................................................................................222

9.15 Debug & Security.........................................................................................................................................................222

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Chapter 10

Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................223

10.2 Signal Multiplexing Integration....................................................................................................................................223

10.2.1 Port control and interrupt module features..................................................................................................224

10.2.2 PCRn reset values for port A.......................................................................................................................224

10.2.3 Clock gating.................................................................................................................................................224

10.2.4 Signal multiplexing constraints....................................................................................................................224

10.3 Pinout............................................................................................................................................................................225

10.3.1 K22 Signal Multiplexing and Pin Assignments...........................................................................................225

10.3.2 K22 Pinouts..................................................................................................................................................228

10.4 Module Signal Description Tables................................................................................................................................229

10.4.1 Core Modules...............................................................................................................................................230

10.4.2 System Modules...........................................................................................................................................230

10.4.3 Clock Modules.............................................................................................................................................231

10.4.4 Memories and Memory Interfaces...............................................................................................................231

10.4.5 Analog..........................................................................................................................................................234

10.4.6 Timer Modules.............................................................................................................................................236

10.4.7 Communication Interfaces...........................................................................................................................238

10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................240

Chapter 11

Port control and interrupts (PORT)

11.1 Introduction...................................................................................................................................................................243

11.2 Overview.......................................................................................................................................................................243

11.2.1 Features........................................................................................................................................................243

11.2.2 Modes of operation......................................................................................................................................244

11.3 External signal description............................................................................................................................................245

11.4 Detailed signal description............................................................................................................................................245

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