NXP Semiconductors Freescale MC92604 Manuel utilisateur

MC92604

Dual GEt Design

Verification Board

User’s Guide

MC92604DVBUG

Rev. 1, 06/2005

Blank

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1

Freescale Semiconductor iii

Contents

Paragraph Page

Number Title Number

Chapter 1

General Information

1.1 Introduction...................................................................................................................... 1-1

1.2 Design Verification Board Features................................................................................. 1-2

1.3 Specifications................................................................................................................... 1-2

1.4 Abbreviation List ............................................................................................................. 1-3

1.5 Related Documentation.................................................................................................... 1-3

1.6 Block Diagram................................................................................................................. 1-4

1.7 Board Components .......................................................................................................... 1-5

1.8 Contact Information......................................................................................................... 1-5

Chapter 2

Hardware Preparation and Installation

2.1 Unpacking Instructions .................................................................................................... 2-1

2.2 MC92604DVB Package Contents ................................................................................... 2-1

2.3 Hardware Preparation ...................................................................................................... 2-2

2.3.1 Setting the Power Supply and Voltage Regulators ...................................................... 2-3

2.3.2 Setting the Voltage Regulators..................................................................................... 2-3

2.4 Reference Clock Source................................................................................................... 2-3

2.4.1 Using the Onboard Oscillators..................................................................................... 2-4

2.4.2 External Reference Clock Source................................................................................ 2-4

2.4.3 Supplying a Clock to the MC92604 ............................................................................ 2-5

2.4.4 3.3V_CLK_OUTnSMA Connectors .......................................................................... 2-5

2.4.5 Clock Frequency Selection .......................................................................................... 2-5

2.5 Interface Components ...................................................................................................... 2-6

2.5.1 Parallel Inputs and Outputs.......................................................................................... 2-6

2.5.1.1 Parallel Inputs .......................................................................................................... 2-7

2.5.1.2 Parallel Outputs ....................................................................................................... 2-7

2.5.2 +VDDQ and Ground (GND) Access Connections........................................................ 2-7

2.5.3 Serial Inputs and Outputs............................................................................................. 2-7

2.6 Special Application Connections..................................................................................... 2-8

2.7 Special Test Connection................................................................................................... 2-8

2.8 Test Traces ....................................................................................................................... 2-8

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1

iv Freescale Semiconductor

Paragraph Page

Number Title Number

Chapter 3

Laboratory Equipment and Quick Setup Evaluation

3.1 Recommended Laboratory Equipment ............................................................................ 3-1

3.2 Quick Setup Data-Eye Diagram ...................................................................................... 3-3

3.2.1 Quick Setup Data-Eye Generation and Observation ................................................... 3-3

3.2.1.1 Equipment Setup...................................................................................................... 3-3

3.2.1.2 Parallel Input Connections....................................................................................... 3-4

3.2.1.3 Basic Eye Observation—Test Procedure................................................................. 3-6

3.2.2 Quick Setup Bit Error Rate Checking.......................................................................... 3-8

3.2.2.1 Equipment Setup...................................................................................................... 3-8

3.2.2.2 Parallel I/O Connections.......................................................................................... 3-8

3.2.2.3 Quick Setup BERC Test Procedure ......................................................................... 3-9

Chapter 4

Test Setups

4.1 Serial Link Verification Using a Serial Bit Error Rate Tester (BERT) ............................ 4-1

4.1.1 Test Setup for Full-Speed Mode .................................................................................. 4-2

4.1.2 Test Setup for Half-Speed Modes................................................................................ 4-3

4.2 Jitter Testing..................................................................................................................... 4-4

4.2.1 Jitter Test System Calibration ...................................................................................... 4-4

4.2.2 Reference Clock Jitter Transfer Test............................................................................ 4-5

4.2.3 Reference Clock Jitter Tolerance Test ......................................................................... 4-6

4.2.4 Data Jitter Tolerance Test............................................................................................. 4-7

Appendix A

Connector Signals

A.1 Input: 2×10 (0.100") Connectors.................................................................................... A-1

A.1.1 Control Signal Input Connectors ................................................................................ A-1

A.1.2 Transmitter Parallel Data Input Connectors ............................................................... A-3

A.2 Output: 2×20 (0.100") Connectors................................................................................. A-5

A.3 JTAG Connector ............................................................................................................. A-6

A.4 MDIO Connector ............................................................................................................ A-7

A.5 SFP_CTRL Connector.................................................................................................... A-8

Appendix B

Parts List

B.1 Design Verification Board Parts List ...............................................................................B-1

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1

Freescale Semiconductor v

Paragraph Page

Number Title Number

Appendix C

Prescaler for Jitter Measurement

C.1 Divide-by-xx Prescaler Description .................................................................................C-1

C.2 Prescaler Components......................................................................................................C-2

Appendix D

Revision History

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1

vi Freescale Semiconductor

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MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1

Freescale Semiconductor 1-1

Chapter 1

General Information

1.1 Introduction

This user’s guide describes the MC92604DVB design verification board for the MC92604 integrated

circuit. The design verification board (DVB) facilitates the full evaluation of the MC92604 Dual Gigabit

Ethernet transceiver (GEt). It should be read in conjunction with the MC92604 Dual Gigabit Ethernet

Transceiver Reference Guide. This design verification board is intended for evaluation and testing

purposes only. Freescale does not guarantee its performance in a production environment.

This board was designed to be used with laboratory equipment (pattern generators, data analyzers, BERT,

scopes, etc.) or connected to other evaluation boards. Access to the MC92604 device (verification chip) is

through connectors to each pin, to allow complete in-depth ‘design verification’ testing of the chip design.

This allows the user to check any or all features/functions of the MC92604 GEt device.

The two parallel data input ports and all configuration/control signal pins, are accessed through common

2×10, 0.100" male connectors (headers). The parallel data output ports are accessed through 2×20, 0.100"

connectors. Device JTAG and MDIO port signals are also accessed with separate connectors.

The MC92604 high-speed serial receivers and transmitters are accessed via SMA coaxial connectors for

signal integrity measurements. Gigabit Ethernet fiber media evaluations can be made with the provided

small form-factor pluggable (SFP) socket on the DVB, and an MSA (multi-source agreement) compliant

transceiver. To use this SFP socket, four short coax cables are required to connect the SFP socket to the

device’s transmitter and receiver SMA connectors.

A single 5.0-V power source is required for the DVB operation. All necessary voltages are generated by

regulators onboard. The reference clock for the MC92604 chip may be provided using either an external

clock or the onboard crystal oscillator. Clock drivers on the DVB provide additional clock signals for

triggering analyzer instrumentation and scopes.

General Information

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1

1-2 Freescale Semiconductor

1.2 Design Verification Board Features

The functional, physical, and performance features of the MC92604DVB are as follows:

• A single external 5.0-V to onboard regulators supply power to all onboard circuitry.

• Reference clock source is a 250-MHz crystal oscillator or an external clock source.

• IEEE Std 802.3-2002® compliant GMII or TBI interfaces accessible through standard 0.100",

2 row connectors for data generators and analyzers.

• The full-duplex differential data links accessible through SMA connectors.

• Two pairs of 50-Ωtest traces with SMA connections facilitate TDR measurements of the

characteristic impedance of representative board traces.

• Connectors provided for JTAG and MDIO ports

• SFP socket provided for MSA-compliant fiber modules

• IEEE Std 1394b (bilingual) socket provided for standard cable links

1.3 Specifications

The MC92604DVB design verification board specifications are provided in Table 1-1.

Table 1-1. MC92604DVB Design Verification Board Specifications

Characteristics Specifications

Board revision A

External power supply +5 V DC ± 0.5 V DC < 1.5 A typical

Support circuit regulator 3.3 V ± 0.3 V DC

MC92604 core and link I/O regulator 1.8 V ± 0.15 V DC

Interface I/O (VDDQ) regulator 2.5 V ± 0.2 or 3.3 V ± 0.3 V DC

MC92604 package 196 MAPBGA

Operating temperature 0°−30°C

Material FR-4

Dimensions Height 11.2", 287 mm

Width 9.35", 238 mm

Thickness 0.062", 1.6 mm

Conducting layers Four ground planes, one split power plane, three signal routing layers, top and

bottom component layers with some additional signal routing.

General Information

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1

Freescale Semiconductor 1-3

1.4 Abbreviation List

Table 1-2 contains abbreviations used in this document.

1.5 Related Documentation

Related documentation includes the following:

•MC92604 Dual Gigabit Ethernet Transceiver Reference Guide (MC92604RM)

• MC92604DVB schematics

• MC100ES6222 data sheet

• MPC9456 data sheet

• IEEE Std 802.3-2002, Part 3: Carrier sense multiple access with collision detection (CSMA/CD)

access method and physical layer specifications

Table 1-2. Acronyms and Abbreviated Terms

Term Meaning

‘1’ High logic level (nominally 2.5 or 3.3 V)

‘0’ Low logic level (nominally 0.0 V)

BIST Built-in self-test

DVB Design verification board

I/F Interface

MDIO Management data input/output port

MSA Multi-source agreement

N/C No connection

PN Pseudo-noise

PRBS Pseudo random bit sequence

SFP Small form-factor pluggable (fiber optics module)

TAP Test access port

TDR Time delay reflectometry

UIp-p Peak-to-peak unit interval

General Information

MC92604 Dual GEt Design Verification Board User’s Guide, Rev. 1

1-4 Freescale Semiconductor

1.6 Block Diagram

Figure 1-1. MC92604DVB Design Verification Board Block Diagram

MC92604

2×20, 0.100"

2×10, 0.100" Connectors

A_XCLK

+3.3-V

Regulator

+2.5- to 3.5-V

Regulator

+5 V

MC100 MPC9456

Horizontal 50-Ω

Te s t Tr a c e s

Vertical 50-Ω

Te s t Tr a c e s

JTAG

Control

RECV_B

RECV_A

XMIT_A

XMIT_B

MDIO

2×10, 0.100"

SW1

Connectors

CLK_IN

RLINK_A

RLINK_B

XLINK_A

XLINK_B

TST1 TST2

TST5 TST6

TST3 TST7

TST4 TST8

0.100" Connector

+VDDQ/GND

R22V1

R12V

+3.3 V

TPA

GND

+1.8-V

Regulator

R22V

3.3V_CLK_OUT2

3.3V_CLK_OUT3

X-TAL

Osc 3.3V_CLK_OUT4

CLK_B_PG

CLK_A_PG

ES6222

3.3V_CLK_OUT1

LA1

LA2

PG11

PG8

PG9

DDQ

+1.8 V

GEt

B_XCLK

Connectors

SFP

1394b

2×8, 0.100"

Connector

X-TAL

Osc

REF_CLK

RECV_B

Status LEDs

RECV_A

Status LEDs

T3,4

PG11

PG14

PG1 PG3

PG2 PG13

PG4

PG10

PG12

DIFF_CLK_OUT5

DIFF_CLK_OUT6

Table des matières

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