NXP Semiconductors K32W061 Manuel utilisateur

K32W061

K32W061/K32W041 User

Manual

UM11323

Rev. 1.1 — June 2020 User manual

Document information

Info Content

Keywords Arm Cortex-M4, microcontroller, Zigbee, Thread, Bluetooth Low Energy

Abstract K32W061/41 User Manual

User manual Rev. 1.1 — June 2020 2 of 350

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

NXP Semiconductors UM11323

K32W061/41 User manual

11111111

Revision history

Rev Date Description

1.1 2020/06 •Updated ISP usage restrictions in the Section 38.8 “Usage restrictions”.

•Updated to reserve the CT32B_IR[7:6].

1.0 2020/04 Initial public release

User manual Rev. 1.1 — June 2020 3 of 350

1.1 Introduction

The K32W061 and K32W041 (called K32W061/41 throughout this document) are

ultra-low power, high performance Arm® Cortex®-M4 based wireless microcontrollers

supporting Zigbee 3.0, Thread and Bluetooth Low Energy 5.0 networking stacks to

facilitate home and building automation, smart lighting, smart locks and sensor network

applications.

The K32W061/41 includes a 2.4 GHz IEEE 802.15.4 and a Bluetooth Low Energy

compliant transceivers and a comprehensive mix of analog and digital peripherals.

Ultra-low current consumption in radio receive and radio transmit modes allows use of

coin cell batteries.

K32W061/041 has 640 KB embedded Flash, 152 KB RAM and 128 KB ROM memory.

The embedded flash can support Over The Air (OTA) code download to applications. The

devices include 10-channel PWM, two timers, one RTC/alarm timer, a Windowed

Watchdog Timer (WWDT), two USARTs, two SPI interfaces, two I2C interfaces, a DMIC

subsystem with dual-channel PDM microphone interface with voice activity detector, one

12-bit ADC, temperature sensor and comparator.

The K32W061 variant has an internal NTAG I2C plus NFC tag and connections for the

external NFC antenna. The tag is an NXP device NT3H2211.

The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low-power

consumption and enhanced debug features. The Arm Cortex-M4 CPU, operating at up to

48 MHz, incorporates a 3-stage pipeline, uses a Harvard architecture with separate local

instruction and data buses as well as a third bus for peripherals, and includes an internal

prefetch unit that supports speculative branching. The Arm Cortex-M4 supports

single-cycle digital signal processing and SIMD instructions. Debug is supported using the

Serial Wire Debug.

Refer to the data sheet for complete details on specific products and configurations.

1.2 Features

1.2.1 Microcontroller features

•Application CPU, Arm Cortex-M4 CPU:

–Arm Cortex-M4 processor, running at a frequency of up to 48 MHz.

–Arm built-in Nested Vectored Interrupt Controller (NVIC)

–Memory Protection Unit (MPU)

–Non-maskable Interrupt (NMI) with a selection of sources

–Serial Wire Debug (SWD) with 8 breakpoints and 4 watchpoints

–System tick timer

–Includes Serial Wire Output for enhanced debug capabilities.

UM11323

Chapter 1: Introductory Information

Rev. 1.1 — June 2020 User manual

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NXP Semiconductors UM11323

Chapter 1: Introductory Information

•On-Chip memory:

–640 KB flash

–152 KB SRAM

–128 KB ROM

•12 MHz to 48 MHz system clock speed for low-power

•2 x I2C-bus interface, operate as either master or slave

•10 x PWM

•2 x Low-power timers

•2 x USART, one with flow control

•2 x SPI-bus, master or slave

•1 x PDM digital audio interface with a hardware based voice activity detector to

reduce power consumption in voice applications. Support for dual-channel

microphone interface, flexible decimators, 16 entry FIFOs and optional DC blocking

•19-channel DMA engine for efficient data transfer between peripherals and SRAM, or

SRAM to SRAM. DMA can operate with fixed or incrementing addresses. Operations

can be chained together to provide complex functionality with low CPU overhead

•Up to four GPIOs can be selected as pin interrupts (PINT), triggered by rising, falling

or both input edges

•Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical

(AND/OR) combination of input states.

•32-bit Real Time clock (RTC) with 1 s resolution. A timer in the RTC can be used to

wake from Sleep, Deep-sleep and Power-down, with 1 ms resolution

•Voltage Brown Out with 8 programmable thresholds

•8-input 12-bit ADC, 190 kS/sec. HW support for continuous operation or single

conversions, single or multiple inputs can be sampled within a sequence. DMA

operation can be linked to achieve low overhead operation.

•1 x analog comparator

•Battery voltage measurement

•Temperature sensor

•Watchdog timer and POR

•Standby power controller

•Up to 22 Digital IOs (DIO)

•1 x Quad SPIFI for reading or writing to external flash device

•NTAG NFC Forum Type 2 on K32W061 only

•Random Number Generator engine

•AES engine

•Hash hardware accelerator

•EFuse :

–128-bit random AES key

–configuration modes

–Trimming

User manual Rev. 1.1 — June 2020 5 of 350

NXP Semiconductors UM11323

Chapter 1: Introductory Information

1.2.2 Radio features

•2.4 GHz IEEE 802.15.4 compliant

•2.4 GHz Bluetooth Low Energy 5.0 compliant

•Receive current 4.3 mA

•IEEE 802.15.4 receiver sensitivity -100 dBm

•Bluetooth Low Energy 5.0 2 Mbps high data rate

•Bluetooth Low Energy Receiver Sensitivity -97 dBm

•Improved co-existence with WiFi

•Flexible output power up to 11 dBm, programmable with 46 dB range

•Transmit power +10 dBm current 20.3 mA

•Transmit power +3 dBm current 9.4 mA

•Transmit power 0 dBm current 7.4 mA

•1.9 V to 3.6 V supply voltage

•32 MHz XTAL cell with internal capacitors, able with suitable external XTAL, to meet

the required accuracy for radio operation over the operating conditions

•Antenna Diversity control

•Integrated RF balun

•Integrated ultra Low-power sleep oscillator

•Deep Power-down current 350 nA (with wake-up from IO)

•128-bit or 256-bit AES security processor

•MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers

1.2.3 Low-power features

•Sleep mode supported, CPU in low-power state waiting for interrupt

•Deep-sleep mode supported, CPU in low-power state waiting for interrupt, but extra

functionality disabled or in low-power state compared to sleep mode

•Power Down mode, main functionality powered down, wakeup possible from IOs,

wakeup possible from some peripherals (I2C, USART, SPI) in a limited function mode

and low-power timers

•Deep power down, very low-power state with option of reset triggered by IOs, 350 nA

•41-bit and 28-bit Low power timers can run in power down mode, clocked by 32 kHz

FRO or 32 kHz XTAL. Timers can run for over one year or 2 days

•Bluetooth Low Energy specific low-power timers closely linked to the Bluetooth Low

Energy link layer to manage timing in low-power states.

User manual Rev. 1.1 — June 2020 6 of 350

NXP Semiconductors UM11323

Chapter 1: Introductory Information

1.3 Block diagram

1.4 Architectural overview

The Arm Cortex-M4 includes three AHB-Lite buses, one system bus and the I-code and

D-code buses. One bus is dedicated for instruction fetch (I-code), and one bus is

dedicated for data access (D-code). The use of two core buses allows for simultaneous

operations if concurrent operations target different devices.

A multi-layer AHB matrix connects the CPU buses and other bus masters to peripherals in

a flexible manner that optimizes performance by allowing peripherals on different slaves

ports of the matrix to be accessed simultaneously by different bus masters. More

information on the multilayer matrix can be found in Section 2.1.3 “AHB multilayer matrix”.

Connections in the multilayer matrix are shown in Figure 1. Note that while the AHB bus

itself supports word, halfword, and byte accesses, not all AHB peripherals need or provide

that support.

Fig 1. Chip block diagram

Master

Slave

pmu_top

Analog

Comparator

ADC

XTAL

Oscillator

Temperature

Sensor

Free Running

Oscillator

192 MHz

Free Running

Oscillator

Power

Reset

Brown Out

Detectors

DCDC

Converter

1 MHz

Free Running

Oscillator

core_digita

AHB Multi-Layer Matrix

APB Bridge 0

Arm

Cortex-M4

with MPU

Quad

SPIFI

MODEM

System

APB Bridge 1

FLASH

640K

(1 * 640K)

FLASH

Functional

Muxes I/Os

Func

MUX

Func

MUX

Func

MUX

Func

MUX

Func

MUX

Func

MUX

...

AES

256

ADC

Controller

Debug

Access

Port

DMA

Controller

(19channels)

DMIC

USART 0 SPI 0

GPIO

(22I/Os)

Power

Management

Controller

(PMC)

Watchdog

Timer

Interrupt

Pattern

Matching

USART 1 SPI 1

I2C 1

ISO7816

PWM

(10 channels)

Peripheral

Input Mux Infra Red

Random

Number

Generator

Async

System

Config.

CTimers

0 / 1

GPIO

Global

Interrupt

Sync.

System

Config.

RTC I/O

Config.

Wake-up

Timers 0/1

Sleep

Config.

Reset

Controller

Clock

Controller

Analog

Interrupt

Controller

Zigbee/

Thread

MAC

MoDem

AHB

Master

RFP

MODEM

Zigbee/

Thread

MODEM Flash

Controller

SRAM

88 K

(2*4K + 2*8K

+ 4*16K)

SRAM 0

SRAM

Controller

SRAM

64 K

(4 * 16K)

SRAM 1

SRAM

Controller

ROM

128 K

(1*128K)

ROM

Code

Patch

radio_to

32 MHz

XTAL

Oscillator

Radio

LDOs

Band Gap

(Bias)

Hash

(SHA-1,

SHA-2 256)

I2C 0

LINK

LAYER MODEM

Analog Mixed SignalDigital Units System Control Bus

(AMBA AHB/APB)

ROM, RAM, FLASH

I2C 2

eFUSE

(64 * 16)

OTP

Controller

Interface

Key:

(NTAG control)

Bluetooth LE Bluetooth LE

32 kHz 32 kHz

User manual Rev. 1.1 — June 2020 7 of 350

NXP Semiconductors UM11323

Chapter 1: Introductory Information

APB peripherals are connected to the AHB matrix via two APB buses using separate

slave ports from the multilayer AHB matrix. This allows for better performance by reducing

collisions between the CPU and the DMA controller, and also for peripherals on the

asynchronous bridge to have a fixed clock that does not track the system clock. Note that

APB, by definition, does not directly support byte or halfword accesses.

The multi-layer has several master interfaces and slave interfaces. The following table

shows which slaves the master interfaces are able to access; indicated with a 'x'. Where a

block has '-REG' in the name, this shows that it is the register interface of the block.

SPIFI-MEM is the direct memory access function of the block and not the register

interface.

1.5 Arm Cortex-M4 processor

The Cortex-M4 is a general purpose 32-bit microprocessor, which offers high performance

and very low-power consumption. The Cortex-M4 offers a Thumb-2 instruction set, low

interrupt latency, interruptible/continuable multiple load and store instructions, automatic

state save and restore for interrupts, tightly integrated interrupt controller, and multiple

core buses capable of simultaneous accesses.

Table 1. AHB master interface accessibility to the slaves

AHB slave AHB master

CPU DMA HASH MODEM

I-code D-code System

Slave port 0 Flash x x x x

Slave port 1 ROM x x x

Slave port 2 SRAM0 x x x x x

Slave port 3 SRAM1 x x x x x

Slave port 4 SPIFI-MEM x x

Slave port 5 APB bridge 0 x x

Slave port 6 APB bridge 1 x

Slave port 7 SPIFI-REG x x

GPIO x x

DMA-REG x x

AES x x

ADC x x

DMIC x x

USART0 x x

USART1 x x

SPI0 x x

SPI1 x x

HASH x x

Slave port 8 Bluetooth Low Energy

Link Layer

Zigbee/Thread MODEM x x

Zigbee/Thread MAC x x

User manual Rev. 1.1 — June 2020 8 of 350

NXP Semiconductors UM11323

Chapter 1: Introductory Information

A 3-stage pipeline is employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

Information about Cortex-M4 configuration options can be found in Chapter 43 “Arm

Cortex-M4 Appendix”.

User manual Rev. 1.1 — June 2020 9 of 350

2.1 General description

The K32W061/41 incorporates several distinct memory regions. Figure 1 shows the

overall map of the entire address space from the user program viewpoint following reset.

The APB peripheral area (detailed in Figure 1) is divided into fixed 4 KB slots to simplify

addressing.

The registers incorporated into the CPU, such as NVIC, SysTick, and sleep mode control,

are located on the private peripheral bus.

2.1.1 Main SRAM

The main SRAM is composed of 152 KB of on-chip static RAM memory. The SRAM is

accessed through two controllers SRAM-CTRL0 and SRAM-CTRL1. SRAM-CTRL0 gives

access to the first 88 KB and SRAM-CTRL1 gives access to the remaining 64 KB. The

memory is contiguous within the two separate regions but not contiguous from

SRAM-CTRL0 to SRAM-CTRL1. Each SRAM has a separate clock control and power

switch.

2.1.1.1 SRAM usage notes

The SRAM controllers, SRAM-CTRL0 and SRAM-CTRL1, are placed on different AHB

matrix ports. This allows user programs to potentially obtain better performance by

dividing RAM usage among the ports. For example, simultaneous access to SRAM0 by

the CPU and SRAM1 by the system DMA controller does not result in any bus stalls for

either master.

Generally, data being communicated via peripherals will be accessed by the CPU at some

point, even when peripheral data is mainly being transferred via DMA. So, in order to

minimizing data read/write stalls, data buffers may be placed in RAMs on different AHB

matrix ports. For instance, if DMA is writing to one buffer on a specific AHB matrix port

while the CPU is reading data from a buffer on a different AHB matrix port, there is no stall

for either the CPU or the DMA. Sequences of data from the same peripheral could be

alternated between RAM on each port. This could be helpful if DMA fills or empties a RAM

buffer, then signals the CPU before proceeding on to a second buffer. The CPU would

then tend to access the data while the DMA is using the other RAM.

2.1.2 Memory mapping

The overall memory map and also details of the APB peripheral mapping are shown in

Figure 1 “Main memory map”.

UM11323

Chapter 2: Memory Map

Rev. 1.1 — June 2020 User manual

Table 2. SRAM configuration

SRAM Controller SRAM-CTRL0 SRAM-CTRL1

(total main SRAM = up to 152 KB)

Size 88 KB Up to 64 KB

Address range 0x0400 0000 to 0x0401 5FFF 0x0402 0000 to 0x0402 FFFF

User manual Rev. 1.1 — June 2020 10 of 350

NXP Semiconductors UM11323

Chapter 2: Memory Map

1) The private peripheral bus includes CPU peripherals such as the NVIC, SysTick, and the core control registers.

2) Memory region 0x00000000 to 0x000001FF can be mapped to flash, as shown here, or ROM or RAM depending upon the

Vector Table Remapping setting.

Fig 2. Main memory map

FLASH Memory

Reserved

(Do not access)

0x0000_0000

0x0301_FFFF

0x4000_0000

640 KBytes

APB Bridge 0

(Synchronous)

0xFFFF_FFFF

General Purpose I/O

Synchronous System

Configuration

ROM

0x0009_FFFF

0x0300_0000

Main Memory Map (AHB) APB Bridge 0 Memory Map

32-bit Words

Reserved

(Do not access)

SRAM-CTRL0

(2*4KB, 2*8KB, 4*16KB)

0x0400_0000

0x0401_5FFF

Reserved

Quad SPIFI

(Memory-Mapped Space)

0x1000_0000

0x103F_FFFF

Reserved

(Do not access)

0x4001_FFFF

0x4008_0000

0x4008_3FFF

SPIFI Registers

DMA Controller

AES-256

Reserved

(Do not access)

Private Peripheral

Bus (Internal)

Private Peripheral

Bus (External)

Reserved

(Do not access)

0x4008_4FFF

0x4008_5FFF

0x4008_6FFF

0x4008_4000

0x4008_5000

0x4008_6000

0xE003_FFFF

0xE00F_FFFF

0xE004_0000

0xE000_0000

128 KBytes

88 KBytes

4 MBytes

4 KBytes

768 KBytes

16 KBytes

4 KBytes

128 KBytes

4 KBytes

0x4000_0000

Reserved (do not

access) 4 KBytes

0x4000_1000

Reserved (do not

access) 4 KBytes

0x4000_2000

I2C 0 4 KBytes

0x4000_3000

I2C 1 4 KBytes

0x4000_4000

I2C 2 4 KBytes

0x4000_5000

ISO7816 4 KBytes

0x4000_6000

IR Modulator 4 KBytes

0x4000_7000

Code Patch

Module 4 KBytes

0x4000_8000

Flash Controller 4 KBytes

0x4000_9000

WWDT 4 KBytes

0x4000_A000

RTC 4 KBytes

0x4000_B000

PWM 4 KBytes

0x4000_C000

4 KBytes

0x4000_D000

Random Number

Generator

4 KBytes

0x4000_E000 INPUT MUX

4 KBytes

0x4000_F000

IO CONFIG

(IOCON)

4 KBytes

0x4001_0000

GPIO Pattern

Interrupt (PINT)

4 KBytes

0x4001_1000

CTIMER 0

4 KBytes

0x4001_2000

RFP MODEM 4 KBytes

0x4001_3000

4 KBytes

0x4001_4000

Reserved

(Do not access)

0x4001_5000

40 KBytes

GPIO Group

Interrupt (GINT0)

APB Bridge 1

(Asynchronous)

0x4002_0000

0x4003_FFFF

CTIMER 1

APB Bridge 1 Memory Map

4 KBytes

0x4002_0000

Reserved

(Do not access) 116 KBytes

0x4002_1000

SRAM 0 (16 KB)

SRAMs Memory Map

0x0400_0000

SRAM 1 (16 KB)

0x0400_4000

SRAM 2 (16 KB)

0x0400_8000

SRAM 5 (8 KB)

0x0400_C000

0x0401_4000

128 KBytes

0x4003_FFFF

0x4002_0FFF

0x4001_FFFF

32-bit Words

PMC

4 Kbytes

Asynchronous

System Configuration

0x4002_1FFF

0x4002_2000

0x4002_2FFF

0x4002_3000

4 KBytes

SRAM 6 (4 KB)

SRAM 7 (4 KB)

SRAM 8 (16 KB)

SRAM 9 (16 KB)

0x0401_5000

0x0402_0000

0x0402_4000

0x0401_5FFF

0x0402_3FFF

0x0401_4FFF

0x0401_3FFF

0x0400_BFFF

0x0400_7FFF

0x0400_3FFF

0x0402_7FFF

IEEE 802.15.4 MODEM

IEEE 802.15.4 MAC

0x400A_0000

0x400B_0000

0x400B_1000

0x400A_FFFF

0x400B_0FFF

0x400B_1FFF

4 Kbytes

64 Kbytes

Reserved

(Do not access)

Reserved

(Do not access)

4 Kbytes

0x4008_8FFF

0x4008_7FFF

0x4008_7000

0x4008_8000

Reserved

(Do not access)

0x4008_9000

ADC 4 Kbytes

0x4008_9FFF

DMIC 4 Kbytes

0x4008_A000

0x4008_AFFF

USART 0

USART 1

4 Kbytes

0x4008_CFFF

0x4008_BFFF

0x4008_B000

0x4008_C000

0x4008_D000

SPI 0 4 Kbytes

0x4008_DFFF

SPI 1 4 Kbytes

0x4008_E000

0x4008_EFFF

SRAM 3 (16 KB)

SRAM 4 (8 KB)

0x0400_FFFF

0x0401_0000

0x0401_2000

0x0401_1FFF

SRAM-CTRL1

(4*16KB)

64 KBytes

0x0402_0000

0x0402_FFFF

Reserved SRAM 10 (16 KB)

SRAM 11 (16 KB)

0x0402_8000

0x0402_FFFF

0x0402_C000

0x0402_BFFF

Reserved

(Do not access) 4 KBytes

0x4001_6000

Hash 4 Kbytes

0x4008_F000

0x4008_FFFF

Bluetooth LE

LINK LAYER

Bluetooth LE

MODEM

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