Cypress Semiconductor CY7C1471BV33 Manuel utilisateur

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through

SRAM with NoBL™ Architecture

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-15029 Rev. *B Revised March 05, 2008

Features

■No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

■Supports up to 133 MHz bus operations with zero wait states

■Data is transferred on every clock

■Pin compatible and functionally equivalent to ZBT™ devices

■Internally self timed output buffer control to eliminate the need

to use OE

■Registered inputs for flow through operation

■Byte Write capability

■3.3V/2.5V IO supply (VDDQ)

■Fast clock-to-output times

❐6.5 ns (for 133 MHz device)

■ClockEnable(CEN)pintoenable clockandsuspendoperation

■Synchronous self-timed writes

■Asynchronous Output Enable (OE)

■CY7C1471BV33, CY7C1473BV33 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and

non-Pb-free 165-Ball FBGA package. CY7C1475BV33

available in Pb-free and non-Pb-free 209-Ball FBGA package

■Three Chip Enables (CE1, CE2, CE3) for simple depth

expansion

■Automatic power down feature available using ZZ mode or CE

deselect

■IEEE 1149.1 JTAG Boundary Scan compatible

■Burst Capability—linear or interleaved burst order

■Low standby power

Functional Description

The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33

are 3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through

burst SRAMs designed specifically to support unlimited true

back-to-back read or write operations without the insertion of

wait states. The CY7C1471BV33, CY7C1473BV33, and

CY7C1475BV33 are equipped with the advanced No Bus

Latency (NoBL) logic. NoBL™ is required to enable consecutive

read or write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput of

data through the SRAM, especially in systems that require

frequent write-read transitions.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock input is qualified by the

Clock Enable (CEN) signal, which when deasserted suspends

operation and extends the previous clock cycle. Maximum

access delay from the clock rise is 6.5 ns (133 MHz device).

Write operations are controlled by two or four Byte Write Select

(BWX) and a Write Enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence. For best practice recommendations,

refer to the Cypress application note AN1064 “SRAM System

Guidelines”.

Selection Guide

Description 133 MHz 117 MHz Unit

Maximum Access Time 6.5 8.5 ns

Maximum Operating Current 305 275 mA

Maximum CMOS Standby Current 120 120 mA

[+] Feedback

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B Page 2 of 32

Logic Block Diagram – CY7C1471BV33 (2M x 36)

Logic Block Diagram – CY7C1473BV33 (4M x 18)

MODE

CE1

CE2

CE3

OE READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

CE ADV/LD

CLK

CEN

WRITE

DRIVERS

WRITE ADDRESS

A0, A1, A

ZZ SLEEP

CONTROL

MODE

BW A

BW B

CE1

CE2

CE3

OE READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

CE ADV/LD

CLK

WRITE

DRIVERS

WRITE ADDRESS

A0, A1, A

ZZ SLEEP

CONTROL

[+] Feedback

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B Page 3 of 32

Logic Block Diagram – CY7C1475BV33 (1M x 72)

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQ s

DQ Pa

DQ Pb

DQ Pc

DQ Pd

DQ Pe

DQ Pf

DQ Pg

DQ Ph

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

BURST

LOGIC

A0'

A1'

ADV/LD

INPUT

CLK

CEN

WRITE

DRIVERS

Sleep Control

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

[+] Feedback

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B Page 4 of 32

Pin Configuration

NC/288M

NC/144M

VSS

VDD

DQPB

DQB

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

DQA

DQPA

DQPC

DQC

VDDQ

VSS

DQC

VSS

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSS

DQD

VSS

VDDQ

DQD

DQPD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

CEN

100

ADV/LD

MODE

CY7C1471BV33

BYTE A

BYTE B

BYTE D

BYTE C

Figure 1. 100-Pin TQFP Pinout

[+] Feedback

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B Page 5 of 32

Pin Configuration (continued)

NC/288M

NC/144M

VSS

VDD

VDDQ

VSS

DQPA

DQA

VSS

VDDQ

DQA

VSS

VDD

DQA

VDDQ

VSS

DQA

VSS

VDDQ

VSS

DQB

VSS

VDDQ

DQB

VDD

VSS

DQB

VDDQ

VSS

DQB

DQPB

VSS

VDDQ

CE1

CE2

BWB

BWA

CE3

VDD

VSS

CLK

CEN

100

ADV/LD

MODE

CY7C1473BV33 BYTE A

BYTE B

Figure 2. 100-Pin TQFP Pinout

[+] Feedback

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B Page 6 of 32

Pin Configuration (continued)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1471BV33 (2M x 36)

CY7C1473BV33 (4M x 18)

2345671

TDO

NC/576M

NC/1G

DQP

CEN

ACE2

MODE

DDQ

CLK WE

DDQ

TCK

TDI

NC V

NC/144M NC

DDQ

TMS

891011

NC/288M

ADV/LD

ANC

DDQ

NC DQP

DDQ

DQP

DDQ

2345671

TDO

NC/576M

NC/1G

DQP

CEN

ACE2

MODE

DDQ

NC BW

CLK WE

DDQ

TCK

TDI

NC V

NC NC V

NC/144M NC

DDQ

TMS

891011

NC/288M

ADV/LD

ANC

DDQ

NC DQP

DDQ

NC DQ

DDQ

NCV

DDQ

NC ZZ

DDQ

[+] Feedback

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B Page 7 of 32

Pin Configuration (continued)

CY7C1475BV33 (1M × 72)

123456789 1110

DQg

DQc

DQPg

DQh

DQd

DQPd

DQPc

DQc

DQh

DQPh

DQd

DQb

DQf

DQPf

DQa

DQe

DQPa

DQPb

DQf

DQa

DQPe

DQe

AA AA

NC NC

NC/144M AA NC/288M

AAA

AAAA1

AAA

NC/576M

NC NC

BWSbBWSf

BWSeBWSa

BWScBWSg

BWSd

BWSh

TMS TDI TDO TCK

NC MODE NC

CEN VSS

CLK NC VSS

VDD VDD VDD

VDD

VSS VSS

VSS

VSS VSS

VSS

NC/1G

VDD

CE3

CE1

CE2ADV/LD

VSS

VSS VSS VSS VSS

VDDQ

VSS

VSS NC VSS VSS

VSS VSS VSS VSS

VSS

VDDQ VDDQ VDDQ VDDQ

VDDQ NC VDDQ VDDQ

VDDQ VDDQ NC VDDQ VDDQ

VDDQ

VDDQ VDDQ

VDDQ VDDQ VDDQ VDDQ

209-Ball FBGA (14 x 22 x 1.76 mm) Pinout

[+] Feedback

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B Page 8 of 32

Pin Definitions

Name IO Description

A0, A1, A Input-

Synchronous Address Inputs used to select one of the Address Locations. Sampled at the rising edge

of the CLK. A[1:0] is fed to the two-bit burst counter.

BWA, BWB,

BWC, BWD,

BWE, BWF,

BWG, BWH

Input-

Synchronous Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled

on the rising edge of CLK.

WE Input-

Synchronous Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.

This signal must be asserted LOW to initiate a write sequence.

ADV/LD Input-

Synchronous Advance/Load Input. Advances the on-chip address counter or loads a new address. When

HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new

address can be loaded into the device for an access. After deselection, drive ADV/LD LOW to

load a new address.

CLK Input-

Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

CE1Input-

Synchronous Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2and CE3to select or deselect the device.

CE2Input-

Synchronous Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE1 and CE3to select or deselect the device.

CE3Input-

Synchronous Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE1and CE2 to select or deselect the device.

OE Input-

Asynchronous Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic

blockinsidethedevicetocontrolthedirectionoftheIOpins.WhenLOW,theIOpinsareenabled

to behave as outputs.When deasserted HIGH, IO pinsaretri-stated, andact as inputdata pins.

OE is masked during the data portion of a write sequence, during the first clock when emerging

from a deselected state, and when the device is deselected.

CEN Input-

Synchronous Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the

SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does

not deselect the device, CEN can be used to extend the previous cycle when required.

ZZ Input-

Asynchronous ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”

condition with data integrity preserved. During normal operation, this pin must be LOW or left

floating. ZZ pin has an internal pull down.

DQsIO-

Synchronous Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the addresses presented during the previous clock rise of the read cycle. The

directionofthepinsiscontrolledbyOE.WhenOEisassertedLOW, thepinsbehaveasoutputs.

When HIGH, DQsand DQPXare placed in a tri-state condition.The outputs are automatically

tri-stated during the data portion of a write sequence, during the first clock when emerging from

a deselected state, and when the device is deselected, regardless of the state of OE.

DQPXIO-

Synchronous Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs.During

write sequences, DQPXis controlled by BWXcorrespondingly.

MODE Input Strap Pin Mode Input. Selects the Burst Order of the Device. When tied to Gnd selects linear burst

sequence. When tied to VDD or left floating selects interleaved burst sequence.

VDD Power Supply Power Supply Inputs to the Core of the Device.

VDDQ IO Power Supply Power Supply for the IO Circuitry.

VSS Ground Ground for the Device.

[+] Feedback

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B Page 9 of 32

Functional Overview

The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33

are synchronous flow through burst SRAMs designed

specifically to eliminate wait states during write-read transitions.

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. The clock signal is qualified with the

ClockEnable inputsignal (CEN).IfCEN isHIGH,theclock signal

is not recognized and all internal states are maintained. All

synchronous operations are qualified with CEN. Maximum

access delay from the clock rise (tCDV) is 6.5 ns (133 MHz

device).

Accesses may be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the clock. If (CEN)

is active LOW and ADV/LD is asserted LOW, the address

presented to the device is latched. The access can either be a

read or write operation, depending on the status of the Write

Enable (WE). Byte Write Select (BWX) can be used to conduct

Byte Write operations.

Write operations are qualified by the Write Enable (WE). All

writes are simplified with on-chip synchronous self timed write

circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) simplify depth expansion. All

operations (reads, writes, and deselects) are pipelined. ADV/LD

must be driven LOW after the device is deselected to load a new

address for the next operation.

Single Read Accesses

A read access is initiated when these conditions are satisfied at

clock rise:

■CEN is asserted LOW

■CE1, CE2, and CE3 are ALL asserted active

■WE is deasserted HIGH

■ADV/LD is asserted LOW

The address presented to the address inputs is latched into the

AddressRegisterand presentedto thememory arrayandcontrol

logic. The control logic determines that a read access is in

progress and allows the requested data to propagate to the

output buffers. The data is available within 6.5 ns (133 MHz

device) provided OE is active LOW. After the first clock of the

read access, the output buffers are controlled by OE and the

internal control logic. OE must be driven LOW to drive out the

requested data. On the subsequent clock, another operation

(read/write/deselect) can be initiated. When the SRAM is

deselected at clock rise by one of the chip enable signals, output

is tri-stated immediately.

Burst Read Accesses

The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33

have an on-chip burst counter that enables the user to supply a

single address and conduct up to four reads without reasserting

the address inputs. ADV/LD must be driven LOW to load a new

address into the SRAM, as described in the Single Read Access

section. The sequence of the burst counter is determined by the

MODE input signal. A LOW input on MODE selects a linear burst

mode, a HIGH selects an interleaved burst sequence. Both burst

counters use A0 and A1 in the burst sequence, and wrap around

when incremented sufficiently. A HIGH input on ADV/LD

increments the internal burst counter regardless of the state of

chip enable inputs or WE. WE is latched at the beginning of a

burst cycle. Therefore, the type of access (read or write) is

maintained throughout the burst sequence.

TDO JTAG serial

output

Synchronous

Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG

feature is not used, this pin must be left unconnected. This pin is not available on TQFP

packages.

TDI JTAG serial input

Synchronous Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is

not used, this pin can be left floating or connected to VDD through a pull up resistor. This pin is

not available on TQFP packages.

TMS JTAG serial input

Synchronous Serial Data-In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is

not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP

packages.

TCK JTAG

-Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected

to VSS. This pin is not available on TQFP packages.

NC - No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address

expansion pins and are not internally connected to the die.

Pin Definitions (continued)

Name IO Description

[+] Feedback

CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B Page 10 of 32

Single Write Accesses

Write accesses are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are all asserted active, and (3) WE is asserted LOW.

The address presented to the address bus is loaded into the

Address Register. The Write signals are latched into the Control

Logic block. The data lines are automatically tri-stated

regardless of the state of the OE input signal. This allows the

external logic to present the data on DQs and DQPX.

On the next clock rise the data presented to DQs and DQPX (or

a subset for Byte Write operations, see section Truth Table for

Read/Write on page 12 for details), input is latched into the

device and the write is complete. Additional accesses

(read/write/deselect) can be initiated on this cycle.

The data written during the write operation is controlled by BWX

signals. The CY7C1471BV33, CY7C1473BV33, and

CY7C1475BV33 provide Byte Write capability that is described

in the section Truth Table for Read/Write on page 12. The input

WE with the selected BWXinput selectively writes to only the

desired bytes. Bytes not selected during a Byte Write operation

remain unaltered. A synchronous self timed write mechanism is

provided to simplify the write operations. Byte write capability is

included to greatly simplify read/modify/write sequences, which

can be reduced to simple byte write operations.

Because the CY7C1471BV33, CY7C1473BV33, and

CY7C1475BV33 are common IO devices, do not drive data into

the device when the outputs are active. The Output Enable (OE)

can be deasserted HIGH before presenting data to the DQs and

DQPXinputs. Doing so tri-states the output drivers. As a safety

precaution, DQs and DQPXare automatically tri-stated during

the data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33

have an on-chip burst counter that enables the user to supply a

single address and conduct up to four write operations without

reasserting the address inputs. ADV/LD must be driven LOW to

load the initial address, as described in section Single Write

Accesses on page 10. When ADV/LD is driven HIGH on the

subsequent clock rise, the Chip Enables (CE1, CE2, and CE3)

and WE inputs are ignored and the burst counter is incremented.

Drive the correct BWXinputs in each cycle of the burst write to

write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when enteringthe “sleep”mode arenotconsideredvalid

and the completion of the operation is not guaranteed. The

device must be deselected before entering the “sleep” mode.

CE1, CE2, and CE3, must remain inactive for the duration of

tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 120 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[+] Feedback

Ce manuel convient aux modèles suivants

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