Cypress Semiconductor CY7C0430CV Manuel utilisateur

10 Gb/s 3.3V QuadPort™ DSE Family

CY7C0430BV

CY7C0430CV

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-06027 Rev. *B Revised May 23, 2006

Features

• QuadPort™ datapath switching element (DSE) family

allows four independent ports of access for data path

management and switching

• High-bandwidth data throughput up to 10 Gb/s

• 133-MHz[1] port speed x 18-bit-wide interface × 4 ports

• High-speed clock to data access 4.2 ns (max.)

• Synchronous pipelined device

— 1-Mb (64K × 18) switch array

• 0.25-micron CMOS for optimum speed/power

• IEEE 1149.1 JTAG boundary scan

• Width and depth expansion capabilities

• BIST (Built-In Self-Test) controller

• Dual Chip Enables on all ports for easy depth expansion

• Separate upper-byte and lower-byte controls on all

ports

• Simple array partitioning

— Internal mask register controls counter wrap-around

— Counter-Interrupt flags to indicate wrap-around

— Counter and mask registers readback on address

• 272-ball BGA package (27-mm × 27-mm × 1.27-mm ball

pitch)

• Commercial and industrial temperature ranges

• 3.3V low operating power

— Active = 750 mA (maximum)

— Standby = 15 mA (maximum

Note:

1. fMAX2 for commercial is 135 MHz and for industrial is 133 MHz.

BUFFERED SWITCH

REDUNDANT DATA MIRROR

PORT 1 PORT 3

PORT 4

PORT 2

PORT 1

PORT 2

PORT 3

PORT 4

QuadPort DSE Family Applications

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CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 2 of 37

Functional Description

The Quadport Datapath Switching Element (DSE) family offers

four ports that may be clocked at independent frequencies

from one another. Each port can read or write up to 133 MHz[1],

giving the device up to 10 Gb/s of data throughput. The device

is 1-Mb (64K × 18) in density. Simultaneous reads are allowed

for accesses to the same address location; however, simulta-

neous reading and writing to the same address is not allowed.

Any port can write to a certain location while other ports are

reading that location simultaneously, if the timing spec for port

to port delay (tCCS) is met. The result of writing to the same

location by more than one port at the same time is undefined.

Data is registered for decreased cycle time. Clock to data valid

tCD2 = 4.2 ns. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address the counter will self-increment the address inter-

nally (more details to follow). The internal write pulse width is

independent of the duration of the R/W input signal. The

internal write pulse is self-timed to allow the shortest possible

cycle times.

A HIGH on CE0or LOW on CE1for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle is required with chip enables asserted

to reactivate the outputs.

The CY7C0430BV and CY7C0430CV (64K × 18 device)

supports burst contains for simple array partitioning. Counter

enable inputs are provided to stall the operation of the address

input and utilize the internal address generated by the internal

counter for fast interleaved memory applications. A port’s burst

DATA PATH AGGREGATOR

PORT 1

PORT 2

PORT 3

PORT 4

DATA PATH MANAGER FOR

PARALLEL PACKET PROCESSING

Processor 2

Processor 1

Pre-processed DATA Path Processed DATA Path

DATA CLASSIFICATION ENGINE

PORT 2 PORT 4

PORT 1 PORT 3

Queue #1

Queue #2

QuadPort

DSE Family

[+] Feedback

CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 3 of 37

counter is loaded with an external address when the port’s

Counter Load pin (CNTLD) is asserted LOW. When the port’s

Counter Increment pin (CNTINC) is asserted, the address

counter will increment on each subsequent LOW-to- HIGH

transition of that port’s clock signal. This will read/write one

word from/into each successive address location until

CNTINC is deasserted. The counter can address the entire

switch array and will loop back to the start. Counter Reset

(CNTRST) is used to reset the burst counter. A counter-mask

mask register operations are described in more details in the

following sections.

The counter or mask register values can be read back on the

bidirectional address lines by activating MKRD or CNTRD,

respectively.

The new features included for the QuadPort DSE family

include: readback of burst-counter internal address value on

address lines, counter-mask registers to control the counter

wrap-around, readback of mask register value on address

lines, interrupt flags for message passing, BIST, JTAG for

boundary scan, and asynchronous Master Reset.

Notes:

2. Port 1 Control Logic Block is detailed on page 4.

3. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.

Port-1

Control

Logic

Port 1

Counter/

Mask Reg/

Address

Decode

Port 1

I/O

Top Level Logic Block Diagram

64K × 18

QuadPort DSE

Array

Port 1 Operation-control Logic Blocks[2]

Port 2 Logic Blocks[3]

Port 4 Logic Blocks[3]

Port 3 Logic Blocks[3]

CNTLDP1

CNTINCP1

CNTRSTP1

MKLDP1

CNTINTP1

MKRDP1

CNTRDP1

INTP1

CE1P1

CE0P1

R/WP1

OEP1

UBP1

LBP1

I/O0P1- I/O17P1

A0P1–A15P1

TMS

TCK

TDI TDO

BIST

MRST Reset

Logic

JTAG

Controller

CLKP1

CLKBIST

Port 1

Port 2 Port 3

Port 4

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CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 4 of 37

Addr.

Read

Port 1 Operation-Control Logic Block Diagram

R/WP1

CE0P1

CE1P1

LBP1

OEP1

UBP1

I/O9P1–I/O17P1

I/O0P1–I/O8P1

I/O

Control

Counter/

A0P1–A15P1

CLKP1

CNTLDP1

CNTINCP1

CNTRSTP1

MKLDP1

CNTINTP1

MKRDP1

Mask Register

Port-1

Port 1

64K × 18

QuadPort

DSE Array

Port 1

Port 2

Port 4

Port 3

Address

Readback

Port 1

CNTRDP1

Port 1

Address

Decode

Port 1

Interrupt

Logic

R/WP1

CE0P1

CE1P1

OEP1

INTP1

CLKP1

MRST

Priority

Decision

Logic

MRST

(Address Readback is independent of CEs)

LBP1

UBP1

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CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 5 of 37

Pin Configuration

272-ball Grid Array (BGA)

Top View

Note:

4. Central Leads are for thermal dissipation only. They are connected to device VSS.

1234567891011121314151617181920

ALB

I/O17

I/O15

I/O13

I/O11

I/O9

I/O16

I/O14

I/O12

I/O10

I/O12

I/O14

I/O16

I/O9

I/O11

I/O13

I/O15

I/O17

BVDD1 UB

I/O16

I/O14

I/O12

I/O10

I/O17

I/O13

I/O11

TMS TDI I/O11

I/O13

I/O17

I/O10

I/O12

I/O14

I/O16

VDD1

CA14

A15

CE1

CE0

R/W

I/O15

VSS2 VSS2 I/O9

TCK TDO I/O9

VSS2 VSS2 I/O15

R/W

CE0

CE1

A15

A14

DVSS1 A12

A13

VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE

A13

A12

VSS1

EA10

A11

MKRD

CNTRD

MKRD

A11

A10

FA7

CNTINT

GVSS1 A5

CNTINC

VSS1

HA3

MKLD

CNTLD

MKLD

JVDD1 A1

VDD GND[4] GND[4] GND[4] GND[4] VDD A2

VDD1

KA0

INT

CNTRST

CLK

GND[4] GND[4] GND[4] GND[4] CLK

CNTRST

INT

LA0

INT

CNTRST

VSS GND[4] GND[4] GND[4] GND[4] VSS CNTRST

INT

MVDD1 A1

CLK

GND[4] GND[4] GND[4] GND[4] CLK

VDD1

NA3

MKLD

CNTLD

MKLD

PVSS1 A5

CNTINC

VSS1

RA7

CNTINT

TA10

A11

MKRD

CNTRD

MKRD

A11

A10

UVSS1 A12

A13

VDD2 VSS2 VSS2 VDD2 VDD VSS VSS VDD VDD2 VSS2 VSS2 VDD2 OE

A13

A12

VSS1

VA14

A15

CE1

CE0

R/W

I/O6

VSS2 VSS2 I/O0

NC NC I/O0

VSS2 VSS2 I/O6

R/W

CE0

CE1

A15

A14

WVDD1 UB

I/O7

I/O5

I/O3

I/O1

I/O8

I/O4

I/O2

MRST CLKBIST I/O2

I/O4

I/O8

I/O1

I/O3

I/O5

I/O7

VDD1

YLB

I/O8

I/O6

I/O4

I/O2

I/O0

1/O7

I/O5

I/O3

I/O1

I/O3

I/O5

I/O7

I/O0

I/O2

I/O4

I/O6

I/O8

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CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 6 of 37

Selection Guide

CY7C0430CV

–133

CY7C0430CV

–100 Unit

fMAX2 133[1] 100 MHz

Max Access Time (Clock to Data) 4.2 5.0 ns

Max Operating Current ICC 750 600 mA

Max Standby Current for ISB1 (All ports TTL Level) 200 150 mA

Max Standby Current for ISB3 (All ports CMOS Level) 15 15 mA

Pin Definitions

Port 1 Port 2 Port 3 Port 4 Description

A0P1–A15P1 A0P2–A15P2 A0P3–A15P3 A0P4–A15P4 Address Input/Output.

I/O0P1–I/O17P1 I/O0P2–I/O17P2 I/O0P3–I/O17P3 I/O0P4–I/O17P4 Data Bus Input/Output.

CLKP1 CLKP2 CLKP3 CLKP4 Clock Input. This input can be free running or strobed.

Maximum clock input rate is fMAX.

LBP1 LBP2 LBP3 LBP4 Lower Byte Select Input. Asserting this signal LOW

enables read and write operations to the lower byte. For

read operations both the LB and OE signals must be

asserted to drive output data on the lower byte of the data

pins.

UBP1 UBP2 UBP3 UBP4 Upper Byte Select Input. Same function as LB, but to the

upper byte.

CE0P1,CE1P1 CE0P2,CE1P2 CE0P3,CE1P3 CE0P4,CE1P4 Chip Enable Input. To select any port, both CE0AND

CE1must be asserted to their active states (CE0≤VIL and

CE1≥ VIH).

OEP1 OEP2 OEP3 OEP4 Output Enable Input. This signal must be asserted LOW

to enable the I/O data lines during read operations. OE is

asynchronous input.

R/WP1 R/WP2 R/WP3 R/WP4 Read/Write Enable Input. This signal is asserted LOW

to write to the dual port memory array. For read opera-

tions, assert this pin HIGH.

MRST Master Reset Input. This is one signal for All Ports.

MRST is an asynchronous input. Asserting MRST LOW

performs all of the reset functions as described in the text.

A MRST operation is required at power-up.

CNTRSTP1 CNTRSTP2 CNTRSTP3 CNTRSTP4 Counter Reset Input. Asserting this signal LOW resets

the burst address counter of its respective port to zero.

CNTRST is second to MRST in priority with respect to

counter and mask register operations.

MKLDP1 MKLDP2 MKLDP3 MKLDP4 Mask Register Load Input. Asserting this signal LOW

loads the mask register with the external address

available on the address lines. MKLD operation has

higher priority over CNTLD operation.

CNTLDP1 CNTLDP2 CNTLDP3 CNTLDP4 Counter Load Input. Asserting this signal LOW loads the

burst counter with the external address present on the

address pins.

CNTINCP1 CNTINCP2 CNTINCP3 CNTINCP4 Counter Increment Input. Asserting this signal LOW

increments the burst address counter of its respective port

on each rising edge of CLK.

[+] Feedback

CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 7 of 37

CNTRDP1 CNTRDP2 CNTRDP3 CNTRDP4 Counter Readback Input. When asserted LOW, the

internal address value of the counter will be read back on

the address lines. During CNTRD operation, both CNTLD

and CNTINC must be HIGH. Counter readback operation

has higher priority over mask register readback operation.

Counter readback operation is independent of port chip

enables. If address readback operation occurs with chip

enables active (CE0= LOW, CE1= HIGH), the data lines

(I/Os) will be three-stated. The readback timing will be

valid after one no-operation cycle plus tCD2 from the rising

edge of the next cycle.

MKRDP1 MKRDP2 MKRDP3 MKRDP4 Mask Register Readback Input. When asserted LOW,

the value of the mask register will be readback on address

lines. During mask register readback operation, all

counter and MKLD inputs must be HIGH (see Counter

and Mask Register Operations truth table). Mask register

readback operation is independent of port chip enables.

If address readback operation occurs with chip enables

active (CE0= LOW, CE1= HIGH), the data lines (I/Os) will

be three-stated. The readback will be valid after one

no-operation cycle plus tCD2 from the rising edge of the

next cycle.

CNTINTP1 CNTINTP2 CNTINTP3 CNTINTP4 Counter Interrupt Flag Output. Flag is asserted LOW

for one clock cycle when the counter wraps around to

location zero.

INTP1 INTP2 INTP3 INTP4 Interrupt Flag Output. Interrupt permits communications

between all four ports. The upper four memory locations

can be used for message passing. Example of operation:

INTP4 is asserted LOW when another port writes to the

mailbox location of Port 4. Flag is cleared when Port 4

reads the contents of its mailbox. The same operation is

applicable to ports 1, 2, and 3.

TMS JTAG Test Mode Select Input. It controls the advance of

JTAG TAP state machine. State machine transitions occur

on the rising edge of TCK.

TCK JTAG Test Clock Input. This can be CLK of any port or

an external clock connected to the JTAG TAP.

TDI JTAG Test Data Input. This is the only data input. TDI

inputs will shift data serially in to the selected register.

TDO JTAG Test Data Output. This is the only data output.

TDO transitions occur on the falling edge of TCK. TDO

normally three-stated except when captured data is

shifted out of the JTAG TAP.

CLKBIST BIST Clock Input.

GND Thermal Ground for Heat Dissipation.

VSS Ground Input.

VDD Power Input.

VSS1 Address Lines Ground Input.

VDD1 Address Lines Power Input.

VSS2 Data Lines Ground Input.

VDD2 Data Lines Power Input.

Pin Definitions (continued)

Port 1 Port 2 Port 3 Port 4 Description

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CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 8 of 37

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Power Applied............................................–55°C to + 125°C

Supply Voltage to Ground Potential .............. –0.5V to + 4.6V

DC Voltage Applied to

Outputs in High-Z State..........................–0.5V to VCC + 0.5V

DC Input Voltage....................................–0.5V to VCC + 0.5V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage........................................... > 2200V

Latch-up Current..................................................... > 200 mA

Operating Range

Range Ambient Temperature VDD

Commercial 0°C to +70°C3.3V ±150 mV

Industrial –40°C to +85°C 3.3V ±150 mV

Electrical Characteristics Over the Operating Range

Parameter Description

Quadport DSE Family

Unit

–133 –100

Min. Typ. Max. Min. Typ. Max.

VOH Output HIGH Voltage

(VCC = Min., IOH = –4.0 mA)

2.4 2.4 V

VOL Output LOW Voltage

(VCC = Min., IOH = +4.0 mA)

0.4 0.4 V

VIH Input HIGH Voltage 2.0 2.0 V

VIL Input LOW Voltage 0.8 0.8 V

IOZ Output Leakage Current –10 10 –10 10 µA

ICC Operating Current (VCC = Max., IOUT = 0 mA)

Outputs Disabled, CE = VIL, f = fmax

350 700 300 550 mA

ISB1 Standby Current (four ports toggling at TTL

Levels,0 active)

CE1-4 ≥VIH, f = fMAX

80 200 60 150 mA

ISB2 Standby Current (four ports toggling at TTL

Levels, 1 active) CE1| CE2| CE3 | CE4 <VIL,

f = fMAX

150 300 125 250 mA

ISB3 Standby Current (four ports CMOS Level, 0

active) CE1–4 ≥VIH, f = 0

1.5 15 1.5 15 mA

ISB4 Standby Current (four ports CMOS Level, 1

active and toggling) CE1| CE2| CE3 | CE4 <

VIL, f = fMAX

110 290 85 240 mA

JTAG TAP Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

VOH1 Output HIGH Voltage IOH = −4.0 mA 2.4 V

VOL1 Output LOW Voltage IOL = 4.0 mA 0.4 V

VIH Input HIGH Voltage 2.0 V

VIL Input LOW Voltage 0.8 V

IXInput Leakage Current GND ≤VI≤VDD –100 100 µA

Capacitance

Parameter Description Test Conditions Max. Unit

CIN (All Pins) Input Capacitance TA= 25°C, f = 1 MHz,

VCC = 3.3V

10 pF

COUT (All Pins) Output Capacitance 10 pF

CIN (CLK Pins) Input Capacitance 15 pF

COUT (CLK Pins) Output Capacitance 15 pF

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CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 9 of 37

AC Test Load

Note:

5. Test conditions: C = 10 pF.

VTH =1.5V

OUTPUT

(a) Normal Load

R = 50Ω

Z0= 50Ω

[5]

3.0V

GND 90% 90%

10%

tRtF

10%

All Input Pulses

(b) Three-State Delay

VTH =1.5V

OUTPUT

5 pF

R = 50Ω

Z0= 50Ω

TDO

C= 10 pF

Z0=50Ω

GND

1.5V

50Ω

VTH =3.3V

OUTPUT

5 pF

R = 50Ω

Z0= 50Ω

[+] Feedback

CY7C0430BV

CY7C0430CV

Document #: 38-06027 Rev. *B Page 10 of 37

Switching Characteristics Over the Industrial Operating Range [6]

Parameter Description

CY7C0430BV and CY7C0430CV

Unit

–133 –100

Min. Max. Min. Max.

fMAX2[7] Maximum Frequency 133 100 MHz

tCYC2[7] Clock Cycle Time 7.5 10 ns

tCH2 Clock HIGH Time 3 4 ns

tCL2 Clock LOW Time 3 4 ns

tRClock Rise Time 2 3 ns

tFClock Fall Time 2 3 ns

tSA Address Set-up Time 2.3 3 ns

tHA Address Hold Time 0.7 0.7 ns

tSC Chip Enable Set-up Time 2.3 3 ns

tHC Chip Enable Hold Time 0.7 0.7 ns

tSW R/W Set-up Time 2.3 3 ns

tHW R/W Hold Time 0.7 0.7 ns

tSD Input Data Set-up Time 2.3 3 ns

tHD Input Data Hold Time 0.7 0.7 ns

tSB Byte Set-up Time 2.3 3 ns

tHB Byte Hold Time 0.7 0.7 ns

tSCLD CNTLD Set-up Time 2.3 3 ns

tHCLD CNTLD Hold Time 0.7 0.7 ns

tSCINC CNTINC Set-up Time 2.3 3 ns

tHCINC CNTINC Hold Time 0.7 0.7 ns

tSCRST CNTRST Set-up Time 2.3 3 ns

tHCRST CNTRST Hold Time 0.7 0.7 ns

tSCRD CNTRD Set-up Time 2.3 3 ns

tHCRD CNTRD Hold Time 0.7 0.7 ns

tSMLD MKLD Set-up Time 2.3 3 ns

tHMLD MKLD Hold Time 0.7 0.7 ns

tSMRD MKRD Set-up Time 2.3 3 ns

tHMRD MKRD Hold Time 0.7 0.7 ns

tOE Output Enable to Data Valid 6.5 8 ns

tOLZ[8] OE to Low-Z 1 1 ns

tOHZ[8] OE to High-Z 1 6 1 7 ns

tCD2 Clock to Data Valid 4.2 5 ns

tCA2 Clock to Counter Address Readback Valid 4.7 5 ns

tCM2 Clock to Mask Register Readback Valid 4.7 5 ns

tDC Data Output Hold After Clock HIGH 1 1 ns

tCKHZ[9] Clock HIGH to Output High-Z 1 4.8 1 6.8 ns

Notes:

6. If data is simultaneously written and read to the same address location and tCCS is violated, the data read from the address, as well as the subsequent data

remaining in the address is undefined.

7. fMAX2 for commercial is 135 MHz. tCYC2 Min. for commercial is 7.4 ns.

8. This parameter is guaranteed by design, but it is not production tested.

9. Valid for both address and data outputs.

[+] Feedback

Ce manuel convient aux modèles suivants

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