Cypress Semiconductor CY62167EV30 Manuel utilisateur

CY62167EV30 MoBL®

16-Mbit (1M x 16 / 2M x 8) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05446 Rev. *E Revised March 23, 2009

Features

■TSOP I Package Configurable as 1M x 16 or 2M x 8 SRAM

■Very High Speed: 45 ns

■Temperature Ranges

❐Industrial: –40°C to +85°C

❐Automotive-A: –40°C to +85°C

■Wide Voltage Range: 2.20V to 3.60V

■Ultra Low Standby Power

❐Typical standby current: 1.5 μA

❐Maximum standby current: 12 μA

■Ultra Low Active Power

❐Typical active current: 2.2 mA @ f = 1 MHz

■Easy Memory Expansion with CE1, CE2, and OE Features

■Automatic Power Down when Deselected

■CMOS for Optimum Speed and Power

■Offered in Pb-free 48-Ball VFBGA and 48-Pin TSOP I

Packages

Functional Description

The CY62167EV30 is a high performance CMOS static RAM

organized as 1M words by 16 bits or 2M words by 8 bits. This

device features an advanced circuit design that provides an ultra

low active current. Ultra low active current is ideal for providing

More Battery Life™(MoBL®) in portable applications such as

cellular telephones. The device also has an automatic power

down feature that reduces power consumption by 99 percent

when addresses are not toggling. Place the device into standby

mode when deselected (CE1HIGH or CE2 LOW or both BHE and

BLE are HIGH). The input and output pins (I/O0through I/O15)

are placed in a high impedance state when: the device is

deselected (CE1 HIGH or CE2LOW), outputs are disabled (OE

HIGH), both Byte High Enable and Byte Low Enable are disabled

(BHE, BLE HIGH), or a write operation is in progress (CE1LOW,

CE2HIGH and WE LOW).

To write to the device, take Chip Enables (CE1 LOW and CE2

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0through I/O7) is

written into the location specified on the address pins (A0through

A19). If Byte High Enable (BHE) is LOW, then data from the I/O

pins (I/O8through I/O15) is written into the location specified on

the address pins (A0through A19).

To read from the device, take Chip Enables (CE1 LOW and CE2

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appears

on I/O0to I/O7. If Byte High Enable (BHE) is LOW, then data from

memory appears on I/O8to I/O15. See the “Truth Table” on

page 9 for a complete description of read and write modes.

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

1M × 16 / 2M x 8

RAM Array IO0–IO7

ROW DECODER

A 8

A 7

A 6

A 5

A 2

COLUMN DECODER

A11

A12

A13

A14

A15

SENSE AMPS

DATA IN DRIVERS

A 4

A 3IO8–IO15

BLE

BHE

A16

A 0

A 1

A17

A 9

A18

A10

CE2

CE1

A19

BYTE

PowerDown

Circuit BHE

BLE

CE2

CE1

Logic Block Diagram

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CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 2 of 14

Pin Configuration

Figure 1. 48-Ball VFBGA (6 x 7 x 1mm) / (6 x 8 x 1mm) Top View [1, 2, 3]

Figure 2. 48-Pin TSOP I Top View [3, 4]

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Range Operating ICC (mA) Standby ISB2

(μA)

f = 1 MHz f = fmax

Min Typ[5] Max Typ[5] Max Typ[5] Max Typ[5] Max

CY62167EV30LL Industrial/Auto-A 2.2 3.0 3.6 45 2.2 4.0 25 30 1.5 12

A11

A10

CE1

I/O

Vss

I/O

BHE

CE2

A17

BLE

I/O

5I/O

I/O

A15

A14

A13

A19

A18 NC

A16

VCC

A1A2

A15

A14

A13

A12

A11

A10

A19

BHE

BLE

A18

A17

A16

BYTE

Vss

IO15/A20

IO7

IO14

IO6

IO13

IO5

IO12

IO4

Vcc

IO11

IO3

IO10

IO2

IO9

IO1

IO8

IO0

Vss

Notes

1. The information related to 6 x 7 x 1 mm VFBGA package is preliminary.

2. Ball H6 for the VFBGA package can be used to upgrade to a 32M density.

3. NC pins are not connected on the die.

4. The BYTE pin in the 48-TSOPI package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOPI package can also be used as a 2M X 8 SRAM

by tying the BYTE signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and IO8to IO14 pins are not used.

5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.

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CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 3 of 14

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Power Applied ........................................... –55°C to + 125°C

Supply Voltage to Ground

Potential .................................–0.3V to 3.9V VCC(max) + 0.3V

DC Voltage Applied to Outputs

in High Z State[6, 7]..................–0.3V to 3.9V VCC(max) + 0.3V

DC Input Voltage[6, 7]...........–0.3V to 3.9V (VCC(max) + 0.3V

Output Current into Outputs (LOW) ............................ 20 mA

Static Discharge Voltage........................................... >2001V

(MIL-STD-883, Method 3015)

Latch up Current...................................................... >200 mA

Operating Range

Device Range Ambient

Temperature VCC[8]

CY62167EV30LL Industrial/

Auto-A –40°Cto +85°C 2.2V to 3.6V

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions 45 ns (Industrial/Auto-A) Unit

Min Typ[5] Max

VOH Output HIGH Voltage 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 V

2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 V

VOL Output LOW Voltage 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 V

2.7 < VCC < 3.6 IOL = 2.1mA 0.4 V

VIH Input HIGH Voltage 2.2 < VCC < 2.7 1.8 VCC + 0.3V V

2.7 < VCC < 3.6 2.2 VCC + 0.3V V

VIL Input LOW Voltage 2.2 < VCC < 2.7 –0.3 0.6 V

2.7 < VCC < 3.6 For VFBGA package –0.3 0.8 V

For TSOP I package –0.3 0.7[9] V

IIX Input Leakage Current GND < VI< VCC –1 +1 μA

IOZ Output Leakage Current GND < VO <VCC, Output Disabled –1 +1 μA

ICC VCC Operating Supply

Current

f = fMAX = 1/tRC VCC = VCC(max)

IOUT = 0 mA

CMOS levels

25 30 mA

f = 1 MHz 2.2 4.0 mA

ISB1 Automatic CE Power Down

Current—CMOS Inputs CE1> VCC − 0.2V or CE2 <0.2V

VIN >VCC − 0.2V, VIN <0.2V,

f = fMAX (Address and Data Only),

f = 0 (OE, WE, BHE and BLE), VCC =3.60V

1.5 12 μA

ISB2[10] Automatic CE Power Down

Current—CMOS Inputs CE1> VCC −0.2V or CE2< 0.2V,

VIN > VCC −0.2V or VIN < 0.2V,

f = 0, VCC = 3.60V

1.5 12 μA

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = VCC(typ)

10 pF

COUT Output Capacitance 10 pF

Notes

6. VIL(min) = –2.0V for pulse durations less than 20 ns.

7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.

8. Full Device AC operation assumes a 100 μs ramp time from 0 to VCC (min) and 200 μs wait time after VCC stabilization.

9. Under DC conditions the device meets a VIL of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7V. This is

applicable to TSOP I package only.

10. Only chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating

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CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 4 of 14

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions VFBGA

(6 x 7 x 1mm)

VFBGA

(6 x 8 x 1mm) TSOP I Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still Air, soldered on a 3 × 4.5 inch,

two-layer printed circuit board

27.74 55 60 °C/W

ΘJC Thermal Resistance

(Junction to Case)

9.84 16 4.3 °C/W

Shaded areas contain preliminary information.

Figure 3. AC Test Loads and Waveforms

Parameters 2.2V to 2.7V 2.7V to 3.6V Unit

R1 16667 1103 Ω

R2 15385 1554 Ω

RTH 8000 645 Ω

VTH 1.20 1.75 V

Data Retention Characteristics

Over the Operating Range

Parameter Description Conditions Min Typ[5] Max Unit

VDR VCC for Data Retention 1.5 V

ICCDR[10] Data Retention Current VCC = 1.5V to 3.0V, CE1> VCC −0.2V, CE2

<0.2V, VIN > VCC −0.2V or VIN < 0.2V

Industrial/

Auto-A

-45ZXI

(TSOP I)

8μA

VCC = 1.5V, CE1> VCC −0.2V, CE2< 0.2V,

VIN > VCC −0.2V or VIN < 0.2V

Industrial -45BAXI/

-45BVXI/

-45BVI

(VFBGA)

10 μA

tCDR[11] Chip Deselect to Data

Retention Time

0ns

tR[12] Operation Recovery Time tRC ns

Figure 4. Data Retention Waveform

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10% 90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalent to: THÉVENIN EQUIVALENT

ALL INPUT PULSES

Notes

11. Tested initially and after any design or process changes that may affect these parameters.

12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 μs or stable at VCC(min) > 100 μs.

13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE.

VCC(min)

tCDR

VDR >1.5 V

DATA RETENTION MODE

CE1or

VCC

BHE.BLE

CE2

[13]

[+] Feedback

CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 5 of 14

Switching Characteristics

Over the Operating Range[14, 15]

Parameter Description 45 ns (Industrial/Auto-A) Unit

Min Max

READ CYCLE

tRC Read Cycle Time 45 ns

tAA Address to Data Valid 45 ns

tOHA Data Hold from Address Change 10 ns

tACE CE1LOW and CE2 HIGH to Data Valid 45 ns

tDOE OE LOW to Data Valid 22 ns

tLZOE OE LOW to LOW Z[16] 5ns

tHZOE OE HIGH to High Z[16, 17] 18 ns

tLZCE CE1LOW and CE2 HIGH to Low Z[16] 10 ns

tHZCE CE1HIGH and CE2 LOW to High Z[16, 17] 18 ns

tPU CE1LOW and CE2 HIGH to Power Up 0 ns

tPD CE1HIGH and CE2 LOW to Power Down 45 ns

tDBE BLE / BHE LOW to Data Valid 45 ns

tLZBE BLE / BHE LOW to Low Z[16] 10 ns

tHZBE BLE / BHE HIGH to HIGH Z[16, 17] 18 ns

WRITE CYCLE[18]

tWC Write Cycle Time 45 ns

tSCE CE1LOW and CE2 HIGH to Write End 35 ns

tAW Address Setup to Write End 35 ns

tHA Address Hold from Write End 0 ns

tSA Address Setup to Write Start 0 ns

tPWE WE Pulse Width 35 ns

tBW BLE / BHE LOW to Write End 35 ns

tSD Data Setup to Write End 25 ns

tHD Data Hold from Write End 0 ns

tHZWE WE LOW to High-Z[16, 17] 18 ns

tLZWE WE HIGH to Low-Z[16] 10 ns

Notes

14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0

to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4.

15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.

16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.

17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.

18. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a

write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.

[+] Feedback

CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 6 of 14

Switching Waveforms

Figure 5 shows address transition controlled read cycle waveforms.[19, 20]

Figure 5. Read Cycle No. 1

Figure 6 shows OE controlled read cycle waveforms.[20, 21]

Figure 6. Read Cycle No. 2

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tPD

tHZBE

tLZBE

HZCE

tDBE

CE1

ADDRESS

CE2

BHE/BLE

DATA OUT

VCC

SUPPLY

CURRENT

HIGH

ICC

ISB

IMPEDANCE

Notes

19. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH.

20. WE is HIGH for read cycle.

21. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2transition HIGH.

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CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 7 of 14

Figure 7 shows WE controlled write cycle waveforms.[18, 22, 23]

Figure 7. Write Cycle No. 1

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

NOTE 24

CE1

ADDRESS

CE2

DATA I/O

BHE/BLE

Notes

22. Data IO is high impedance if OE = VIH.

23. If CE1goes HIGH and CE2goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

24. During this period the I/Os are in output state. Do not apply input signals.

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CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 8 of 14

Figure 8 shows CE1or CE2controlled write cycle waveforms.[18, 22, 23]

Figure 8. Write Cycle No. 2

Figure 9 shows WE controlled, OE LOW write cycle waveforms.[23]

Figure 9. Write Cycle No. 3

Switching Waveforms (continued)

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

tSA

NOTE 24

CE1

ADDRESS

CE2

DATA I/O

BHE/BLE

VALID DATA

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

tBW

NOTE 24

ADDRESS

DATA I/O

BHE

/BLE

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CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 9 of 14

Figure 10 shows BHE/BLE controlled, OE LOW write cycle waveforms.[23]

Figure 10. Write Cycle No. 4

Truth Table

CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power

HXXXXXHighZ Deselect/PowerDown Standby (ISB)

XLXXXXHighZ Deselect/PowerDown Standby (ISB)

XXXXHHHighZ Deselect/PowerDown Standby (ISB)

L H H L L L Data Out (I/O0–I/O15) Read Active (ICC)

L H H L H L Data Out (I/O0–I/O7);

High Z (I/O8–I/O15)

Read Active (ICC)

LHHLLHHighZ(I/O

0–I/O7);

Data Out (I/O8–I/O15)

Read Active (ICC)

L H H H L H High Z Output Disabled Active (ICC)

LHHHHLHighZ OutputDisabled Active(I

CC)

L H H H L L High Z Output Disabled Active (ICC)

L H L X L L Data In (I/O0–I/O15) Write Active (ICC)

L H L X H L Data In (I/O0–I/O7);

High Z (I/O8–I/O15)Write Active (ICC)

LHLXLHHighZ(I/O

0–I/O7);

Data In (I/O8–I/O15)

Write Active (ICC)

Switching Waveforms (continued)

tHD

tSD

tSA

tHA

tAW

tWC

VALID DATA

tBW

tSCE

tPWE

NOTE 24

ADDRESS

DATA IO

BHE

/BLE

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CY62167EV30 MoBL®

Document #: 38-05446 Rev. *E Page 10 of 14

Ordering Information

Speed

(ns) Ordering Code

Package

Diagram Package Type Operating

Range

45 CY62167EV30LL-45BAXI 001-13297 48-ball VFBGA (6 x 7 x 1 mm) (Pb-free) Industrial

CY62167EV30LL-45BVI 51-85150 48-ball VFBGA (6 x 8 x 1 mm)

CY62167EV30LL-45BVXI 51-85150 48-ball VFBGA (6 x 8 x 1 mm) (Pb-free)

CY62167EV30LL-45ZXI 51-85183 48-pin TSOP I (Pb-free)

CY62167EV30LL-45ZXA 51-85183 48-pin TSOP I (Pb-free) Automotive-A

Shaded areas contain preliminary information. Please contact your local Cypress sales representative for availability of these parts.

Package Diagrams

Figure 11. 48-Ball VFBGA (6 x 7 x 1 mm), 001-13297

NOTES:

1. ALL DIMENSION ARE IN MM [MAX/MIN]

2. JEDEC REFERENCE : MO-216

3. PACKAGE WEIGHT : 0.03g 001-13297-*A

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