Cypress Semiconductor CY7C1018CV33 Manuel utilisateur
128K x 8 Static RAM
CY7C1018CV33
Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05131 Rev. *D Revised August 3, 2006
Features
• Pin- and function-compatible with CY7C1018BV33
•Highspeed
—tAA = 10 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Data retention at 2.0V
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in Pb-free and non Pb-free 300-mil-wide
32-pin SOJ
Functional Description[1]
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0through I/O7) is then written into the location
specified on the address pins (A0through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
Note:
1. For guidelines on SRAMsystem designs, please referto the ‘System DesignGuidelines’ Cypress application note, availableon the internet at www.cypress.com.
14
15
Logic Block Diagram Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A11
A13
A12
A
A10
CE
A
A16
A9
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15 17
18
A7
A1
A2
A3
CE
I/O0
I/O1
VCC
A13
A16
A15
OE
I/O7
I/O6
A12
A11
A10
A9
I/O2
A0
A4
A5
A6
I/O4
VCC
I/O5
A8
I/O3
WE
VSS
A14
VSS
128K x 8
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CY7C1018CV33
Document #: 38-05131 Rev. *D Page 2 of 7
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC Relative to GND[2] ...–0.5V to + 4.6V
DC Voltage Applied to Outputs[6]
in High-Z State.......................................–0.5V to VCC + 0.5V
DC Input Voltage[2].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage...........................................> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Selection Guide
-10 -12 -15 Unit
Maximum Access Time 10 12 15 ns
Maximum Operating Current Comm’l 90 85 80 mA
Ind’l 85 mA
Maximum Standby Current 5 5 5 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V ±10%
Industrial –40°C to +85°C 3.3V ±10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
–10 –12 –15
UnitMin. Max. Min. Max. Min. Max.
VOH Output HIGH Voltage VCC = Min.,
IOH = – 4.0 mA 2.4 2.4 2.4 V
VOL Output LOW Voltage VCC = Min.,
IOL = 8.0 mA 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 2.0 VCC + 0.3 V
VIL Input LOW Voltage[2] –0.3 0.8 –0.3 0.8 –0.3 0.8 V
IIX Input Leakage
Current GND < VI< VCC –1 +1 –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND < VI <VCC,
Output Disabled –1 +1 –1 +1 –1 +1 µA
ICC VCC Operating
Supply Current VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Comm’l 90 85 80 mA
Ind’l 85 mA
ISB1 Automatic CE
Power-down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
Comm’l 15 15 15 mA
Ind’l 15 mA
ISB2 Automatic CE
Power-down Current
—CMOS Inputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Comm’l 5 5 5 mA
Ind’l 5 mA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = 3.3V 8pF
COUT Output Capacitance 8 pF
Notes:
2. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
3. Tested initially and after any design or process changes that may affect these parameters.
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CY7C1018CV33
Document #: 38-05131 Rev. *D Page 3 of 7
AC Test Loads and Waveforms[4]
Switching CharacteristicsOver the Operating Range[5]
Parameter Description
-10 -12 -15
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 10 12 15 ns
tAA Address to Data Valid 10 12 15 ns
tOHA Data Hold from Address Change 3 3 3ns
tACE CE LOW to Data Valid 10 12 15 ns
tDOE OE LOW to Data Valid 5 6 7ns
tLZOE OE LOW to Low-Z 0 0 0ns
tHZOE OE HIGH to High-Z[6, 7] 567ns
tLZCE CE LOW to Low-Z[7] 333ns
tHZCE CE HIGH to High-Z[6, 7] 567ns
tPU[8] CE LOW to Power-up 0 0 0ns
tPD[8] CE HIGH to Power-down 10 12 15 ns
Write Cycle[9, 10]
tWC Write Cycle Time 10 12 15 ns
tSCE CE LOW to Write End 8 9 10 ns
tAW Address Set-up to Write End 8 9 10 ns
tHA Address Hold from Write End 0 0 0ns
tSA Address Set-up to Write Start 0 0 0ns
tPWE WE Pulse Width 7 8 10 ns
tSD Data Set-up to Write End 5 6 8ns
tHD Data Hold from Write End 0 0 0ns
tLZWE WE HIGH to Low-Z[7] 333ns
tHZWE WE LOW to High-Z[6, 7] 567ns
Notes:
4. AC characteristics (except High-Z) for all speeds are tested using the Thèvenin load shown in Figure (a). High-Z characteristics are tested for allspeeds using
the test load shown in Figure (c).
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in (d) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. This parameter is guaranteed by design and is not tested.
9. The internal Write time of the memory is defined by the overlap of CELOWandWE LOW. CEandWE mustbeLOW toinitiateaWrite,andthe transitionofany ofthese
signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal thatterminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
3.3V
OUTPUT
30 pF
(a)
R 317Ω
R2
351Ω
Rise Time: 1 V/ns Fall Time: 1 V/ns
(b)
3.3V
OUTPUT
5 pF
(c)
R 317Ω
R2
351Ω
High-Z characteristics:
[+] Feedback
CY7C1018CV33
Document #: 38-05131 Rev. *D Page 4 of 7
Switching Waveforms
Read Cycle No. 1[11, 12]
Read Cycle No. 2 (OE Controlled)[12, 13]
Write Cycle No. 1 (CE Controlled)[14, 15]
Notes:
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for Read cycle.
13. Address valid prior to or coincident with CEtransition LOW.
14. Data I/O is high impedance if OE= VIH.
15. If CEgoes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
tSCE
CE
ADDRESS
WE
DATA I/O
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CY7C1018CV33
Document #: 38-05131 Rev. *D Page 5 of 7
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
Write Cycle No. 3 (WE Controlled, OE LOW)[10, 15]
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 16
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 16
Truth Table
CE OE WE I/O0–I/O7Mode Power
H X X High-Z Power-down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High-Z Selected, Outputs Disabled Active (ICC)
Note:
16. During this period the I/Os are in the output state and input signals should not be applied.
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CY7C1018CV33
Document #: 38-05131 Rev. *D Page 6 of 7
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Package Diagram
All product and company names mentioned in this document are the trademarks of their respective holders.
Ordering Information
Speed
(ns) Ordering Code Package
Diagram Package Type Operating
Range
10 CY7C1018CV33-10VC 51-85041 32-lead 300-mil Molded SOJ Commercial
12 CY7C1018CV33-12VC 32-lead 300-mil Molded SOJ Commercial
CY7C1018CV33-12VXI 32-lead 300-mil Molded SOJ (Pb-Free) Industrial
15 CY7C1018CV33-15VXC 32-lead 300-mil Molded SOJ (Pb-Free) Commercial
32-lead (300-mil) Molded SOJ (51-85041)
51-85041-*A
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CY7C1018CV33
Document #: 38-05131 Rev. *D Page 7 of 7
Document History Page
Document Title: CY7C1018CV33 128K x 8 Static RAM
Document Number: 38-05131
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 109426 12/14/01 HGK New Data Sheet
*A 113432 04/10/02 NSL AC Test Loads split based on speed
*B 115046 05/30/02 HGK ICC and ISB1 modified
*C 116476 09/16/02 CEA Add applications foot note on data sheet, pg 1
*D 493543 See ECN NXR Added Industrial Operating Range
Removed 8 ns speed bin from Product offering
Changed the description of IIX from Input Load Current to
Input Leakage Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the Ordering Information Table
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