Analog Devices AD9284-250EBZ Manuel utilisateur

AD9284-250EBZ User Guide

UG-178

One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: 781.329.4700 •Fax: 781.461.3113 •www.analog.com

Evaluating the AD9284 Analog-to-Digital Converter

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS.Rev. A | Page 1 of 24

FEATURES

Full featured evaluation board for the AD9284

SPI interface for setup and control

Support LVDS output mode option

External or on-board oscillator options

Balun/transformer or amplifier input drive options

Switching power supply

VisualAnalog™ and SPIController software interfaces

EQUIPMENT NEEDED

Analog signal source and antialiasing filter

Sample clock source (if not using the on-board oscillator)

Two switching power supplies (6.0 V, 2.5 A),

CUI EPS060250UH-PHP-SZ, provided

PC running 32-bit Windows® XP, Window Vista, or Windows 7

USB 2.0 port, recommended (USB 1.1-compatible)

AD9284 evaluation board

HSC-ADC-EVALCZ FPGA-based data capture kit

SOFTWARE NEEDED

VisualAnalog

SPIController

DOCUMENTS NEEDED

AD9284 data sheet

HSC-ADC-EVALCZ data sheet

AN-905 Application Note, VisualAnalog Converter Evaluation

Tool Version 1.0 User Manual

AN-878 Application Note, High Speed ADC SPI Control Software

AN-877 Application Note, Interfacing to High Speed ADCs via SPI

AN-835 Application Note, Understanding High Speed ADC

Testing and Evaluation

GENERAL DESCRIPTION

This user guide describes the AD9284 evaluation board,

which provides all of the support circuitry required to operate

the AD9284 in its various modes and configurations. The

application software used to interface with the device is also

described.

The AD9284 data sheet provides additional information and

should be consulted when using the evaluation board. All

documents and software tools are available at the FIFO page.

For additional information or questions, send an email to

highspeed.converters@analog.com.

TYPICAL MEASUREMENT SETUP

09228-001

9284EE01

REV A

AD9284

9284EE02AHSC-ADC-EVALCZ

Figure 1. AD9284 Evaluation Board and HSC-ADC-EVALCZ Data Capture Board

UG-178 AD9284-250EBZ User Guide

Rev. A | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Equipment Needed........................................................................... 1

Software Needed............................................................................... 1

Documents Needed.......................................................................... 1

General Description ......................................................................... 1

Typical Measurement Setup ............................................................ 1

Revision History ............................................................................... 2

Evaluation Board Hardware ............................................................ 3

Power Supplies .............................................................................. 3

Input Signals...................................................................................3

Output Signals ...............................................................................3

Default Operation and Jumper Selection Settings....................4

Evaluation Board Software Quick Start Procedures.....................5

Configuring the Board .................................................................5

Using the Software for Testing.....................................................5

Evaluation Board Schematics and Artwork...................................9

Ordering Information.................................................................... 22

Bill of Materials........................................................................... 22

REVISION HISTORY

6/14—Rev. 0 to Rev. A

Changes to Figure 13........................................................................ 9

Changes to Figure 14...................................................................... 10

Changes to Figure 15...................................................................... 11

Changes to Figure 16...................................................................... 12

Changes to Figure 17...................................................................... 13

Changes to Figure 18...................................................................... 14

Changes to Figure 19...................................................................... 15

5/11—Revision 0: Initial Version

AD9284-250EBZ User Guide UG-178

Rev. A | Page 3 of 24

EVALUATION BOARD HARDWARE

The AD9284 evaluation board provides all of the support

circuitry required to operate the AD9284 in its various modes

and configurations. Figure 2 shows the typical bench charac-

terization setup used to evaluate the ac performance of the

AD9284. It is critical that the signal sources used for the analog

input and clock have very low phase noise (<1 ps rms jitter) to

realize the optimum performance of the signal chain. Proper

filtering of the analog input signal to remove harmonics and

lower the integrated or broadband noise at the input is necessary

to achieve the specified noise performance.

See the Evaluation Board Software Quick Start Procedures

section to get started, and see Figure 13 to Figure 25 for the

complete schematics and layout diagrams. These diagrams

demonstrate the routing and grounding techniques that

should be applied at the system level when designing

application boards using the AD9284.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching

power supply that provides a 6 V, 2 A maximum output. Connect

the supply to the rated 100 V ac to the 240 V ac wall outlet at

47 Hz to 63 Hz. The output from the supply is provided through

a 2.1 mm inner diameter jack that connects to the printed circuit

board (PCB) at J101. The 6 V supply is fused and conditioned

on the PCB before connecting to the low dropout linear regulators

(default configuration) that supply the proper bias to each of the

various sections on the board.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal

generators with low phase noise, such as the Rohde & Schwarz SMA,

or HP8644B signal generators or an equivalent. Use a 1 m shielded,

RG-58, 50 Ω coaxial cable for connecting to the evaluation

board. Enter the desired frequency and amplitude (see the

specifications in the AD9284 data sheet). When connecting the

analog input source, a multipole, narrow-band, band-pass filter

with 50 Ω terminations is recommended. Analog Devices, Inc.,

uses TTE and K&L Microwave, Inc., band-pass filters. The

filters should be connected directly to the evaluation board.

If an external clock source is used, it should also be supplied

with a clean signal generator as previously specified. Typically,

most Analog Devices evaluation boards can accept ~2.8 V p-p or

13 dBm sine wave input for the clock.

OUTPUT SIGNALS

The default setup uses the Analog Devices high speed converter

evaluation platform (HSC-ADC-EVALCZ) for data capture.

6V DC

2A MAX

6V DC

2A MAX

SWITCHING

POWER

SUPPLY

SWITCHING

POWER

SUPPLY

WALL OUTLET

100V TO 240V AC

47Hz TO 63Hz

PC RUNNING

VisualAnalog

AND SPIController

USER SOFTWARE

SIGNALGENERATOR

CLOCK SOURCE

SIGNALGENERATOR

ANALOG FILTER

SIGNALGENERATOR

ANALOG FILTER

09228 -002

9284EE01

REVA

AD9284

9284EE02A HSC-ADC-EVALCZ

Figure 2. Evaluation Board Connection

UG-178 AD9284-250EBZ User Guide

Rev. A | Page 4 of 24

DEFAULT OPERATION AND JUMPER SELECTION

SETTINGS

This section explains the default and optional settings or modes

allowed on the AD9284 evaluation board.

Power Circuitry

Connect the switching power supply that is supplied in the

evaluation kit between a rated 100 V ac to 240 V ac wall outlet

at 47 Hz to 63 Hz and J101.

Analog Input

The A and B channel inputs on the evaluation board are set up as

simultaneous channel sampling using a single transformer (per

channel) analog input with a 50 Ω impedance. The default

analog input configuration supports analog input frequencies

of up to ~200 MHz. This input network is optimized to support

a wide frequency band. See the AD9284 data sheet for additional

information on the recommended networks for different input

frequency ranges. The nominal input drive level is 10.5 dBm to

achieve 1.5 V p-p full scale into 50 Ω. At higher input frequencies,

slightly higher input drive levels are required due to losses in the

front-end network.

VREF

The AD9284 operates with a fixed 1.0 V reference. This sets the

analog input span to 1.5 V p-p.

RBIAS

RBIAS has a default setting of 10 kΩ (R206) to ground and is

used to set the ADC core bias current. Note that using a resistor

value other than a 10 kΩ, 1% resistor for RBIAS may degrade

the performance of the device.

Clock Circuitry

The default clock input circuit on the AD9284 evaluation

board uses a simple transformer-coupled circuit using a high

bandwidth 1:1 impedance ratio transformer (T501) that adds a

very low amount of jitter to the clock path. The clock input is

50 Ω terminated and ac-coupled to handle single-ended sine wave

types of inputs. The transformer converts the single-ended input to

a differential signal that is clipped by CR501 before entering the

ADC clock inputs. The AD9284 board has on-chip circuitry to

distribute a single clock to both ADC channels.

Non-SPI Mode

For users who want to operate the DUT without using SPI,

remove the shorting jumpers on J302. This disconnects the

CSB, SCLK, and SDIO/PWDN pins from the SPI control bus,

allowing the DUT to operate in non-SPI mode. In this mode,

the SDIO/PWDN pin takes on an alternate function to enable

power down functionality.

To enable the power-down feature, add a shorting jumper across

J202 at Pin 2 and Pin 3 to connect the SDIO/PDWN pin to

DRVDD.

AD9284-250EBZ User Guide UG-178

Rev. A | Page 5 of 24

EVALUATION BOARD SOFTWARE QUICK START PROCEDURES

This section provides quick start procedures for using the AD9284

evaluation board. Both the default and optional settings are

described.

CONFIGURING THE BOARD

Before using the software for testing, configure the evaluation

board using the following steps:

1. Connect the evaluation board to the data capture board, as

shown in Figure 1 and Figure 2.

2. Connect one 6 V, 2.5 A switching power supply (such as

the CUI, Inc., EPS060250UH-PHP-SZ) to the AD9284

board.

3. Connect one 6 V, 2.5 A switching power supply (such

as the supplied CUI EPS060250UH-PHP-SZ) to the

HSC-ADC-EVALCZ board.

4. Connect the HSC-ADC-EVALCZ board to the PC with a

USB cable.

5. On the ADC evaluation board, confirm that six jumpers

are installed as described as follows:

•J103, Pin 2 and Pin 3 (clock with regulator)

•J104, Pin 2 and Pin 3 (amp with regulator)

•J105, Pin 2 and Pin 3 (DRVDD with regulator)

•J106, Pin 2 and Pin 3 (AVDD with regulator)

•J201, Pin 1 and Pin 2 (SCLK SPI)

•J202, Pin 1 and Pin 2 (SDIO SPI)

6. On the ADC evaluation board, use a clean signal generator

with low phase noise to provide an input signal to the desired

A and/or B channel(s). Use a 1 m, shielded, RG-58, 50 Ω

coaxial cable to connect the signal generator. For best results,

use a narrow-band band-pass filter with 50 Ω terminations

and an appropriate center frequency. (Analog Devices uses

TTE, Allen Avionics, and K&L band-pass filters.)

USING THE SOFTWARE FOR TESTING

Setting Up the ADC Data Capture

After configuring the board, set up the ADC data capture using

the following steps:

1. Open VisualAnalog on the connected PC. The appro-

priate part type should be listed in the status bar of the

VisualAnalog – New Canvas window. Select the template

that corresponds to the type of testing to be performed (see

Figure 3).

Note that once power is applied to the AD9284 evaluation

board, the device is powered down. To wake up the device,

the SDIO/PWDN pin must be pulled low. This occurs

automatically by VisualAnalog after you complete Step 1.

09228-003

Figure 3. VisualAnalog, New Canvas Window

2. After the template is selected, a message appears asking if

the default configuration can be used to program the FPGA

(see Figure 4). Click Ye s to close the window.

09228-004

Figure 4. VisualAnalog Default Configuration Message

3. To change features to settings other than the default settings,

click the Expand Display button, located on the bottom

right corner of the window, to see what is shown in Figure 6.

Detailed instructions for changing the features and capture

settings can be found in the AN-905 Application Note,

VisualAnalog Converter Evaluation Tool Version 1.0 User

Manual. After the changes are made to the capture settings,

click the collapse display button (see the collapsed display

in Figure 5).

09228-005

Figure 5. VisualAnalog Window Toolbar, Collapsed Display

UG-178 AD9284-250EBZ User Guide

Rev. A | Page 6 of 24

09228-006

Figure 6. VisualAnalog Main Window

AD9284-250EBZ User Guide UG-178

Rev. A | Page 7 of 24

Setting Up the SPIController Software

After the ADC data capture board setup is complete, set up

the SPIController software using the following procedure:

1. Open the SPIController software by selecting Start >

SPIController or by double-clicking the SPIController

software desktop icon.

If prompted for a configuration file, select the appropriate one.

If not, check the title bar of the window to determine

which configuration is loaded. If necessary, choose

Cfg Open from the File menu and select the appropriate

file based on your part type. Note that the CHIP ID(1)

field should be filled to indicate whether the correct

SPIController configuration file is loaded (see Figure 7).

09228-007

Figure 7. SPIController, CHIP ID(1) Box

2. Click the New DUT button in the SPIController window (see

Figure 8).

09228-008

Figure 8. SPIController, New DUT Button

3. In the ADCBase 0 tab of the SPIController window, you can

access all global register settings (see Figure 9). See the AD9284

data sheet; the AN-878 Application Note, High Speed ADC SPI

Control Software; and the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI, for additional information.

09228-009

Figure 9. SPIController, ADC Base0

4. Note that other settings can be changed on the ADCBase 0

page (see Figure 9) and the ADC A and ADC B pages (see

Figure 10) to set up the part in the desired mode. The ADCBase 0

page settings affect the entire part, whereas the settings on the

ADC A and ADC B pages affect the selected channel only. See

the AD9284 data sheet; the AN-878 Application Note, High

Speed ADC SPI Control Software; and the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI, for additional

information on the available settings.

09228-010

Figure 10. SPIController, ADC A Page

UG-178 AD9284-250EBZ User Guide

Rev. A | Page 8 of 24

5. Click the Run button in the VisualAnalog toolbar (see

Figure 11).

09228-011

Figure 11. Run Button in VisualAnalog Toolbar, Collapsed Display

Adjusting the Amplitude of the Input Signal

The next step is to adjust the amplitude of the input signal for

each channel as follows:

1. Adjust the amplitude of the input signal so that the funda-

mental is at the desired level (examine the Fund Power

reading in the left panel of the VisualAnalog Graph - AD9284

FFT window). See Figure 12.

09228-012

Figure 12. Graph Window of VisualAnalog

2. Repeat this procedure for Channel B.

3. Click the disk icon within the Graph window to save the

performance plot data as a .csv formatted file.

Troubleshooting Tips

If the FFT plot appears abnormal, do the following:

•If you see a normal noise floor when you disconnect the

signal generator from the analog input, be sure you are not

overdriving the ADC. Reduce the input level, if necessary.

•In VisualAnalog, click the Settings button in the Input

Formatter block. Check that Number Format is set to the

correct encoding (offset binary by default). Repeat for the

other channel.

If the FFT appears normal but the performance is poor, check

the following:

•Make sure an appropriate filter is used on the analog input.

•Make sure the signal generators for the clock and the

analog input are clean (low phase noise).

•Change the analog input frequency slightly if noncoherent

sampling is being used.

•Make sure the SPI configuration file matches the product

being evaluated.

If the FFT window remains blank after Run is clicked, do the

following:

•Make sure the evaluation board is securely connected to

the HSC-ADC-EVALCZ board.

•Make sure the FPGA has been programmed by verifying

that the DONE LED is illuminated on the HSC-ADC-

EVALCZ board. If this LED is not illuminated, make sure

the U4 switch on the HSC-ADC-EVALCZ board is in the

correct position for USB configuration.

•Make sure the correct FPGA program was installed by

selecting the Settings button in the ADC Data Capture

block in VisualAnalog. Then select the FPGA tab and

verify that the proper FPGA bin file is selected for the part.

If VisualAnalog indicates that the FIFO Capture timed out,

do the following:

•Make sure all power and USB connections are secure.

•Probe the DCOA signal at RN601 on the evaluation board

and confirm that a clock signal is present at the ADC

sampling rate.

AD9284-250EBZ User Guide UG-178

Rev. A | Page 9 of 24

EVALUATION BOARD SCHEMATICS AND ARTWORK

09228-013

SUPPLY REGULATORS

POWER SUPPLY INPUT

VARIABLE POWER SUPPLY INPUT

3.3V

GND

DVDD (1.8V)

GND

AVDD (1.8V)

GND

1UF

10UF

10UF10UF

10UF 10UF

10UF10UF

10UF

LTST-C190GKT

ADP2108AUJZ-3.3-R7

SPI_DVDD

REF_AVDD

DRVDD_REG

AVDD_REG

3.3V_AMPVDD_REG

DRVDD

AVDD

3.3V_AMPVDD

3.3V_CLK_REG

BNX016-01

RAPC722X

100NH

0.1UF

VIN

1UF

S2A-TP

BLK BLK

S2A-TP

2.2UH

0.1UF

3.3V_CLK

0.1UF

Z5.530.3625.0

ADP2108AUJZ-1.8-R7

1.6A

3.3V_CLK_REG

39OHM

3.3V_AMPVDD_REG

39OHM

AVDD_BENCH

39OHM

DRVDD_BENCH

39OHM

AVDD_REG

39OHM

DRVDD_REG

39OHM

300

100K

E102

1 2

E101

1 2

C101

F101

CR101

FL101

R101

CR103

CR102

TP101

E112

1 2

E111

1 2

C125

C127

TP102

C129 C130

C128

E109

1 2

E110

1 2

C126

J102 1

R102C102 C103 C104

L101 L102

C105 C106 C107

C109

R103

E105

1 2

E107

1 2

C112

C114

C111

L104

C110

L103

U101

U102

C115 C117C116

C108

C113

J101

1 2

J103

J104

J105

J106

R104

R105

GND

GND GND

GND

GND GND GND

GND

GND GND

GND

VIN

GND

VIN

GND GND

GND

ALIAS

GND

Figure 13. Board Power Input and Supply Circuits

UG-178 AD9284-250EBZ User Guide

Rev. A | Page 10 of 24

09228-014

AVDD PINS 48

DURINGLAYOUT CHECK IF WE CAN FIT 0402 ELSE 0201

DECOUPLINGCAPACITORS,ONE ON THE TOP AND ONE ON THE BOTTOM CLOSE TOTHE PINS

SHARE PADS

2-3 PWRDN MODE

1-2 SDIO MODE

AVDD PIN 1

NO CONNECT CMOS MODE (DEFAULT)

1-2 SCLK MODE

2-3 LVDS MODE

DEFAULT HIGH (EN)

CONNECT OUTPUT DISABLED

DEFAULT LOW (DISABLED)

NOCONNECT(DEFAULT)

REFIN CKT

DRVDD PIN 20

DRVDD PIN 39

AVDD PINS 8 & 9

AVDD PIN 6

AVDD PINS 12

AVDD PINS 13

AVDD PINS 16

AVDD PINS 45

AVDD PIN 4

CONNECT CLKB ENABLED

AD9284

65/135/250 MSPS

AVDD

ENC A+

SPI_CSB

SPI_SDIO/PWRDN

SPI_SCLK/CMOS_LVDS

DRGND

DRVDD

ENC A-

D6A(D7A-/D7B-)

AVDD

AIN B-

AIN B+

AVDD

REF IN

AVDD

CMVOUT

AVDD

AIN A+

AIN A-

AVDD D5A/(D6A+ /D6B+)

D5B/(D2A+/D2B+)

D6B/(D3A-/D3B-)

D7B/(D3A+/D3B+)

DCOB/(DCO-)

DCOA/(DCO+)

D0A/(D4A-/D4B-)

D1A/(D4A+/D4B+)

D2A/(D5A-/D5B-)

D3A/(D5A+/D5B+)

OUTPUT_ENABLE

D4A/(D6A-/D6B-)

D7A(D7A+/D7B+)

D4B/(D2A-/D2B-)

D1B/(D0A+/D0B+)

D2B/(D1A-/D1B-)

D3B/(D1A+/D1B+)

CLOC K B ENABLE

D0B/(D0A-/D0B-)

RBIAS

DRGND

DRVDD

ENC B-

AVDD

ENC B+

D7A_D7P

ADR512ARTZ-REEL7

AVDD

DRVDD

0.1UF

AVDD AVDD

DRVDD DRVDD

BLK

SDIO_DUT

DRVDD

SAMTECTSW10608GS3PIN

D0B_D0M

D1B_D0P

D2B_D1M

D3B_D1P

D6A_D7M

SCLK_DUT_CMOS_LVDS

DRVDD

SCLK_DUT

SAMTECTSW10608GS3PIN

.1UF .1UF

.1UF

.1UF .1UF

.1UF

.1UF .1UF

0.1UF

SDIO_DUT_PWRDN

AVDD

.1UF

.1UF .1UF

DNI

0.1UF

CMV_OUT

REF_AVDD

.1UF

AVDD

.1UF

5K TSW-102-08-G-S

DRVDD

TSW-102-08-G-S

10K

2.7K

RBIAS

J204

J203

U202

R201

R203

R202

R205 TP201

C207

C205

C203

C201

C209

C211

C215

C223

C204

C202

C206

C208

C210

C212

C214

C216

C218

C220C219

C222C221

C224

R204

J201

J202

C225

C226

C227

R206

PAD

12 25

SG-MLF-7006

U201

AVDD

ENC_B+

ENC_B-

GND

DRVDD

D4B_D2M

D5B_D2P

D6B_D3M

D7B_D3P

DCO_B

DCO_A D0A_D4M

D1A_D4P

D2A_D5M

D3A_D5P

D4A_D6M

D5A_D6P

DRVDD

GND

SCLK_DUT_CMOS_LVDS

SDIO_DUT_PWRDN

CSB_DUT

ENC_A-

ENC_A+

AVDD

AIN_A-

AIN_A+

AVDD

AIN_B+

AIN_B-

AVDD

GND

TRIM

V_N

V_P

GND

Figure 14. DUT and Related Circuits

Table des matières

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