Texas Instruments TMDSEVM6678L Manuel du produit

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TMDSEVM6678LEVM

TechnicalReferenceManual

Version2.01

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LiteratureNumber:SPRUH58

RevisedMarch2012

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DocumentCopyright

PublicationTitle:

TMDSEVM6678LTechnicalReferenceManualAll

RightsReserved.Reproduction,adaptation,or

translationwithoutpriorwrittenpermissionis

prohibited,exceptasallowedundercopyrightlaws.

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EVALUATIONBOARD/KIT/MODULE(EVM)WARNINGS,RESTRICTIONSANDDISCLAIMER

NotforDiagnosticUse:ForFeasibilityEvaluationOnlyinLaboratory/Development

Environments

TheEVMmaynotbeusedfordiagnosticpurposes.

ThisEVMisintendedsolelyforevaluationanddevelopmentpurposes.Itisnotintendedfor

useandmaynotbeusedasall,orpartofanendequipmentproduct.

ThisEVMshouldbeusedsolelybyqualifiedengineersandtechnicianswhoarefamiliarwith

therisksassociatedwithhandlingelectricalandmechanicalcomponents,systemsand

subsystems.

YourObligationsandResponsibilities

PleaseconsulttheEVMdocumentation,includingbutnotlimitedtoanyuserguides,setup

guidesorgettingstartedguides,andotherwarningspriortousingtheEVM.Anyuseofthe

EVMoutsideofthespecifiedoperatingrangemaycausedangertousersand/orproduce

unintendedresults,inaccurateoperation,andpermanentdamagetotheEVMand

associatedelectronics.Youacknowledgeandagreethat:

YouareresponsibleforcompliancewithallapplicableFederal,Stateandlocalregulatory

requirements(includingbutnotlimitedtoFoodandDrugAdministrationregulations,UL,

CSA,VDE,CE,RoHSandWEEE,)thatrelatetoyouruse(andthatofyouremployees,

contractorsordesignees)oftheEVMforevaluation,testingandotherpurposes.

Youareresponsibleforthesafetyofyouandyouremployeesandcontractorswhen

usingorhandlingtheEVM.Further,youareresponsibleforensuringthatanycontacts

orinterfacesbetweentheEVMandanyhumanbodyaredesignedtobesafeandto

avoidtheriskofelectricalshock.

Youwilldefend,indemnifyandholdTI,itslicensorsandtheirrepresentativesharmless

fromandagainstanyandallclaims,damages,losses,expenses,costsandliabilities

(collectively,“Claims”)arisingoutof,orinconnectionwithanyuseoftheEVMthatis

notinaccordancewiththetermsofthisagreement.Thisobligationshallapplywhether

Claimsariseunderthelawoftortorcontractoranyotherlegaltheory,andevenifthe

EVMfailstoperformasdescribedorexpected.

Warning

TheEVMboardmaygetveryhotduringuse.Specifically,theDSP,itsheat

sinkandpowersupplycircuitsallheatupduringoperation.Thiswillnotharm

theEVM.Usecarewhentouchingtheunitwhenoperatingorallowittocool

afterusebeforehandling.Ifunitisoperatedinanenvironmentthatlimits

freeairflow,afanmaybeneeded.

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Preface

AboutthisDocument

ThisdocumentisaTechnicalReferenceManualfortheTMS320C6678EvaluationModule

(TMDSEVM6678L)designedanddevelopedbyAdvantechLimitedforTexasInstruments,Inc.

NotationalConventions

Thisdocumentusesthefollowingconventions:

Programlistings,programexamples,andinteractivedisplaysareshowninamonospaced

font.Examplesuseboldforemphasis,andinteractivedisplaysuseboldtodistinguish

commandsthatyouenterfromitemsthatthesystemdisplays(suchasprompts,command

output,errormessages,etc.).

Squarebrackets([and])identifyanoptionalparameter.Ifyouuseanoptionalparameter,

youspecifytheinformationwithinthebrackets.Unlessthesquarebracketsareinabold

typeface,donotenterthebracketsthemselves.

Underlined,italicizednon‐boldtextinacommandisusedtomarkplaceholdertextthat

shouldbereplacedbytheappropriatevaluefortheuser’sconfiguration.

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Trademarks

TheTexasInstrumentslogoandTexasInstrumentsareregisteredtrademarksofTexas

Instruments.TrademarksofTexasInstrumentsinclude:TI,XDS,CodeComposer,Code

ComposerStudio,ProbePoint,CodeExplorer,DSP/BIOS,RTDX,OnlineDSPLab,TMS320,

TMS320C54x,TMS320C55x,TMS320C62x,TMS320C64x,TMS320C67x,TMS320C5000,and

TMS320C6000.

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MS‐DOS,Windows,WindowsXP,andWindowsNTaretrademarksofMicrosoft

Corporation.

UNIXisaregisteredtrademarkofTheOpenGroupintheUnitedStatesandothercountries.

Allotherbrand,productnames,andservicenamesaretrademarksorregisteredtrademarks

oftheirrespectivecompaniesororganizations.

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DocumentRevisionHistory

Release Chapter DescriptionofChange

1.00All TheFirstRelease fordraft

2.00AllTheSecondReleaseforRev1.0production

2.01AllTheThirdReleaseforRev3.0production

 

Acronyms

Acronym Description

AMCorAdvancedMC AdvancedMezzanineCard

CCS CodeComposerStudio

DDR3DoubleDataRate3Interface

DSP DigitalSignalProcessor

DTE DataTerminalEquipment

EEPROM ElectricallyErasableProgrammableReadOnlyMemory

EMAC EthernetMediaAccessController

EMIF ExternalMemoryInterface

EVM EvaluationModule

FPGA FieldProgrammableGateArray

RFUReservedforFutureUse

I2C InterIntegratedCircuit

IPMB IntelligentPlatformManagementBus

IPMI IntelligentPlatformManagementInterface

JTAG JointTestActionGroup

LED LightEmittingDiode

MCH MicroTCACarrierHub

MTCAorMicroTCA MicroTelecommunicationComputingArchitecture

MMC ModuleManagementController

PICMG® PCIIndustrialComputerManufacturersGroup

PCIEPCIexpress

SDRAM SynchronousDynamicRandomAccessMemory

SERDES Serializer‐Deserializer

SGMII SerialGigabitMediaIndependentInterface

SRIO SerialRapidIO

TSIPTelecomSerialInterfacePort

UART UniversalAsynchronousReceiver/Transmitter

USB UniversalSerialBus

XDS560v2 TexasInstruments’SystemTraceEmulator

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TableofContents

1.Overview..............................................................................................................................11

1.1KeyFeatures...............................................................................................................11

1.2FunctionalOverview..................................................................................................12

1.3BasicOperation..........................................................................................................12

1.4BootModeandBootConfigurationSwitchSetting..................................................13

1.5PowerSupply.............................................................................................................14

2.IntroductiontotheTMDSEVM6678Lboard........................................................................15

2.1MemoryMap.............................................................................................................15

2.2EVMBootModeandBootConfigurationSwitchSettings........................................18

2.3JTAG‐EmulationOverview........................................................................................18

2.4ClockDomains............................................................................................................19

2.5I2CBootEEPROM/SPINORFlash.............................................................................20

2.6FPGA...........................................................................................................................21

2.7GigabitEthernetConnections....................................................................................22

2.8SerialRapidIO(SRIO)Interface..................................................................................22

2.9DDR3ExternalMemoryInterface..............................................................................23

2.1016‐bitAsynchronousExternalMemoryInterface(EMIF‐16)...................................23

2.11HyperLinkInterface..................................................................................................24

2.12PCIeInterface...........................................................................................................25

2.13TelecomSerialInterfacePort(TSIP)........................................................................25

2.14UARTInterface.........................................................................................................26

2.15ModuleManagementController(MMC)forIPMI..................................................26

2.16ExpansionHeader....................................................................................................27

3.TMDSEVM6678LBoardPhysicalSpecifications...................................................................28

3.1BoardLayout..............................................................................................................28

3.2ConnectorIndex.........................................................................................................29

3.2.1560V2_PWR1,XDS560v2MezzaninePowerConnector..............................30

3.2.2AMC1,AMCEdgeConnector.......................................................................30

3.2.3COM1,UART3PinConnector.......................................................................32

3.2.4COM_SEL1,UARTRouteSelectConnector..................................................32

3.2.5DC_IN1,DCPowerInputJackConnector.....................................................33

3.2.6EMU1,TI60‐PinDSPJTAGConnector..........................................................33

3.2.7FAN1,FANConnector...................................................................................34

3.2.8HyperLink1,HyperLinkConnector...............................................................35

3.2.9LAN1,EthernetConnector...........................................................................37

3.2.10PMBUS1,PMBUSConnectorforSmart‐ReflexControl.............................37

3.2.11TAP_FPGA1,FPGAJTAGConnector(ForFactoryUseOnly).......................38

3.2.12SBW_MMC1,MSP430SpyBiWireConnector(ForFactoryUseOnly).......39

3.2.13TEST_PH1,ExpansionHeader(EMIF‐16,SPI,GPIO,TimerI/O,I2C,and

UART).......................................................................................................................39

3.2.14USB1,Mini‐USBConnector........................................................................41

3.3DIPandPushbuttonSwitches....................................................................................41

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3.3.1RST_FULL1,FullReset..................................................................................41

3.3.2RST_COLD1,ColdReset................................................................................42

3.3.3RST_WARM1,WarmReset...........................................................................42

3.3.4SW3,SW4,SW5,andSW6,DSPbootmodeandConfiguration..................42

3.3.4SW9,DSPPCIESSEnableandUserDefinedSwitchConfiguration..............44

3.4TestPoints..................................................................................................................45

3.5SystemLEDs...............................................................................................................47

4.SystemPowerRequirements...............................................................................................48

4.1PowerRequirements.................................................................................................48

4.2ThePowerSupplyDistribution..................................................................................50

4.3ThePowerSupplyBootSequence.............................................................................54

5.TMDSEVM6678LFPGAFUNCTIONALDESCRIPTION............................................................59

5.1FPGAoverview...........................................................................................................59

5.2FPGAsignalsdescription............................................................................................60

5.3Sequenceofoperation...............................................................................................

66

5.3.1Power‐OnSequence........................................................................................67

5.3.2PowerOffSequence........................................................................................67

5.3.3BootConfigurationTiming..............................................................................68

5.3.4BootConfigurationForcedinI2CBoot...........................................................69

5.4Resetdefinition..........................................................................................................69

5.4.1ResetBehavior................................................................................................69

5.4.2ResetSwitchesandTriggers............................................................................70

5.5SPIprotocol................................................................................................................71

5.5.1FPGA‐DSPSPIProtocol....................................................................................71

5.5.2FPGA‐CDCE62005(ClockGenerator)SPIProtocol..........................................73

5.5.3TheFPGA‐programmingCDCE62005fromtheDSP.......................................74

5.5.4CDCE62005programmingsequencesontheFPGA........................................76

5.5.5CDCE62005defaultvalueontheEVM.........................................................77

5.6FPGAConfigurationRegisters....................................................................................78

5.6.1FPGAConfigurationRegistersSummary.........................................................78

5.6.2FPGAConfigurationRegistersDescriptions....................................................79

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8

ListofFigures

Figure1.1:BlockDiagramofTMDSEVM6678LEVM...............................................................12

Figure1.2:TMDSEVM6678LEVMLayout................................................................................13

Figure2.1:TMDSEVM6678LEVMJTAGemulation.................................................................19

Figure2.2:TMDSEVM6678LEVMClockDomains...................................................................20

Figure2.3:TMDSEVM6678LEVMFPGAConnections.............................................................21

Figure2.4:TMDSEVM6678LEVMEthernetRouting...............................................................22

Figure2.5:TMDSEVM6678LEVMSRIOPortConnections......................................................22

Figure2.6:TMDSEVM6678LEVMSDRAM...............................................................................23

Figure2.7:TMDSEVM6678LEVMEMIF‐16connections.........................................................24

Figure2.8:TMDSEVM6678LEVMHyperLinkconnections......................................................24

Figure2.9:TMDSEVM6678LEVMPCIEPortConnections.......................................................25

Figure2.10:TMDSEVM6678LEVMTSIPconnections.............................................................26

Figure2.11:TMDSEVM6678LEVMUARTConnections...........................................................26

Figure2.12:TMDSEVM6678LEVMMMCConnectionsforIPMI.............................................27

Figure3.1:TMDSEVM6678LEVMBoardAssemblyLayout–TOPview..................................28

Figure3.2:TMDSEVM6678LEVMBoardlayout–Bottomview..............................................29

Figure3.3:COM_SEL1Jumpersetting.....................................................................................33

Figure3.4:TheHyperLinkConnector.....................................................................................35

Figure3.5:TAP_FPGA1functiondiagram...............................................................................39

Figure3.6:SW3,SW4,SW5,andSW6defaultsettings..........................................................42

Figure3.7:SW9defaultsettings.............................................................................................44

Figure3.8:TMDSEVM6678Ltestpointsontopside..............................................................45

Figure3.9:TMDSEVM6678Ltestpointsonthebottomside..................................................45

Figure3.10:TMDSEVM6678LEVMBoardLEDs......................................................................47

Figure4.1:AlltheAMCpowersupplyonTMDSEVM6678LEVM............................................51

Figure4.2:TheCVDDandVCC1V0(CVDD1)powerdesignonTMDSEVM6678LEVM...........52

Figure4.3:TheVCC3_AUXpowerdesignonTMDSEVM6678LEVM......................................53

Figure4.4:TheVCC1V5powerdesignonTMDSEVM6678LEVM...........................................53

Figure4.5:TheVCC5powerdesignonTMDSEVM6678LEVM...............................................54

Figure4.6:InitialPowerUpSequenceTimingDiagram..........................................................57

Figure4.7:InitialPowerDownSequenceTimingDiagram.....................................................58

Figure5.1:Power‐OnResetBootConfigurationTiming..........................................................68

9

Figure5.2:Reset‐FullSwitch/TriggerBootConfigurationTiming............................................69

Figure5.3:TheSPIaccessformtheTMS320C6678totheFPGA(WRITE/highlevel)............72

Figure5.4:TheSPIaccessformtheTMS320C6678totheFPGA(WRITE)...............................72

Figure5.5:TheSPIaccessformtheTMS320C6678totheFPGA(READ/highlevel)..............72

Figure5.6:TheSPIaccessformtheTMS320C6678totheFPGA(READ)................................73

Figure5.7:TheSPIaccessformtheFPGAtotheCDCE62005(WRITE)...................................73

Figure5.8:TheSPIaccessformtheFPGAtotheCDCE62005(READ).....................................73



10

ListofTables

Table2.1:TMS320C6678MemoryMap..................................................................................16

Table3.1:TMDSEVM6678LEVMBoardConnectors..............................................................29

Table3.2:XDS560v2PowerConnectorpinout......................................................................30

Table3.3:AMCEdgeConnector...............................................................................................30

Table3.4:UARTConnectorpinout..........................................................................................32

Table3.5:UARTPathSelectConnectorpinout.......................................................................

33

Table3.6:DSPJTAGConnectorpinout....................................................................................34

Table3.7:FAN1Connectorpinout.........................................................................................35

Table3.8:TheHyperLinkConnector.......................................................................................36

Table3.9:EthernetConnectorpinout....................................................................................37

Table3.10:PMBUS1pinout...................................................................................................38

Table3.11:FPGAJTAGConnectorpinout..............................................................................38

Table3.12:MSP430JTAGConnectorpinout..........................................................................39

Table3.13:ExpansionHeaderpinout....................................................................................40

Table3.14:Mini‐USBConnectorpinout.................................................................................41

Table3.15:TMDSEVM6678LEVMBoardSwitches.................................................................41

Table3.16:SW3‐SW6,DSPConfigurationSwitch...................................................................

43

Table3.17:SW9,DSPPCIExpressEnableandUserSwitch.....................................................44

Table3.18:TMDSEVM6678LEVMBoardTestPoints.............................................................46

Table3.19:TMDSEVM6678LTEEVMBoardLEDs.....................................................................47

Table4.1:EVMVoltageTable..................................................................................................49

Table4.2:EachCurrentRequirementsoneachdeviceofEVMboard...................................50

Table4.3:Thepower‐upanddowntimingontheTMDSEVM6678L......................................56

Table5.1:TMDSEVM6678LEVMFPGAPinDescription..........................................................60

Table5.2:CLK2,CDCE62005Registerconfigurations..............................................................77

Table5.3:CLK3,CDCE62005Registerconfigurations..............................................................77

Table5.4:TMS320C6678EVMFPGAMemoryMap...............................................................78

Table5.7:FPGAConfigurationRegistersSummary................................................................78



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