Texas Instruments TMS570LS0714 Manuel utilisateur

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS570LS0714

SPNS226E –JUNE 2013–REVISED NOVEMBER 2016

TMS570LS0714 16- and 32-Bit RISC Flash Microcontroller

1 Device Overview

1.1 Features

• High-Performance Automotive-Grade

Microcontroller (MCU) for Safety-Critical

Applications

– Dual CPUs Running in Lockstep

– ECC on Flash and RAM Interfaces

– Built-In Self-Test (BIST) for CPU and On-chip

RAMs

– Error Signaling Module With Error Pin

– Voltage and Clock Monitoring

• ARM®Cortex®-R4F 32-Bit RISC CPU

– 1.66 DMIPS/MHz With 8-Stage Pipeline

– FPU With Single and Double Precision

– 12-Region Memory Protection Unit (MPU)

– Open Architecture With Third-Party Support

• Operating Conditions

– Up to 160-MHz System Clock

– Core Supply Voltage (VCC): 1.14 to 1.32 V

– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V

• Integrated Memory

– 768KB of Flash With ECC

– 128KB of RAM With ECC

– 64KB of Flash for Emulated EEPROM With

ECC

• Common Platform Architecture

– Consistent Memory Map Across Family

– Real-Time Interrupt Timer (RTI) OS Timer

– 128-Channel Vectored Interrupt Module (VIM)

– 2-Channel Cyclic Redundancy Checker (CRC)

• Direct Memory Access (DMA) Controller

– 16 Channels and 32 Peripheral Requests

– Parity for Control Packet RAM

– DMA Accesses Protected by Dedicated MPU

• Frequency-Modulated Phase-Locked Loop

(FMPLL) With Built-In Slip Detector

• IEEE 1149.1 JTAG, Boundary Scan and ARM

CoreSight™ Components

• Advanced JTAG Security Module (AJSM)

• Up to 64 General-Purpose I/O (GIO) Pins

– Up to 16 GIO Pins With Interrupt Generation

Capability

• Enhanced Timing Peripherals

– 7 Enhanced Pulse Width Modulator (ePWM)

Modules

– 6 Enhanced Capture (eCAP) Modules

– 2 Enhanced Quadrature Encoder Pulse (eQEP)

Modules

• Two Next Generation High-End Timer (N2HET)

Modules

– N2HET1: 32 Programmable Channels

– N2HET2: 18 Programmable Channels

– 160-Word Instruction RAM With Parity

Protection Each

– Each N2HET Includes Hardware Angle

Generator

– Dedicated High-End Timer Transfer Unit (HTU)

for Each N2HET

• Two 12-Bit Multibuffered ADC Modules

– ADC1: 24 Channels

– ADC2: 16 Channels

– 16 Shared Channels

– 64 Result Buffers With Parity Protection Each

• Multiple Communication Interfaces

– Up to Three CAN Controllers (DCANs)

– 64 Mailboxes With Parity Protection Each

– Compliant to CAN Protocol Version 2.0A and

2.0B

– Inter-Integrated Circuit (I2C)

– 3 Multibuffered Serial Peripheral Interfaces

(MibSPIs)

– 128 Words With Parity Protection Each

– 8 Transfer Groups

– One Standard Serial Peripheral Interface (SPI)

Module

– Two UART (SCI) Interfaces, One With Local

Interconnect Network (LIN 2.1) Interface

Support

• Packages

– 144-Pin Quad Flatpack (PGE) [Green]

– 100-Pin Quad Flatpack (PZ) [Green]

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1.2 Applications

• Electric Power Steering (EPS)

• Braking Systems (ABS and ESC)

• HEV and EV Inverter Systems

• Battery-Management Systems

• Active Driver Assistance Systems

• Aerospace and Avionics

• Railway Communications

• Off-road Vehicles

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1.3 Description

The TMS570LS0714 device is part of the Hercules TMS570 series of high-performance automotive-grade

ARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and software are available to

assist in the development of ISO 26262 and IEC 61508 functional safety applications. Start evaluating

today with the Hercules TMS570 LaunchPad Development Kit. The TMS570LS0714 device has on-chip

diagnostic features including: dual CPUs in lockstep; CPU and memory Built-In Self-Test (BIST) logic;

ECC on both the flash and the SRAM; parity on peripheral memories; and loopback capability on most

peripheral I/Os.

The TMS570LS0714 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient

1.66 DMIPS/MHz, and has configurations which can run up to 160 MHz providing up to 265 DMIPS. The

TMS570 device supports the word invariant big-endian [BE32] format.

The TMS570LS0714 device has 768KB of integrated flash and 128KB of RAM configurations with single-

bit error correction and double-bit error detection. The flash memory on this device is nonvolatile,

electrically erasable and programmable, and is implemented with a 64-bit-wide data bus interface. The

flash operates on a 3.3-V supply input (same level as the I/O supply) for all read, program, and erase

operations. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and

doubleword modes throughout the supported frequency range.

The TMS570LS0714 device features peripherals for real-time control-based applications, including two

Next-Generation High-End Timer (N2HET) timing coprocessors with up to 44 total I/O terminals, seven

Enhanced PWM (ePWM) modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, two

Enhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bit Analog-to-Digital Converters

(ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,

capture or compare inputs, or general-purpose I/O (GIO). The N2HET is especially well suited for

applications requiring multiple sensor information and drive actuators with complex and accurate time

pulses. A High-End Timer Transfer Unit (HTU) can transfer N2HET data to or from main memory. A

Memory Protection Unit (MPU) is built into the HTU.

The ePWM module can generate complex pulse width waveforms with minimal CPU overhead or

intervention. The ePWM is easy to use and supports complementary PWMs and deadband generation.

With integrated trip zone protection and synchronization with the on-chip MibADC, the ePWM is ideal for

digital motor control applications.

The eCAP module is essential in systems where the accurately timed capture of external events is

important. The eCAP can also be used to monitor the ePWM outputs or to generate simple PWM when

not needed for capture applications.

The eQEP module is used for direct interface with a linear or rotary incremental encoder to get position,

direction, and speed information from a rotating machine as used in high-performance motion and

position-control systems.

The device has two 12-bit-resolution MibADCs with 24 total inputs and 64 words of parity-protected buffer

RAM each. The MibADC channels can be converted individually or can be grouped by software for

sequential conversion sequences. Sixteen inputs are shared between the two MibADCs. There are three

separate groups. Each group can be converted once when triggered or configured for continuous

conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster

conversion time is desired.

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The device has multiple communication interfaces: three MibSPIs; two SPIs; two SCIs, one of which can

be used as LIN; up to three DCANs; and one I2C module. The SPI provides a convenient method of serial

interaction for high-speed communications between similar shift-register type devices. The LIN supports

the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard

Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial,

multimaster communication protocol that efficiently supports distributed real-time control with robust

communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh

environments (for example, automotive and industrial fields) that require reliable serial communication or

multiplexed wiring.

The I2C module is a multimaster communication module providing an interface between the

microcontroller and an I2C-compatible device through the I2C serial bus. The I2C module supports speeds

of 100 and 400 kbps.

A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external

frequency reference to a higher frequency for internal use. The FMPLL provides one of the six possible

clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the

available clock sources and the device clock domains.

The device also has an external clock prescaler (ECP) circuit that when enabled, outputs a continuous

external clock on the ECLK terminal. The ECLK frequency is a user-programmable ratio of the peripheral

interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of

the device operating frequency.

The Direct Memory Access (DMA) controller has 16 channels, 32 peripheral requests,

and parity protection on its memory. An MPU is built into the DMA to protect memory against erroneous

transfers.

The Error Signaling Module (ESM) monitors device errors and determines whether an interrupt or external

error signal (nERROR) is asserted when a fault is detected. The nERROR terminal can be monitored

externally as an indicator of a fault condition in the microcontroller.

With integrated functional safety features and a wide choice of communication and control peripherals, the

TMS570LS0714 device is an ideal solution for high-performance, real-time control applications with safety-

critical requirements.

(1) For more information, see Section 10,Mechanical Packaging and Orderable Information.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE

TMS570LS0714PGE LQFP (144) 20.0 mm × 20.0 mm

TMS570LS0714PZ LQFP (100) 14.0 mm × 14.0 mm

HTU1 HTU2

Switched Central Resource

Main Cross Bar: Arbitration and Prioritization Control

CRC Peripheral Central Resource Bridge

Dual Cortex-R4F

CPUs in Lockstep Switched Central Resource

DCAN1

DCAN2

DCAN3

LIN

SCI

SPI4

64KB Flash

for EEPROM

Emulation

with ECC

MibSPI1

CAN1_RX

CAN1_TX

CAN2_RX

CAN2_TX

CAN3_RX

CAN3_TX

MIBSPI1_CLK

MIBSPI1_SIMO[1:0]

MIBSPI1_SOMI[1:0]

MIBSPI1_nCS[5:0]

MIBSPI1_nENA

SPI2

SPI2_CLK

SPI2_SIMO

SPI2_SOMI

SPI2_nCS[1:0]

SPI2_nENA

MibSPI3

MIBSPI3_CLK

MIBSPI3_SIMO

MIBSPI3_SOMI

MIBSPI3_nCS[5:0]

MIBSPI3_nENA

SPI4_CLK

SPI4_SIMO

SPI4_SOMI

SPI4_nCS0

SPI4_nENA

MibSPI5

MIBSPI5_SIMO[3:0]

MIBSPI5_SOMI[3:0]

MIBSPI5_nCS[3:0]

MIBSPI5_nENA

LIN_RX

LIN_TX

SCI_RX

SCI_TX

IOMM

PMM

VIM

RTI

DCC1

DCC2

32K

128KB

with ECC

RAM

DMA

# 2

# 3

# 5

# 1

always on

Core/RAM RAM

Core

Color Legend for Power Domains

SYS nPORRST

nRST

ECLK

ESM nERROR

768KB

Flash

with

ECC

Switched Central Resource

I2C

N2HET1 GIO

I2C_SCL

I2C_SDA

GIOB[7:0]

GIOA[7:0]

N2HET2[18,16]

N2HET2[15:0]

N2HET1[31:0]

N2HET1_PIN_nDIS

N2HET2_PIN_nDIS

N2HET2

MibADC1 MibADC2

AD1EVT

AD1IN[7:0]

AD2EVT

VSSAD

VCCAD

ADREFHI

ADREFLO

AD1IN[15:8] \

AD2IN[15:8]

AD1IN[23:16] \

AD2IN[7:0]

eQEP

1,2

eQEPxA

eQEPxB

eQEPxS

eQEPxI

eCAP

1..6 eCAP[6:1]

ePWM

1..7

nTZ[3:1]

SYNCO

SYNCI

ePWMxA

ePWMxB

32K

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1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

NOTE: The block diagram reflects the 144PGE package. Some functions are multiplexed or not available

in other packages. For details, see the respective terminal functions table in Section 4.2,Terminal

Functions.

Figure 1-1. Functional Block Diagram

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Table of Contents

1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 2

1.3 Description............................................ 3

1.4 Functional Block Diagram ............................ 5

2 Revision History ......................................... 7

3 Device Comparison ..................................... 8

3.1 Related Products ..................................... 8

4 Terminal Configuration and Functions.............. 9

4.1 Pin Diagrams ......................................... 9

4.2 Signal Descriptions ................................. 11

4.3 Pin Multiplexing...................................... 29

4.4 Buffer Type.......................................... 35

5 Specifications .......................................... 36

5.1 Absolute Maximum Ratings......................... 36

5.2 ESD Ratings ........................................ 36

5.3 Power-On Hours (POH)............................. 36

5.4 Recommended Operating Conditions............... 37

5.5 Input/Output Electrical Characteristics Over

Recommended Operating Conditions............... 38

5.6 Power Consumption Over Recommended

Operating Conditions................................ 39

5.7 Thermal Resistance Characteristics ................ 40

5.8 Timing and Switching Characteristics............... 41

6 System Information and Electrical

Specifications........................................... 43

6.1 Device Power Domains ............................. 43

6.2 Voltage Monitor Characteristics..................... 43

6.3 Power Sequencing and Power-On Reset........... 44

6.4 Warm Reset (nRST)................................. 46

6.5 ARM Cortex-R4F CPU Information ................. 47

6.6 Clocks ............................................... 51

6.7 Clock Monitoring .................................... 58

6.8 Glitch Filters......................................... 60

6.9 Device Memory Map ................................ 61

6.10 Flash Memory ....................................... 66

6.11 Tightly Coupled RAM Interface Module............. 69

6.12 Parity Protection for Accesses to Peripheral RAMs 69

6.13 On-Chip SRAM Initialization and Testing ........... 71

6.14 Vectored Interrupt Manager......................... 73

6.15 DMA Controller...................................... 76

6.16 Real-Time Interrupt Module ......................... 78

6.17 Error Signaling Module.............................. 80

6.18 Reset/Abort/Error Sources.......................... 84

6.19 Digital Windowed Watchdog ........................ 87

6.20 Debug Subsystem................................... 88

7 Peripheral Information and Electrical

Specifications........................................... 93

7.1 I/O Timings ......................................... 93

7.2 Enhanced PWM Modules (ePWM).................. 96

7.3 Enhanced Capture Modules (eCAP)............... 102

7.4 Enhanced Quadrature Encoder (eQEP) ........... 105

7.5 12-Bit Multibuffered Analog-to-Digital Converter

(MibADC)........................................... 108

7.6 General-Purpose Input/Output..................... 121

7.7 Enhanced High-End Timer (N2HET) .............. 122

7.8 Controller Area Network (DCAN) .................. 126

7.9 Local Interconnect Network Interface (LIN)........ 127

7.10 Serial Communication Interface (SCI) ............. 128

7.11 Inter-Integrated Circuit (I2C) Module .............. 129

7.12 Multibuffered / Standard Serial Peripheral

Interface............................................ 132

8 Applications, Implementation, and Layout...... 144

8.1 TI Designs or Reference Designs ................. 144

9 Device and Documentation Support.............. 145

9.1 Getting Started and Next Steps ................... 145

9.2 Device and Development-Support Tool

Nomenclature ...................................... 145

9.3 Tools and Software ................................ 147

9.4 Documentation Support............................ 149

9.5 Community Resources............................. 149

9.6 Trademarks ........................................ 149

9.7 Electrostatic Discharge Caution ................... 150

9.8 Glossary............................................ 150

9.9 Device Identification................................ 151

9.10 Module Certifications............................... 152

10 Mechanical Packaging and Orderable

Information............................................. 157

10.1 Packaging Information ............................. 157

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the SPNS226D device-specific

data manual to make it an SPNS226E revision.

Scope: Applicable updates to the TMS570LS0714 device family, specifically relating to the

TMS570LS0714 devices (Silicon Revision A), which are now in the production data (PD) stage of

development have been incorporated.

Changes from September 15, 2015 to November 1, 2016 (from D Revision (September 2015) to E Revision) Page

• GLOBAL: PZ package is now fully qualified ...................................................................................... 1

•Section 1.1 (Features): Updated/Changed the GIO pin count in GIO bullet.................................................. 1

•Section 1.1: Updated/Changed the SPI features bullet.......................................................................... 1

•Section 3.1 (Related Products): Added new section. ............................................................................ 8

•Section 4.2 (Signal Descriptions): Updated/Changed reference to Technical Reference Manual ....................... 11

•Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET)): Added a description for pins 14 and 55

(N2HET1_PIN_nDIS and N2HET2_PIN_nDIS, respectively).................................................................. 13

•Table 4-20 (PZ Enhanced High-End Timer Modules (N2HET)): Added Pin 10, GIOA[5] / INT[5] / EXTCLKIN

/EPWM1A/N2HET1_PIN_nDIS.................................................................................................... 22

•Table 6-20 (Device Memory Map): Updated/Changed the FRAME SIZE column value for "Flash Data Space

ECC" under Flash Module Bus2 Interface from "768KB" to "1MB"........................................................... 62

•Section 6.19 (Digital Windowed Watchdog): Added Figure 6-13,Digital Windowed Watchdog Example............... 87

•Table 7-11 (eCAPx Clock Enable Control): Updated/Changed "ePWM" to "eCAP" in MODULE INSTANCE

column............................................................................................................................... 103

•Table 7-15 (eQEPx Clock Enable Control): Updated/Changed "ePWM" to "eQEP" in MODULE INSTANCE

column............................................................................................................................... 106

•Table 7-20 (MibADC1 Trigger Event Hookup): Added lead-in paragraph referencing the table ........................ 108

•Table 7-21 (MibADC2 Event Trigger Hookup): Added lead-in paragraph referencing the table ........................ 110

•Figure 7-11 (ePWM1SOC1A Switch Implementation): Added missing ePWM1 SOC1A detailed switch

connection example and lead-in reference sentence......................................................................... 114

•Section 9.1 (Getting Started and Next Steps): Added new section......................................................... 145

•Section 9.2 (Device and Development-Support Tool Nomenclature): Moved subsection after "Getting Started

and Next Steps" subsection (new) .............................................................................................. 145

•Section 9.9.1 Added the address of the Device ID register. ................................................................. 151

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(1) Bolding denotes a superset device. For additional device variants, see www.ti.com/tms570

3 Device Comparison

Table 3-1 lists the features of the TMS570LS0714 devices.

Table 3-1. TMS570LS0714 Device Comparison

FEATURES TMS570LS DEVICES

Generic Part Number 3137ZWT(1) 1227ZWT(1) 0914PGE(1) 0714PGE 0714PZ 0432PZ

Package 337 BGA 337 BGA 144 QFP 144 QFP 100 QFP 100 QFP

CPU ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4

Frequency (MHz) 180 180 160 160 100 80

Flash (KB) 3072 1280 1024 768 768 384

RAM (KB) 256 192 128 128 128 32

Data Flash [EEPROM]

(KB) 64 64 64 64 64 16

EMAC 10/100 10/100 – – – –

FlexRay 2-ch 2-ch – – – –

CAN 333322

MibADC

12-bit (Ch) 2 x (24ch) 2 x (24ch) 2 x (24ch) 2 x (24ch) 2 x (16ch) 1 x (16ch)

N2HET (Ch) 2 (44) 2 (44) 2 (40) 2 (40) 2 (21) 1 (19)

ePWM Channels – 14 14 14 8 –

eCAP Channels – 6 6 6 4 0

eQEP Channels – 2 2 2 1 2

MibSPI (CS) 3 (6 + 6 + 4) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (5 + 6 + 4) 2 (5 + 1) 1 (4)

SPI (CS) 2 (2 + 1) 2 (2 + 1) 1 (1) 1 (1) 1 (1) 2

SCI (LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 1 (with LIN) 1 (with LIN)

I2C 1111––

GPIO (INT) 120 (with 16 interrupt

capable) 101 (with 16 interrupt

capable) 64 (with 10 interrupt

capable) 45 (with 9 interrupt

capable) 45 (with 8 interrupt

capable)

EMIF 16-bit data 16-bit data – – – –

ETM (Trace) 32-bit – – – – –

RTP/DMM YES – – – – –

Operating

Temperature -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC

Core Supply (V) 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V

I/O Supply (V) 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TMS570 16-Bit and 32-Bit MCUs

An expansive portfolio of software and pin-compatible high-performance ARM®Cortex®-R-based MCU

products from 80 MHz up to 300 MHz with on-chip features that prove a high level of diagnostic coverage,

as well as provide scalability to address a wide range of applications.

Companion Products for TMS570LS0714

Review products that are frequently purchased or used with this product.

1108

GIOA[1]

nTRST 109

144

110

111

112

113

114

115

116

117

118

119

120

121

AD1IN[10] / AD2IN[10]

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

2323

2727

107

106

105

104

103

102

101

100

GIOB[3]

GIOA[0]

MIBSPI3NCS[3]

MIBSPI3NCS[2]

N2HET1[11]

FLTP1

FLTP2

GIOA[2]

VCCIO

VSS

CAN3RX

CAN3TX

GIOA[5]

N2HET1[22]

GIOA[6]

VCC

OSCIN

Kelvin_GND

OSCOUT

VSS

GIOA[7]

N2HET1[01]

N2HET1[03]

N2HET1[0]

VCCIO

VSS

VCC

N2HET1[02]

N2HET1[05]

MIBSPI5NCS[0]

N2HET1[07]

TEST

N2HET1[09]

N2HET1[4]

MIBSPI3NCS[1]

N2HET1[06]

N2HET1[13]

MIBSPI1NCS[2]

N2HET1[15]

VCCIO

VSS

VCC

nPORRST

VSS

VCC

VSS

MIBSPI3SOMI

MIBSPI3SIMO

MIBSPI3CLK

MIBSPI3NENA

MIBSPI3NCS[0]

VSS

VCC

AD1IN[16] / AD2IN[0]

AD1IN[17] / AD2IN[01]

AD1IN[0]

AD1IN[07]

AD1IN[18] / AD2IN[02]

AD1IN[19] / AD2IN[03]

AD1IN[20] / AD2IN[04]

AD1IN[21] / AD2IN[05]

ADREFHI

ADREFLO

VSSAD

VCCAD

AD1IN[09] / AD2IN[09]

AD1IN[01]

AD1IN[02]

AD1IN[03]

AD1IN[11] / AD2IN[11]

AD1IN[04]

AD1IN[12] / AD2IN[12]

AD1IN[05]

AD1IN[13] / AD2IN[13]

AD1IN[06]

AD1IN[22] / AD2IN[06]

AD1IN[14] / AD2IN[14]

AD1IN[08] / AD2IN[08]

AD1IN[23] / AD2IN[07]

AD1IN[15] / AD2IN[15]

AD1EVT

VCC

VSS

CAN1TX

CAN1RX

N2HET1[24]

N2HET1[26]

MIBSPI1SIMO

MIBSPI1SOMI

MIBSPI1CLK

MIBSPI1NENA

MIBSPI5NENA

MIBSPI5SOMI[0]

MIBSPI5SIMO[0]

MIBSPI5CLK

VCC

VSS

VCCIO

N2HET1[08]

N2HET1[28]

TMS

TDI

TDO

TCK

RTCK

VCC

VSS

nRST

nERROR

N2HET1[10]

ECLK

VCCIO

VSS

VCC

N2HET1[12]

N2HET1[14]

GIOB[0]

N2HET1[30]

CAN2TX

CAN2RX

MIBSPI1NCS[1]

LINRX

LINTX

GIOB[1]

VCCP

VSS

VCCIO

VCC

VSS

N2HET1[16]

N2HET1[18]

N2HET1[20]

GIOB[2]

VCC

VSS

MIBSPI1NCS[0]

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4 Terminal Configuration and Functions

4.1 Pin Diagrams

4.1.1 PGE QFP Package Pinout (144-Pin)

A. Pins can have multiplexed functions. Only the default function is shown in Figure 4-1.

Figure 4-1. PGE QFP Package Pinout (144-Pin)

MIBSPI1nCS[1]

VCCP

LINRX

VCCIO

ECLK

RTCK

N2HET1[6]

MIBSPI1nCS[2]

VCCIO

VSS

VCC

nPORRST

VCC

VSS

MIBSPI3nENA

AD1IN[21]

TCK

MIBSPI3nCS[0]

MIBSPI1nCS[3]

AD1IN[0]

AD1IN[7]

AD1IN[20]

VSSAD/ADREFLO

AD1IN[9]

VCCAD/ADREFHI

AD1IN[1]

AD1IN[10]

VSS

VCC

CAN2RX

CAN2TX

VCC

VSS

nERROR

nRST

TDO

TDI

nTRST

VSS

LINTX

MIBSPI3CLK

ADEVT

VSS

CAN1TX

CAN1RX

MIBSPI1SOMI

MIBSPI1C LK

MIBSPI1nENA

SPI2SOMI

SPI2SIMO

SPI2CLK

MIBSPI1nCS

TMS

VCC

MIBSPI1SIMO

VCCIO

GIOA[3]/INT[3]

VSS

VCCIO

GIOA[1]/IN T[1]

TEST

GIOA[7]/IN T[7]

VSS

KELVIN_GN D

OSCIN

VC C

GIOA[6]/INT[6]

GIOA[5]/INT[5]

GIOA[2]/INT[2]

FLTP2

FLTP1

GIOA[0]/IN T[0]

GIOA[4]/INT[4]

OSCOUT

100

VSS

VC C

VSS

MIBSPI3SOMI

MIBSPI3SIMO

AD1IN[16]

AD1IN[17]

N2HET1[4]

N2HET1[2]

N2HET1[0]

N2HET1[22]

N2HET1[24]

N2HET1[10]

N2HET1[8]

N2HET1[14]

N2HET1[12]

N2HET1[16]

N2HET1[18]

SPI2nCS[0]

AD1IN[2]

AD1IN[3]

AD1IN[11]

AD1IN[8]

AD1IN[6]

AD1IN[4]

AD1IN[5]

TMS570LS0714

SPNS226E –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: TMS570LS0714

4.1.2 PZ QFP Package Pinout (100-Pin)

Figure 4-2. PZ QFP Package Pinout (100-Pin)

Table des matières

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