Texas Instruments TMS320C6711D Manuel utilisateur

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DExcellent-Price/Performance Floating-Point

Digital Signal Processor (DSP):

TMS320C6711D

− Eight 32-Bit Instructions/Cycle

− 167-, 200-, 250-MHz Clock Rates

− 6-, 5-, 4-ns Instruction Cycle Time

− 1000, 1200, 1500 MFLOPS

DAdvanced Very Long Instruction Word

(VLIW) C67xDSP Core

− Eight Highly Independent Functional

Units:

− Four ALUs (Floating- and Fixed-Point)

− Two ALUs (Fixed-Point)

− Two Multipliers (Floating- and

Fixed-Point)

− Load-Store Architecture With 32 32-Bit

General-Purpose Registers

− Instruction Packing Reduces Code Size

− All Instructions Conditional

DInstruction Set Features

− Hardware Support for IEEE

Single-Precision and Double-Precision

Instructions

− Byte-Addressable (8-, 16-, 32-Bit Data)

− 8-Bit Overflow Protection

− Saturation

− Bit-Field Extract, Set, Clear

− Bit-Counting

− Normalization

DL1/L2 Memory Architecture

− 32K-Bit (4K-Byte) L1P Program Cache

(Direct Mapped)

− 32K-Bit (4K-Byte) L1D Data Cache

(2-Way Set-Associative)

− 512K-Bit (64K-Byte) L2 Unified Mapped

RAM/Cache

(Flexible Data/Program Allocation)

DDevice Configuration

− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot

− Endianness: Little Endian, Big Endian

DEnhanced Direct-Memory-Access (EDMA)

Controller (16 Independent Channels)

D32-Bit External Memory Interface (EMIF)

− Glueless Interface to Asynchronous

Memories: SRAM and EPROM

− Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

− 256M-Byte Total Addressable External

Memory Space

D16-Bit Host-Port Interface (HPI)

DTwo Multichannel Buffered Serial Ports

(McBSPs)

− Direct Interface to T1/E1, MVIP, SCSA

Framers

− ST-Bus-Switching Compatible

− Up to 256 Channels Each

− AC97-Compatible

− Serial-Peripheral-Interface (SPI)

Compatible (Motorola)

DTwo 32-Bit General-Purpose Timers

DFlexible Software Configurable PLL-Based

Clock Generator Module

DA Dedicated General-Purpose Input/Output

(GPIO) Module With 5 Pins

DIEEE-1149.1 (JTAG†)

Boundary-Scan-Compatible

D272-Pin Ball Grid Array (BGA) Package

(GDP and ZDP Suffixes)

DCMOS Technology

− 0.13-µm/6-Level Copper Metal Process

D3.3-V I/O, 1.4-V Internal (−250)

D3.3-V I/O, 1.20-V Internal ‡

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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TMS320C67x and C67x are trademarks of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

All trademarks are the property of their respective owners.

†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

‡These values are compatible with existing 1.26V designs.

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Table of Contents

EMIF big endian mode correctness 60. . . . . . . . . . . . . . . .

bootmode 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

reset 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

absolute maximum ratings over operating case

temperature range 62. . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions 62. . . . . . . . . . . . . . . .

electrical characteristics over recommended ranges of

supply voltage and operating case temperature 63.

parameter measurement information 64. . . . . . . . . . . . . . .

signal transition levels 64. . . . . . . . . . . . . . . . . . . . . . . . . .

timing parameters and board routing analysis 66. . . . . .

input and output clocks 68. . . . . . . . . . . . . . . . . . . . . . . . . . .

asynchronous memory timing 71. . . . . . . . . . . . . . . . . . . . .

synchronous-burst memory timing 74. . . . . . . . . . . . . . . . .

synchronous DRAM timing 76. . . . . . . . . . . . . . . . . . . . . . . .

HOLD/HOLDA timing 82. . . . . . . . . . . . . . . . . . . . . . . . . . . .

BUSREQ timing 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

reset timing 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

external interrupt timing 86. . . . . . . . . . . . . . . . . . . . . . . . . .

host-port interface timing 87. . . . . . . . . . . . . . . . . . . . . . . . .

multichannel buffered serial port timing 91. . . . . . . . . . . . .

timer timing 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

general-purpose input/output (GPIO) port timing 101. . . .

JTAG test-port timing 102. . . . . . . . . . . . . . . . . . . . . . . . . . .

mechanical data 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

revision history 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GDP and ZDP BGA packages (bottom view) 4. . . . . . . . . . . .

description 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

device characteristics 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

device compatibility 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

functional block and CPU (DSP core) diagram 8. . . . . . . . . . .

CPU (DSP core) description 9. . . . . . . . . . . . . . . . . . . . . . . . . .

memory map summary 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

peripheral register descriptions 12. . . . . . . . . . . . . . . . . . . . . . .

signal groups description 17. . . . . . . . . . . . . . . . . . . . . . . . . . . .

device configurations 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

terminal functions 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

development support 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

device support 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CPU CSR register description 40. . . . . . . . . . . . . . . . . . . . . . . .

cache configuration (CCFG) register description 42. . . . . . . .

interrupt sources and interrupt selector 43. . . . . . . . . . . . . . . .

EDMA module and EDMA selector 44. . . . . . . . . . . . . . . . . . . .

PLL and PLL controller 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

general-purpose input/output (GPIO) 53. . . . . . . . . . . . . . . . . .

power-down mode logic 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

power-supply sequencing 56. . . . . . . . . . . . . . . . . . . . . . . . . . . .

power-supply decoupling 58. . . . . . . . . . . . . . . . . . . . . . . . . . . .

IEEE 1149.1 JTAG compatibility statement 58. . . . . . . . . . . . .

EMIF device speed 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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REVISION HISTORY

The TMS320C6711D device-specific documentation has been split from TMS320C6711, TMS320C6711B,

TMS320C6711C, TMS320C6711D Floating−Point Digital Signal Processors, literature number SPRS088N, into a

separate Data Sheet, literature number SPRS292. It also highlights technical changes made to SPRS292 to gen-

erate SPRS292A; these changes are marked by “[Revision A]” in the Revision History table below.

Scope: Updated information on McBSP and JTAG for clarification. Changed Pin Description for A12 and B11

(Revisions SPRS292 and SPRS292A). Updated Nomenclature figure by adding device−specific information for

the ZDP package. Updated Characteristics of the Processor table with device−specific information (footnote) for

the ZDP package

TI Recommends for new designs that the following pins be configured as such:

DPin A12 connected directly to CVDD (core power)

DPin B11 connected directly to Vss (ground)

PAGE(S)

NO. ADDITIONS/CHANGES/DELETIONS

21 Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section:

Removed “CE1 width 32−bit” from Functional Description for “00” in HD[4:3](BOOTMODE) Configuration Pin

25 Terminal Functions, Resets and Interrupts section:

Updated IPU/IPD for RESET Signal Name from “IPU” to “−−”

26 Terminal Functions, Host Port Interface section:

Removed “CE1 width 32−bit” from Description for “00” in Bootmode HD[4:3]

31 Terminal Functions, Reserved for Test section:

Updated Description for RSV Signal Name, A12 GDP/ZDP

Updated Description for RSV Signal Name, B11 GDP/ZDP

31 Terminal Functions, Reserved for Test section:

Updated/changed Description for RSV Signal Name, A12 GDP (to “recommended”) − [Revision A]

Updated/changed Description for RSV Signal Name, B11 GDP (to “recommended”) − [Revision A]

38 Device Support, device and development-support tool nomenclature:

Updated figure for clarity

39 Device Support, documentation support section:

Updated paragraphs for clarity

58 IEEE 1149.1 JTAG Compatibility Statement section:

Updated/added paragraphs for clarity

62 Recommended Operating Conditions:

Added VOS, Maximum voltage during overshoot row and associated footnote

Added VUS, Maximum voltage during undershoot row and associated footnote

65 Parameter Measurement Information:

AC transient rise/fall time specifications section:

Added AC Transient Specification Rise Time figure

Added AC Transient Specification Fall Time figure

93 MULTICHANNEL BUFFERED SERIAL PORT TIMING:

switching characteristics over recommended operating conditions for McBSP section:

Updated McBSP Timings figure for clarification

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GDP and ZDP BGA packages (bottom view)

GDP and ZDP 272-PIN BALL GRID ARRAY (BGA) PACKAGES†

(BOTTOM VIEW)

2468 201816141210

357911 171513 19

†The ZDP mechanical package designator represents the version of the GDP package with lead−free balls. For more detailed information, see

the Mechanical Data section of this document.

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description

The TMS320C67xDSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D

devices†) compose the floating-point DSP family in the TMS320C6000DSP platform. The C6711, C6711B,

C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word

(VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for

multichannel and multifunction applications.

With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of

200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz, the C6711D device also offers cost-effective

solutions to high-performance DSP programming challenges. The C6711D DSP possesses the operational

flexibility of high-speed controllers and the numerical capability of array processors. This processor has

32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight

functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point

multipliers. The C6711D can produce two MACs per cycle for a total of 400 MMACS.

The C6711D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip

peripherals.

The C6711D device uses a two-level cache-based architecture and has a powerful and diverse set of

peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache

(L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory

space that is shared between program and data space. L2 memory can be configured as mapped memory,

cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs),

two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF)

capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6711D has a complete set of development tools which includes: a new C compiler, an assembly optimizer

to simplify programming and scheduling, and a Windowsdebugger interface for visibility into source code

execution.

TMS320C6000 is a trademark of Texas Instruments.

Windows is a registered trademark of the Microsoft Corporation.

†Throughout the remainder of this document, the TMS320C6711D shall be referred to as its individual full device part number or abbreviated

as C6711D or 11D.

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device characteristics

Table 1 provides an overview of the C6711D DSP. The table shows significant features of the device, including

the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more

details on the C6000DSP device part numbers and part numbering, see Figure 5.

Table 1. Characteristics of the C6711D Processor

HARDWARE FEATURES INTERNAL CLOCK

SOURCE C6711D

FLOATING-POINT DSP

EMIF

ECLKIN

EMIF SYSCLK3 or ECLKIN 1

EDMA CPU clock frequency 1

HPI

CPU/2 clock frequency

Peripherals

HPI SYSCLK2 1

Peripherals

McBSPs

CPU/2 clock frequency

McBSPs SYSCLK2 2

32-Bit Timers

CPU/4 clock frequency —

32-Bit Timers 1/2 of SYSCLK2 2

GPIO Module SYSCLK2 1

Size (Bytes) 72K

On-Chip Memory Organization

4K-Byte (4KB) L1 Program

(L1P) Cache

4KB L1 Data (L1D) Cache

64KB Unified Mapped

RAM/Cache (L2)

CPU ID+

CPU Rev ID Control Status Register (CSR.[31:16]) 0x0203

Frequency MHz 167, 200, 250

Cycle Time ns

4 ns (C6711DGDP-250)

5 ns (C6711DGDP−200

and C6711DZDP−200)

6 ns (C6711DGDPA−167

and C6711DZDPA−167)

Voltage

Core (V) 1.20†

1.4 (−250)

Voltage

I/O (V) 3.3

PLL Options CLKIN frequency multiplier −

Clock Generator Options Prescaler

Multiplier

Postscaler

/1, /2, /3, ..., /32

x4, x5, x6, ..., x25

/1, /2, /3, ..., /32

BGA Package 27 x 27 mm 272-Pin BGA

(GDP and ZDP)§

Process Technology µm0.13 µm

Product Status

Product Preview (PP)

Advance Information (AI)

Production Data (PD)

PD‡

†These values are compatible with existing 1.26−V designs.

‡PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include testing of all parameters.

§The ZDP package devices are supported in the same speed grades as the GDP package devices (available upon request).

C6000 is a trademark of Texas Instruments.

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device compatibility

The TMS320C6211/C6211B and C6711/C6711B devices are pin-compatible and have the same peripheral set;

thus, making new system designs easier and providing faster time to market. The following list summarizes the

device characteristic differences among the C6211, C6211B, C6711, C6711B, C6711C, and C6711D devices:

DThe C6211 and C6211B devices have a fixed-point C62x CPU, while the C6711, C6711B, C6711C, and

C6711D devices have a floating-point C67x CPU.

DThe C6211/C6211B device runs at -167 and -150 MHz clock speeds (with a C6211BGFNA extended

temperature device that also runs at -150 MHz), while the C6711/C6711B device runs at -150 and -100 MHz

(with a C6711BGFNA extended temperature device that also runs at -100 MHz) and the C6711C and

C6711D devices run at -200 clock speed (with a C6711CGDPA and C6711DGDPA extended temperature

devices that also run at -167 MHz).

DThe C6211/C6211B, C6711-100, and C6711B devices have a core voltage of 1.8 V, the C6711-150 device

core voltage is 1.9 V, and the C6711C and C6711D devices operate with a core voltage of 1.20†V.

DThere are several enhancements and features that are only available on the C6711C and C6711D devices,

such as: the CLKOUT3 signal, a software programmable PLL and PLL Controller, and a GPIO peripheral

module. The C6711D device also has additional enhancements such as: EMIF Big Endian mode

correctness EMIFBE and the L1D requestor priority to L2 bit [“P” bit] in the cache configuration (CCFG)

For more detailed discussion on the migration of a C6211, C6211B, C6711, C6711B device to a TMS320C6711C

device, see the Migrating from TMS320C6211B/6711B to TMS320C6711C application report (literature number

SPRA837).

For a more detailed discussion on the similarities/differences between the C6211 and C6711 devices, see the

How to Begin Development Today with the TMS320C6211 DSP and How to Begin Development with the

TMS320C6711 DSP application reports (literature number SPRA474 and SPRA522, respectively).

†This value is compatible with existing 1.26V designs.

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functional block and CPU (DSP core) diagram

ÁÁÁ

Test

C6000CPU (DSP Core)

Data Path B

B Register File

Instruction Fetch

Instruction Dispatch

Instruction Decode

Data Path A

A Register File

Power-Down

Logic

.L1†.S1†.M1†.D1 .D2 .M2†.S2†.L2†

SDRAM

ROM/FLASH

SBSRAM

I/O Devices

L1P Cache

Direct Mapped

4K Bytes Total

Control

Registers

Control

Logic

L1D Cache

2-Way Set

Associative

4K Bytes Total

In-Circuit

Emulation

Interrupt

Control

Framing Chips:

H.100, MVIP,

SCSA, T1, E1

AC97 Devices,

SPI Devices,

Codecs

Digital Signal Processor

†In addition to fixed-point instructions, these functional units execute floating-point instructions.

‡The device has a software-configurable PLL (with x4 through x25 multiplier and /1 through /32 divider).

Enhanced

DMA

Controller

(16 channel)

Memory

4 Banks

64K Bytes

Total

PLL‡

Timer 0

External

Memory

Interface

(EMIF)

Multichannel

Buffered

Serial Port 1

(McBSP1)

Multichannel

Buffered

Serial Port 0

(McBSP0)

Host Port

Interface

(HPI)

SRAM

Timer 1

Boot

Configuration

Interrupt

Selector

GPIO

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CPU (DSP core) description

The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit

instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by

which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit

of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous

instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch

packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute

packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains

functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files

each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along

with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and

Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that

side. Additionally, each side features a single data bus connected to all the registers on the other side, by which

the two sets of functional units can access data from the register files on the opposite side. While register access

by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,

The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight

functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two

functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a

total of 128 bits per cycle.

Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers

(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data

transfers between the register files and the memory. The data address driven by the .D units allows data

addresses generated from one register file to be used to load or store data to or from the other register file. The

C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes

with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some

registers, however, are singled out to support specific addressing or to hold the condition for conditional

instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results

available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least

significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous

execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,

effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the

fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of

the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet

can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one

per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch

packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units

for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit

registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store

instructions are byte-, half-word, or word-addressable.



   

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

10 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251−1443

CPU (DSP core) description (continued)

ÁÁÁÁÁ

long src

dst

src2

src1

long dst

dst

src2

long src

long dst

long src

ÁÁÁÁÁ

.L2†

.S2†

.M2†

.D2

ÁÁ

.D1

.M1†

ÁÁ

.S1†

ÁÁ

.L1†

ÁÁ

Control

DA1

DA2

ST1

LD1 32 LSB

LD2 32 LSB

LD2 32 MSB

Data Path A

Data Path B

File A

(A0−A15)

File B

(B0−B15)

LD1 32 MSB

ST2 32

†In addition to fixed-point instructions, these functional units execute floating-point instructions.

Figure 1. TMS320C67xCPU (DSP Core) Data Paths

Table des matières

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