Texas Instruments LM97937EVM R2 Manuel utilisateur

LM97937EVM R2

User's Guide

Literature Number: SLAU542

December 2013

Contents

1 Introduction ........................................................................................................................ 4

2 Equipment .......................................................................................................................... 5

2.1 Evaluation Board Feature Identification Summary .................................................................. 5

2.2 Required Equipment .................................................................................................... 5

3 Setup Procedure ................................................................................................................. 6

3.1 Install the High Speed Data Converter Pro (HSDP) Software ..................................................... 6

3.2 Install the Configuration GUI Software ............................................................................... 6

3.3 Connect the EVM and TSW14J56EVM .............................................................................. 6

3.4 Connect the Power Supplies to the Boards (Power Off) ........................................................... 7

3.5 Connect the Signal Generators to the EVM (RF Signal Off) ...................................................... 7

3.6 Turn the TSW14J56EVM Power on and Connect to the PC ...................................................... 7

3.7 Turn the EVM Power Supplies on and Connect to the PC ........................................................ 7

3.8 Turn the Signal Generator RF Outputs on ........................................................................... 7

3.9 Open the HSDP Software and Load the FPGA Image to the TSW14J56EVM ................................. 7

3.10 Program the LMK04828 Using the Configuration Tab on the HSDC Pro Software ............................ 8

3.11 Calibrate the ADC Device on the EVM ............................................................................... 8

3.12 Verify the TSW14J56EVM Switch Settings, Initialize the JESD204B Link (CPU_RESET), and Verify

TSW14J56EVM Status LEDs .......................................................................................... 8

3.13 Capture Data Using the HSDP Software ............................................................................. 8

3.14 Re-Verify TSW14J56EVM Status LEDs .............................................................................. 9

4 Device Configuration ......................................................................................................... 11

4.1 Supported JESD204B Device Features ............................................................................ 11

4.2 Using the Device Configuration GUI ................................................................................ 11

4.3 Tab Organization ....................................................................................................... 13

4.4 Low-Level Control ...................................................................................................... 13

5 Evaluation Troubleshooting ................................................................................................ 15

6 References ....................................................................................................................... 15

Appendix A .............................................................................................................................. 16

A.1 TSW14J56EVM LED Bank and Switch Configuration ........................................................... 16

A.2 HSDC Pro Settings for Optional ADC Device Configuration ................................................... 17

A.3 Exercising the SYSREF Input of the ADC ........................................................................ 17

A.4 Customizing the EVM for Optional Clocking Support ............................................................ 17

2Table of Contents SLAU542–December 2013

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List of Figures

1 EVM Feature Locations .................................................................................................... 5

2 EVM Test Setup............................................................................................................. 6

3 High Speed Data Converter Pro (HSDP) GUI .......................................................................... 9

4 Configuration GUI Intro Tab.............................................................................................. 12

5 Configuration GUI ADC Core Tab....................................................................................... 12

6 Low-Level Register Control Tab ........................................................................................ 14

List of Tables

1 Default State of LEDs on the TSW14J56EVM During Typical Operation ........................................... 8

2 Default State of LEDs on the TSW14J56EVM during Typical Operation .......................................... 10

3 Supported and Non-Supported Features of the JESD204B Device................................................ 11

4 Low-Level Controls........................................................................................................ 13

5 Troubleshooting ........................................................................................................... 15

6 Meaning of LEDs on the TSW14J56EVM.............................................................................. 16

7 Required State of Switches on the TSW14J56EVM.................................................................. 16

SLAU542–December 2013 List of Figures

1 Introduction

The LM97937EVM is an evaluation board used to evaluate the LM97937 analog-to-digital converter (ADC)

from TI. The LM97937 device is a dual-channel, 9-bit ADC with SNRBoost and Bit-Burst signal processing

capable of operating at sampling rates up to 370 Mega samples per second (MSPS). The LM97937

device output data is transmitted over a standard JESD204B high-speed serial interface.

This evaluation board also includes the following important features:

• Transformer-coupled signal input network allowing a single-ended signal source from 5 MHz to 1 GHz

• LMK04828 system clock generator that generates FPGA reference clocks for the high-speed serial

interface and may be used to generate the ADC sampling clock

• Transformer-coupled clock input network to test the ADC performance with a very low-noise clock

source

• High-speed serial data output over a standard FMC interface connector

• Device register programming via USB connector and FTDI USB-to-SPI bus translator

The digital data from the LM97937EVM board can be quickly and easily captured with the TSW14J56EVM

data capture board. The TSW14J56EVM captures the high-speed serial data, decodes the data, stores

the data in memory, then uploads it to a connected PC through a USB interface for analysis. The High

Speed Data Converter Pro (HSDC Pro) software on the PC communicates with the hardware and

processes the data.

With proper hardware selection in the HSDC Pro software, the TSW14J56 device is automatically

configured to support a wide range of operating speeds of the LM97937EVM, but it may not cover the full

operating range of the ADC device. Serial data rates (and corresponding sampling rates) of 7.4 Gb/s (370

MSPS) down to 1.6 Gb/s (80 MSPS) are supported.

For the rest of this document, the LM97937EVM evaluation board is referred to as EVM and the LM97937

device is referred to as ADC device.

4List of Tables SLAU542–December 2013

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- +

Ch. A Analog Input ADC

Ch. B Analog Input

USB Register

Configuration

Connector

CLK Input

FMC Connector

(Back-side)

LMK

Input Power

Connectors

Primary (+4V)

SYSREF Input EXTREF Input

(Optional LMK04828

reference)

JP1

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Equipment

2 Equipment

This section describes how to setup the EVM on the bench with the proper equipment to evaluate the full

performance of the ADC device.

2.1 Evaluation Board Feature Identification Summary

Figure 1. EVM Feature Locations

2.2 Required Equipment

The following equipment and documents are included in the EVM evaluation kit:

• Evaluation board (EVM)

• Mini-USB cable

The following equipment is not included in the EVM evaluation kit, but is required for evaluation of this

product.

• TSW14J56EVM data capture board plus +5-V power supply and mini-USB cable

• High Speed Data Converter Pro software

• PC computer running Windows XP, 7, or 8

• Two low-noise signal generators. TI recommends the following generators:

– RF generator, > +17 dBm, < –40 dBc harmonics, < 500 fs jitter 20 kHz to 20 MHz, 10 MHz to 2

GHz frequency range

– HP HP8644B

– Rohde & Schwarz™ SMA100A

• Bandpass filter for clock input (370MHz or desired frequency). The following filters are recommended:

– Bandpass filter, ≥60 dB harmonic attenuation, ≤5% bandwidth, > +18 dBm power, < 5 dB insertion

loss

– Trilithic™ 5VH-series tunable BPF

– K&L Microwave™ BT-series tunable BPF

– TTE KC6 or KC7-series fixed BPF

• Bandpass filter for analog input signal. Recommended filters similar to the clock path filter.

• 6-dB resistive attenuator, SMA, 50 Ω

• Signal-path and clock-path cables, SMA or BNC (or both SMA and BNC)

• +4 V, 2-A power supply and cable

SLAU542–December 2013 List of Tables

Channel A

Channel B

6dB, 50

Attenuator

Analog Input

Low Noise

Signal Generator

Clock Input

Low-Noise

Signal Generator

Low Noise

Power Supply

(+4V, 2A)

Mini-USB Cable

+5V Power Supply

Bandpass

Filter

Bandpass

Filter

PC Computer

Running HSDC Pro

CLK

+4V

ADC EVM

TSW14J56EVM

Power

Switch

OFF ON

Setup Procedure

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3 Setup Procedure

Figure 2. EVM Test Setup

NOTE: The HSDP software must be installed before connecting the TSW14J56EVM to the PC for

the first time.

3.1 Install the High Speed Data Converter Pro (HSDP) Software

Download the most recent version of the HSDP software from www.ti.com/tool/dataconverterpro-sw.

Follow the installation instructions to install the software.

3.2 Install the Configuration GUI Software

1. Download the Configuration GUI software from the EVM product page at www.ti.com.

2. Extract files from the zip file.

3. Run “setup.exe” and follow the instructions.

3.3 Connect the EVM and TSW14J56EVM

With the power off, connect the EVM to the TSW14J56EVM via the FMC connector as shown in Figure 2.

Check that the standoffs provide the proper height for robust connector connections.

6List of Tables SLAU542–December 2013

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Setup Procedure

3.4 Connect the Power Supplies to the Boards (Power Off)

1. Confirm that the power switch on the TSW14J56EVM is in the off position. Connect the +5-V power

supply adapter to the TSW14J56EVM.

2. Confirm that the +4-V power supply for the EVM is turned off. Connect the +4-V power supply to the

green power connector (closest to the USB connector).

CAUTION

Do not turn on the power to any board. Powering up the boards in the incorrect

order could potentially cause damage to one of the boards.

3.5 Connect the Signal Generators to the EVM (RF Signal Off)

1. Connect a signal generator to the CLK input of the EVM through a bandpass filter. This must be a low-

noise signal generator. TI recommends a Trilithic™ tunable bandpass filter to filter the signal coming

from the generator. Configure the signal generator for 370 MHz. When using an RF signal generator,

the power input to the CLK SMA connector should be +11 dBm (2.2 Vpp into 50 Ω) for best

performance and must be at least +4 dBm to function. Therefore, the signal generator should be

increased above +11 dB by an amount equal to any additional attenuation in the clock signal path,

such as the insertion loss of the bandpass filter. For example, if the filter insertion loss is 2 dB, the

signal generator should be set to +11 dBm + 2 dB = +13 dBm.

2. Connect a signal generator to the VINA+ input of the EVM through a bandpass filter and attenuator at

the SMA connector. This must be a low-noise signal generator. TI recommends a Trilithic™ tunable

bandpass filter to filter the signal from the generator. Configure the signal generator for 70 MHz, +0

dBm.

3. It is important to frequency lock the input signal generator to the clock signal generator using the 10-

MHz reference. This is required to achieve coherent sampling of the input signal and is recommended,

if possible. Frequency locking this signal generator is not required for non-coherent sampling.

NOTE: Do not turn on the RF output of any signal generator.

3.6 Turn the TSW14J56EVM Power on and Connect to the PC

1. Turn the power switch of the TSW14J56EVM on.

2. Connect a mini-USB cable from the PC to the TSW14J56EVM.

3. If this is the first time connecting the TSW14J56EVM to the PC, then follow the on-screen instructions

to automatically install the device drivers. See the TSW14J56EVM User’s Guide for more specific

instructions.

3.7 Turn the EVM Power Supplies on and Connect to the PC

1. Turn the +4-V power supply on to power up the EVM.

2. Connect the EVM to the PC with the mini-USB cable.

3.8 Turn the Signal Generator RF Outputs on

Turn on the RF signal outputs of the signal generators connector to CLK and VINA+.

3.9 Open the HSDP Software and Load the FPGA Image to the TSW14J56EVM

1. Open the HSDP software.

2. Press OK to confirm the serial number of the TSW14J56EVM device.

3. Select the ‘LM97937EVM_222’ device from the ADC select drop-down in the top left corner and press

'Yes' to update the firmware.

SLAU542–December 2013 List of Tables

Setup Procedure

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NOTE: If the user configures the EVM with options other than the default register values, different

instructions may be required for selecting the device in HSDC Pro. See the Appendix A for

more details.

4. Enter the ADC sampling rate (Fs) as 370M or the desired sampling rate. This number should be equal

to the actual sampling rate of the device and must be updated if the sampling rate changes.

3.10 Program the LMK04828 Using the Configuration Tab on the HSDC Pro Software

1. Note that selecting the EVM in the ADC select drop-down menu made an additional tab appear in

HSDC Pro. Select the tab in the HSDC Pro software and navigate to the ‘Clock Dist’ sub-tab.

2. Press the ‘Configuration 1’ button. Verify that pressing the button changes the state of the LEDs on the

translation card, or that it changes the current draw from the +4-V power supply.

3.11 Calibrate the ADC Device on the EVM

1. With the FTDI SPI GUI open on the PC, navigate to the ‘Intro’ tab.

2. Set the sampling rate selection switch to appropriately indicate the desired sampling rate.

3. Press the calibrate button to calibrate the ADC.

NOTE: This calibrate button executes a calibration sequence that is required for full performance.

This calibration should be performed at power-up, any time the sampling rate changes, or

after exiting the power-down mode. See the device data sheet, SNVS990, for details

regarding the necessary calibration sequence.

3.12 Verify the TSW14J56EVM Switch Settings, Initialize the JESD204B Link

(CPU_RESET), and Verify TSW14J56EVM Status LEDs

1. Observe the switches and jumpers on the TSW14J56EVM and verify that they are in the correct

position. The required switch settings are shown in Table 4.

2. Press the CPU_RESET button (SW7) on the TSW14J56EVM. This button is used to reset the

JESD204B receiver core in the receiving FPGA and should be pressed after power-up, after changing

the test setup, or after changing particular device configuration registers.

3. Verify the status of the D1 to D8 LEDs on the TSW14J56EVM. See the Appendix A for more

information regarding the status LEDs.

Table 1. Default State of LEDs on the TSW14J56EVM

During Typical Operation

LED Status

D1 Blinking

D2 On

D3 Blinking

D4 On

D5 On

D6 Off

D7 Off

D8 On

FPGA_DONE On

3.13 Capture Data Using the HSDP Software

1. Verify that ‘LM97937EVM_222’ is the selected device.

2. Enter the ‘ADC sampling rate (Fs)’ as the desired sampling rate. This value must be equal to the

operating sampling rate of the device.

8List of Tables SLAU542–December 2013

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Choose

Channel

Choose

Data

View

Choose

Test

Select Device and

Capture Data

Check Coherent Freq. Auto‐calculate

Select Size of Data Set

Enter Sampling Rate

Enter Desired Input Frequency

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Setup Procedure

3. It is important to check the ‘Auto Calculate Coherent Frequencies’ checkbox. Enter the frequency of

the analog input signal generator into the ‘ADC Input Target’ box and press Enter. Update the analog

input signal generator to the calculated frequency.

4. Select the test to perform.

5. Select the data view.

6. Select the channel to view.

7. Press the capture button to capture new data.

Additional tips:

• Use the ‘Notch Frequency Bins’ from the 'Test Options' file menu to remove bins around DC (eliminate

DC noise and offset) or the fundamental (eliminate phase noise from signal generators).

• Open the ‘Capture Option’ dialog from the 'Data Capture Options' file menu to change the capture

depth or to enable FFT averaging.

• For analyzing only a portion of the spectrum, use the ‘Single Tone’ test with the ‘Bandwidth Integration

Markers’ from the ‘Test Options’ file menu. The ‘Channel Power’ test may also be useful.

• For analyzing only a subset of the captured data, set the ‘Analysis Window (samples)’ setting to a

value less than the number total samples captured and move the green or red markers in the small

transient data window at the top of the screen to select the data subset of interest.

Figure 3. High Speed Data Converter Pro (HSDP) GUI

3.14 Re-Verify TSW14J56EVM Status LEDs

Verify the status of the D1 to D8 LEDs on the TSW14J56EVM. See the Appendix A for more information

regarding the status LEDs.

SLAU542–December 2013 List of Tables

Setup Procedure

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NOTE: Note that D4 has changed to indicate that the JESD204B link is established.

Table 2. Default State of LEDs on the TSW14J56EVM

during Typical Operation

LED Status

D1 Blinking

D2 On

D3 Blinking

D4 Off

D5 On

D6 Off

D7 Off

D8 On

FPGA_DONE On

10 List of Tables SLAU542–December 2013

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