Texas Instruments C28 Series Manuel utilisateur

C28x DSP Design Workshop

Student Guide

Technical Training

Organization

C28x

Revision 5.0

February 2004

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Customers are responsible for their applications using TI components.

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TI assumes no liability for applications assistance or customer product design. TI does not warrant or

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Revision History

October 2001 – Revision 1.0

January 2002 – Revision 2.0

May 2002 – Revision 3.0

June 2002 – Revision 3.1

October 2002 – Revision 4.0

December 2002 – Revision 4.1

July 2003 – Revision 4.2

August 2003 – Revision 4.21

February 2004 – Revision 5.0

Mailing Address

Texas Instruments

Training Technical Organization

7839 Churchill Way

M/S 3984

Dallas, Texas 75251-1903

ii C28x - Introduction

C28x Workshop

C28x DSP Design Workshop

Texas Instruments

Technical Training

Organization

TTO

eZdsp™ F2812 Starter Kit

eZdsp

eZdsp is a trademark of Spectrum Digital, Inc.

is a trademark of Spectrum Digital, Inc.

Introductions



Name

Name



Company

Company



Project Responsibilities

Project Responsibilities



DSP / Microcontroller Experience

DSP / Microcontroller Experience



TMS320 DSP Experience

TMS320 DSP Experience



Hardware / Software

Hardware / Software -

-Assembly / C

Assembly / C



Interests

Interests

C28x - Introduction iii

C28x Workshop

iv C28x - Introduction

C28x Workshop Outline

1. Architecture Overview

Architecture Overview

2. Programming Development Environment

Programming Development Environment

3. Peripheral Register Header Files

Peripheral Register Header Files

4. Reset and Interrupts

Reset and Interrupts

5. System Initialization

System Initialization

6. Analog

Analog-

-to

to-

-Digital Converter

Digital Converter

7. Event Manager

Event Manager

8. Numerical Concepts and IQ Math

Numerical Concepts and IQ Math

9. Using DSP/BIOS

Using DSP/BIOS

10.

10. System Design

System Design

11.

11. Communications

Communications

12.

12. Support Resources

Support Resources

eZdsp™ F2812 Hardware

eZdsp

eZdsp™ F2812 Hardware

™ F2812 Hardware

Parallel Port/

JTAG

Controller

Interface (P3)

I/O Interface (P4/P8/P7)

ANALOG

Interface (P5/P9)

SRAM

64K x 16

JTAG Interface (P1)

JTAG Interface (P1) EXPANSION

EXPANSION

Data & Address (P2)

Power

Connector (P6)

+5V

TMS320F2812

TMS320F2812 -

-DSP

DSP

Architecture Overview

Introduction

This architecture overview introduces the basic architecture of the TMS320C28x (C28x) series of

Digital Signal Processors from Texas Instruments. The C28x series adds a new level of general

purpose processing ability unseen in any previous DSP chips. The C28x is ideal for applications

combining DSP, standard microcontroller processing, efficient C code execution, or operating

system tasks.

Learning Objectives

When this module is complete, you should have a basic understanding of the C28x architecture

and how all of its components work together to create a high-end, uniprocessor control system.

Learning Objectives



Identify the three main components

Identify the three main components

of the C28x



List the key features of the C28x

List the key features of the C28x

CPU



Identify the memory capabilities of

Identify the memory capabilities of

the C28x



Identify the peripherals available on

Identify the peripherals available on

the C28x

C28x - Architecture Overview 1 - 1

Module Topics

Architecture Overview.............................................................................................................................. 1-1

Module Topics......................................................................................................................................... 1-2

What is the TMS320C28x?...................................................................................................................... 1-3

C28x CPU ............................................................................................................................................... 1-4

Multiplier, ALU, and Shifters............................................................................................................. 1-5

TMS320C28x Internal Bussing .......................................................................................................... 1-6

Special Instructions............................................................................................................................. 1-7

Pipeline Advantage............................................................................................................................. 1-8

Memory ................................................................................................................................................... 1-9

Memory Map ...................................................................................................................................... 1-9

Code Security Module (CSM)...........................................................................................................1-10

Peripherals .........................................................................................................................................1-10

Fast Interrupt Response.........................................................................................................................1-11

C28 Mode...............................................................................................................................................1-12

Reset.......................................................................................................................................................1-13

Summary ................................................................................................................................................1-14

1 - 2 C28x - Architecture Overview

What is the TMS320C28x?

The TMS320C28x is a 32-bit fixed point DSP that specializes in high performance control

applications such as, robotics, industrial automation, mass storage devices, lighting, optical

networking, power supplies, and other control applications needing a single processor to solve a

high performance application.

C28x Block Diagram

32x32 bit

Multiplier

32x32 bit

Multiplier

Sectored

Flash

Sectored

Flash

A(18

A(18-

-0)

D(15

D(15-

-0)

Program Bus

Data Bus

RAM

Boot

ROM

Boot

ROM

32-bit

Auxiliary

Registers

32-

-bit

bit

Auxiliary

Registers

32 bit

Timers

32 bit

Timers

Realtime

JTAG

Realtime

JTAG

JTAG CPU

CPU

R-M-W

Atomic

ALU

R-

-M

M-

-W

Atomic

ALU

PIE

Interrupt

Manager

Event

Manager A

Event

Manager A

Event

Manager B

Event

Manager B

12-bit ADC

12-

-bit ADC

bit ADC

Watchdog

McBSP

CAN2.0B

SCI-A

SCI

SCI-

-A

SCI-B

SCI

SCI-

-B

SPI

GPIO

The C28x architecture can be divided into 3 functional blocks:

• CPU and busing

• Memory

• Peripherals

C28x - Architecture Overview 1 - 3

C28x CPU

The C28x is a highly integrated, high performance solution for demanding control applications.

The C28x is a cross between a general microcontroller and a digital signal processor, balancing

the code density of a RISC chip and the execution speed of a DSP with the architecture,

firmware, and development tools of a microcontroller.

The DSP features include a modified Harvard architecture and circular addressing. The RISC

features are single-cycle instruction execution, register-to-register operations, and modified

Harvard architecture. The microcontroller features include ease of use through an intuitive

instruction set, byte packing and unpacking, and bit manipulation.

C28x CPU



32

32-

-bit fixed

bit fixed-

-point DSP

point DSP



32 x 32 bit fixed

32 x 32 bit fixed-

-point MAC

point MAC



Dual 16 x 16 single

Dual 16 x 16 single-

-cycle fixed

cycle fixed-

point MAC (DMAC)



32

32-

-/64

/64-

-bit saturation

bit saturation



64/32 and 32/32 modulus division

64/32 and 32/32 modulus division



Fast interrupt service time

Fast interrupt service time



Single cycle read

Single cycle read-

-modify

modify-

-write

write

instructions



Unique real

Unique real-

-time debugging

time debugging

capabilities



Upward code compatibility

Upward code compatibility

Data Bus

32-bit

Auxiliary

Registers

32-

-bit

bit

Auxiliary

Registers

32 bit

Timers

32 bit

Timers

Realtime

JTAG

Realtime

JTAG

JTAG CPU

CPU

R-M-W

Atomic

ALU

R-

-M

M-

-W

Atomic

ALU

Program Bus



MCU/DSP balancing code density

MCU/DSP balancing code density

& execution time.



Supports 32

Supports 32-

-bit instructions

bit instructions

for improved execution time;



Supports 16

Supports 16-

-bit instructions

bit instructions

for improved code efficiency

PIE

Interrupt

Manager

32x32 bit

Multiplier

32x32 bit

Multiplier

The C28x design supports an efficient C engine with hardware that allows the C compiler to

generate compact code. Multiple busses and an internal register bus allow an efficient and

flexible way to operate on the data. The architecture is also supported by powerful addressing

modes, which allow the compiler as well as the assembly programmer to generate compact code

that is almost one to one corresponded to the C code.

The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are

handled by microcontroller devices. This efficiency removes the need for a second processor in

many systems.

The C28x is one of several members of the fixed-point generations of digital signal processors

(DSPs) in the TMS320 family. The C28x is source-code and object-code compatible with the

C27x. In addition, the C28x is source code compatible with the 24x/240x DSP and previously

written code can be reassembled to run on a C28x device. This allows for migration of existing

code onto the C28x.

1 - 4 C28x - Architecture Overview

C28x CPU

Multiplier, ALU, and Shifters

XT (32) or T/TL

MULTIPLIER

32 x 32 or

Dual 16 x 16

P (32) or PH/PL

AH (16)

C28x Multiplier and ALU / Shifters

Data Bus

Program Bus

ALU (32)

AL (16)

•

16/32

8/16

Shift R/L (0

Shift R/L (0-

-16)

16)

ACC (32)

AH.MSB AH.LSB

AH.MSB AH.LSB AL.MSB AL.LSB

AL.MSB AL.LSB

Shift R/L (0

Shift R/L (0-

-16)

16)

•

Shift R/L (0

Shift R/L (0-

-16)

16)

The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the

C28x to efficiently handle higher numerical resolution problems that would otherwise demand a

more expensive floating-point processor solution. Along with this is the capability to perform

two 16 x 16-bit multiply accumulate instructions simultaneously or Dual MACs (DMAC).

C28x

C28x XARn

XARn, DP and Memory

, DP and Memory

XAR0

XAR1

XAR2

XAR3

XAR4

XAR5

XAR6

XAR7

ARAU

MUX

Data Memory

MUX

DP (16)

Data Bus

Program Bus

6 LSB

from IR

XARn

XARn →

→32

32-

-bits

bits

ARn

ARn →

→16

16-

-bits

bits

C28x - Architecture Overview 1 - 5

C28x CPU

TMS320C28x Internal Bussing

As with many DSP type devices, multiple busses are used to move data between the memories

and peripherals and the CPU. The C28x memory bus architecture contains:

• A program read bus (22 bit address line and 32 bit data line)

• A data read bus (32 bit address line and 32 bit data line)

• A data write bus (32 bit address line and 32 bit data line)

C28x Internal Bus Structure

Data

Data-

-write Address Bus (32)

write Address Bus (32)

Program Address Bus (22)

Execution

R-

-M

M-

-W

Atomic

ALU

Real

Real-

-Time

Time

Emulation

Test

Engine

Program

Program-

-read Data Bus (32)

read Data Bus (32)

JTAG

Program

Decoder

XAR0

XAR7

DP @X

ARAU

ARAU MPY32x32

MPY32x32

ACC

ALU

Registers

Registers Debug

Debug

Data/Program

Data/Program-

-write Data Bus (32)

write Data Bus (32)

Data

Data-

-read Address Bus (32)

read Address Bus (32)

Data

Data-

-read Data Bus (32)

read Data Bus (32)

Memory

Data

(4G * 16)

Program

(4M* 16)

Standard

Peripherals

External

Interfaces

The 32-bit-wide data busses enable single cycle 32-bit operations. This multiple bus architecture,

known as a Harvard Bus Architecture enables the C28x to fetch an instruction, read a data value

and write a data value in a single cycle. All peripherals and memories are attached to the memory

bus and will prioritize memory accesses.

1 - 6 C28x - Architecture Overview

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