ST ST7LITE1 B Series Manuel utilisateur

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June 2008 1/159

Rev 6

ST7LITE1xB

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,

DATA EEPROM, ADC, 5 TIMERS, SPI

■Memories

– up to 4 Kbytes single voltage extended Flash

(XFlash) Program memory with read-out pro-

tection, In-Circuit Programming and In-Appli-

cation programming (ICP and IAP). 10K write/

erase cycles guaranteed, data retention: 20

years at 55°C.

– 256 bytes RAM

– 128 bytes data EEPROM with read-out pro-

tection. 300K write/erase cycles guaranteed,

data retention: 20 years at 55°C.

■Clock, Reset and Supply Management

– Enhanced reset system

– Enhanced low voltage supervisor (LVD) for

main supply and an auxiliary voltage detector

(AVD) with interrupt capability for implement-

ing safe power-down procedures

– Clock sources: Internal 1% RC oscillator (on

ST7FLITE15B and ST7FLITE19B), crystal/

ceramic resonator or external clock

– Internal 32-MHz input clock for Auto-reload

timer

– Optional x4 or x8 PLL for 4 or 8 MHz internal

clock

– Five Power Saving Modes: Halt, Active-Halt,

Auto Wake-up from Halt, Wait and Slow

■I/O Ports

– Up to 17 multifunctional bidirectional I/O lines

–7

high sink outputs

■5 Timers

– Configurable watchdog timer

– Two 8-bit Lite Timers with prescaler,

1 realtime base and 1 input capture

– Two 12-bit Auto-reload Timers with 4 PWM

outputs, 1 input capture, 4 output compare

and one pulse functions

■Communication Interface

– SPI synchronous serial interface

■Interrupt Management

– 12 interrupt vectors plus TRAP and RESET

– 15 external interrupt lines (on 4 vectors)

■Analog Comparator

■A/D Converter

– 7 input channels

– Fixed gain Op-amp

– 13-bit precision for 0 to 430 mV (@ 5V VDD)

– 10-bit precision for 430 mV to 5V (@ 5V VDD)

■Instruction Set

– 8-bit data manipulation

– 63 basic instructions with illegal opcode de-

tection

– 17 main addressing modes

– 8 x 8 unsigned multiply instructions

■Development Tools

– Full hardware/software development package

– DM (Debug Module)

Device Summary

DIP20

DIP16 SO16

300”

QFN20

SO20

Features ST7LITE10B ST7LITE15B ST7LITE19B

Program memory - bytes 2K/4K

RAM (stack) - bytes 256 (128)

Data EEPROM - bytes - - 128

Peripherals Lite Timer with Wdg, Autoreload

Timer, SPI, 10-bit ADC with Op-Amp

Lite Timer with Wdg, Autoreload Timer with 32-MHz input clock, SPI,

10-bit ADC with Op-Amp, Analog Comparator

Operating Supply 2.7V to 5.5V

CPU Frequency Up to 8Mhz(w/ ext OSC at 16MHz) Up to 8Mhz (w/ ext OSC at 16MHz or int 1MHz RC 1%, PLLx8/4MHz)

Operating Temperature -40°C to +85°C / -40°C to +125°C

Packages SO20 300”, DIP20, SO16 300”, DIP16 SO20 300”, DIP20, SO16 300”, DIP16, QFN20

Table of Contents

159

2/159

1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.5 ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.6 DATA EEPROM READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.2 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.4 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

7.5 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

7.6 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.1 NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.2 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

8.3 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

9.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

9.4 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.5 ACTIVE-HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9.6 AUTO WAKE UP FROM HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

10 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table of Contents

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10.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

10.8 MULTIPLEXED INPUT/OUTPUT PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.2 DUAL 12-BIT AUTORELOAD TIMER 4 (AT4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.3 LITE TIMER 2 (LT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

11.5 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

11.6 ANALOG COMPARATOR (CMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

12.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

13.10 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 137

13.11 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

13.12 ANALOG COMPARATOR CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

13.13 PROGRAMMABLE INTERNAL VOLTAGE REFERENCE CHARACTERISTICS . . . . . 143

13.14 CURRENT BIAS CHARACTERISTICS (FOR COMPARATOR AND INTERNAL VOLTAGE

REFERENCE) 143

14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

14.2 SOLDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 149

15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

15.2 DEVICE ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

15.4 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

ST7LITE1xB

4/159

1 INTRODUCTION

The ST7LITE1xB is a member of the ST7 micro-

controller family. All ST7 devices are based on a

common industry-standard 8-bit core, featuring an

enhanced instruction set.

The ST7LITE1xB features FLASH memory with

byte-by-byte In-Circuit Programming (ICP) and In-

Application Programming (IAP) capability.

Under software control, the ST7LITE1xB device

can be placed in WAIT, SLOW, or HALT mode, re-

ducing power consumption when the application is

in idle or standby state.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

For easy reference, all parametric data are located

in section 13 on page 110. The ST7LITE1xB fea-

tures an on-chip Debug Module (DM) to support

In-Circuit Debugging (ICD). For a description of

the DM registers, refer to the ST7 ICC Protocol

Reference Manual.

Figure 1. General Block Diagram

8-BIT CORE

ALU

ADDRESS AND DATA BUS

OSC1

OSC2

RESET

PORT A

Internal

CLOCK

CONTROL

RAM

(256 Bytes)

PA7:0

(8 bits)

VSS

VDD POWER

SUPPLY

PROGRAM

(up to 4K Bytes)

LVD, AVD

MEMORY

PLL x 8

Ext.

1MHz

PLL

Int.

1MHz

8-Bit

LITE TIMER 2

PORT B

SPI

PB6:0

(7 bits)

DATA EEPROM

(128 Bytes)

1% RC

OSC

16MHz

ADC

+ OpAmp

12-Bit

Auto-Reload

TIMER 2

CLKIN

/ 2

or PLL X4

8MHz -> 32MHz

WATCHDOG

Debug Module

Programmable

Internal Reference

Comparator

PORT C PC1:0

(2 bits)

ST7LITE1xB

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2 PIN DESCRIPTION

Figure 2. 20-Pin SO and DIP Package Pinout

Figure 3. 20-Pin QFN Package Pinout

VSS

VDD

AIN5/PB5

COMPIN-/CLKIN/AIN4/PB4

MOSI/AIN3/PB3

MISO/AIN2/PB2

SCK/AIN1/PB1

COMPIN+/SS/AIN0/PB0

OSC1/CLKIN/PC0

OSC2/PC1

PA5 (HS)/ATPWM3/ICCDATA

PA4 (HS)/ATPWM2

PA3 (HS)/ATPWM1

PA2 (HS)/ATPWM0

PA1 (HS)/ATIC

PA0 (HS)/LTIC

(HS) 20mA High sink capability

eix associated external interrupt vector

AIN6/PB6 PA7(HS)/COMPOUT

PA6/MCO/ICCCLK/BREAK

RESET

ei3

ei2

ei0

ei1

78 910

17181920

AIN5/PB5

MOSI/AIN3/PB3

MISO/AIN2/PB2

SCK/AIN1/PB1

COMPIN+/SS/AIN0/PB0

AIN6/PB6

RESET

VSS

VDD

PC0/OSC1/CLKIN

PC1/OSC2

PA5 (HS)/ATPWM3/ICCDATA

PA4 (HS)/ATPWM2

PA3 (HS)/ATPWM1

PA2 (HS)/ATPWM0

PA1 (HS)/ATIC

COMPOUT/PA7(HS)

MCO/ICCCLKBREAK/PA6

(HS) 20mA High sink capability

eix associated external interrupt vector

ei3

ei1

ei0

COMPIN-/CLKIN/AIN4/PB4

ei2

16 PA0 (HS)/LTIC

ST7LITE1xB

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PIN DESCRIPTION (Cont’d)

Figure 4. 16-Pin SO and DIP Package Pinout

VSS

VDD

COMPIN-/CLKIN/AIN4/PB4

MOSI/AIN3/PB3

MISO/AIN2/PB2

SCK/AIN1/PB1

COMPIN+/SS/AIN0/PB0

OSC1/CLKIN/PC0

OSC2/PC1

PA5 (HS)/ATPWM3/ICCDATA

PA4 (HS)/ATPWM2

PA2 (HS)/ATPWM0

PA0 (HS)/LTIC

(HS) 20mA high sink capability

eix associated external interrupt vector

PA7(HS)/COMPOUT

PA6/MCO/ICCCLK/BREAK

RESET

ei3

ei2

ei0

ei1

ST7LITE1xB

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PIN DESCRIPTION (Cont’d)

Legend / Abbreviations for Table 1:

Type: I = input, O = output, S = supply

In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger

Output level: HS = 20mA high sink (on N-buffer only)

Port and control configuration:

– Input: float = floating, wpu = weak pull-up, int = interrupt, ana = analog

– Output: OD = open drain, PP = push-pull

The RESET configuration of each pin is shown in bold which is valid as long as the device is in reset state.

Table 1. Device Pin Description

Pin No.

Pin Name

Type

Level Port / Control

Main

Function

(after

reset)

Alternate Function

SO20/DPI20

QFN20

SO16/DIP16

Input

Output

Input Output

float

wpu

int

ana

1191V

SS 1) S Ground

2202V

DD 1) S Main power supply

3 1 3 RESET I/O CTXX Top priority non maskable interrupt (active low)

424

PB0/COMPIN+/

AIN0/SS I/O CTX

ei3

XXXPort B0

ADC Analog Input 0 2) or SPI Slave

Select (active low) or Analog Com-

parator Input

Caution: No negative current in-

jection allowed on this pin.

5 3 5 PB1/AIN1/SCK I/O CTXXXXPort B1 ADC Analog Input 1 2) or SPI Serial

Clock

6 4 6 PB2/AIN2/MISO I/O CTXXXXPort B2 ADC Analog Input 2 2) or SPI Mas-

ter In/ Slave Out Data

7 5 7 PB3/AIN3/MOSI I/O CTX

ei2

XXXPort B3 ADC Analog Input 3 2) or SPI Mas-

ter Out / Slave In Data

868

PB4/AIN4/CLKIN/

COMPIN- I/O CTXXXXPort B4

ADC Analog Input 4 2) or External

clock input or Analog Comparator

External Reference Input

9 7 - PB5/AIN5 I/O CTXXXXPort B5 ADC Analog Input 5 2)

10 8 - PB6/AIN6 I/O CTXXXXPort B6 ADC Analog Input 6 2)

11 9 9 PA7/COMPOUT I/O CTHS Xei1 X X Port A7 Analog Comparator Output

ST7LITE1xB

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Notes:

1. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA

pins to ground.

2. When the pin is configured as analog input, positive and negative current injections are not allowed.

3. PCOR not implemented but p-transistor always active in output mode (refer to Figure 32 on page 50).

12 10 10 PA6 /MCO/

ICCCLK/BREAK I/O CTXei1 XXPort A6

Main Clock Output or In Circuit

Communication Clock or External

BREAK

Caution: During normal operation

this pin must be pulled- up, inter-

nally or externally (external pull-up

of 10k mandatory in noisy environ-

ment). This is to avoid entering ICC

mode unexpectedly during a reset.

In the application, even if the pin is

configured as output, any reset will

put it back in input pull-up

13 11 11 PA5 /ICCDATA/

ATPWM3 I/O CTHS X

ei1

XXPort A5 In Circuit Communication Data or

Auto-Reload Timer PWM3

14 12 12 PA4/ATPWM2 I/O CTHS XXXPort A4 Auto-Reload Timer PWM2

15 13 - PA3/ATPWM1 I/O CTHS X

ei0

XXPort A3 Auto-Reload Timer PWM1

16 14 13 PA2/ATPWM0 I/O CTHS XXXPort A2 Auto-Reload Timer PWM0

17 15 - PA1/ATIC I/O CTHS XXXPort A1 Auto-Reload Timer Input Capture

18 16 14 PA0/LTIC I/O CTHS XXXPort A0 Lite Timer Input Capture

19 17 15 OSC2/PC1 I/O XXPort C13) Resonator oscillator inverter out-

put

20 18 16 OSC1/CLKIN/PC0 I/O XXPort C03) Resonator oscillator inverter input

or External clock input

Pin No.

Pin Name

Type

Level Port / Control

Main

Function

(after

reset)

Alternate Function

SO20/DPI20

QFN20

SO16/DIP16

Input

Output

Input Output

float

wpu

int

ana

ST7LITE1xB

9/159

3 REGISTER & MEMORY MAP

As shown in Figure 5, the MCU is capable of ad-

dressing 64K bytes of memories and I/O registers.

The available memory locations consist of 128

bytes of register locations, 256 bytes of RAM, 128

bytes of data EEPROM and up to 4 Kbytes of flash

program memory. The RAM space includes up to

128 bytes for the stack from 180h to 1FFh.

The highest address bytes contain the user reset

and interrupt vectors.

The Flash memory contains two sectors (see Fig-

ure 5) mapped in the upper part of the ST7 ad-

dressing space so the reset and interrupt vectors

are located in Sector 0 (F000h-FFFFh).

The size of Flash Sector 0 and other device op-

tions are configurable by Option byte (refer to sec-

tion 15.1 on page 149).

IMPORTANT: Memory locations marked as “Re-

served” must never be accessed. Accessing a re-

served area can have unpredictable effects on the

device.

Figure 5. Memory Map

0000h

RAM

Flash Memory

(2K or 4K)

Interrupt & Reset Vectors

HW Registers

0080h

007Fh

0FFFh

(see Table 2)

1000h

107Fh

FFE0h

FFFFh

(see Table 5)

0180h

Reserved

017Fh

Short Addressing

RAM (zero page)

0080h

00FFh

(128 Bytes)

Data EEPROM

(128 Bytes)

F000h

1080h

EFFFh

Reserved

FFDFh

128 Bytes Stack

0100h

017Fh

1 Kbyte

3 Kbytes

(SECTOR 1)

(SECTOR 0)

4K FLASH

FFFFh

FC00h

FBFFh

F000h

PROGRAM MEMORY

DEE0h

RCCRH1

RCCRL1

see section 7.1 on page 23

00FFh

01FFh

0100h

Reserved

RAM

(128 Bytes)

Reserved

0200h

0180h

01FFh DEE1h

DEE2h

RCCRH0

RCCRL0

DEE3h

1 Kbyte

(SECTOR 1)

(SECTOR 0)

2K FLASH

FFFFh

FC00h

FBFFh

F800h

PROGRAM MEMORY

Ce manuel convient aux modèles suivants

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