ST STM32F7 Series Supplément

February 2017 DocID027559 Rev 5 1/54

AN4661

Application note

Getting started with STM32F7 Series MCU hardware development

Introduction

This application note is intended for system designers who require an hardware

implementation overview of the development board, with a focus on the features:

•Power supply,

•Package selection,

•Clock management,

•Reset control,

•Boot mode settings,

•Debug management.

This document describes the minimum hardware resources required to develop an

application based on the STM32F7 Series devices.

Reference documents

The following documents are available on www.st.com:

•

Oscillator design guide for STM8S, STM8A and STM32 microcontrollers

application note (AN2867),

•STM32 microcontroller system memory boot mode application note (AN2606).

www.st.com

Contents AN4661

2/54 DocID027559 Rev 5

Contents

1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . . 7

1.1.2 Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.1.3 Independent SDMMC2 supply for STM32F767xx/STM32F777xx

and STM32F72xxx/STM32F73xxx devices . . . . . . . . . . . . . . . . . . . . . . . 9

1.1.4 Independent DSI supply for STM32F769xx/STM32F779xx devices . . . 10

1.1.5 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.1.6 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.2 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.3 Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.3.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . . 17

1.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.3.3 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.3.4 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3.5 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.3.6 Regulator OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.3.7 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 22

2 Alternate function mapping to pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1 HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1.1 External user clock (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.1.2 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 25

3.2 LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2.1 External clock (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2.2 External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 26

3.3 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2 Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3 System bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DocID027559 Rev 5 3/54

AN4661 Contents

5 Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . . 31

5.3.4 SWJ debug port connection with standard JTAG connector . . . . . . . . . 32

6 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1 Printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.2 Component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.3 Ground and power supply (VSS,VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.4 Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.5 Other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.6 Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.7 Recommendations for the WLCSP180 package in the

STM32F769Ax/STM32F768Ax devices . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1.3 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1.4 SWJ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.1.5 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.2 Component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8 Recommended PCB routing guidelines for

STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.1 PCB stack-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.3 Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

8.4 High speed signal layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.4.1 SDMMC bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8.4.2 Flexible memory controller (FMC) interface . . . . . . . . . . . . . . . . . . . . . . 45

Contents AN4661

4/54 DocID027559 Rev 5

8.4.3 Quadrature serial parallel interface (Quad-SPI) . . . . . . . . . . . . . . . . . . 46

8.4.4 Embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.5 Package layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

8.5.1 BGA 216 0.8 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . . . 47

8.5.2 WLCSP143 0.4 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . 49

9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

DocID027559 Rev 5 5/54

AN4661 List of tables

List of tables

Table 1. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 2. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 3. STM32F7 Series bootloader communication peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 4. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 5. Flexible SWJ-DP assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 6. Mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 7. Optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 8. Reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 9. BGA 216 0.8 mm pitch package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 10. Wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

List of figures AN4661

6/54 DocID027559 Rev 5

List of figures

Figure 1. VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. VDDUSB connected to external power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. VDDSDMMC connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Power supply overview (STM32F74xxx/STM32F75xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 5. STM32F769xx/STM32F779xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. STM32F767xx/STM32F777xx power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 7. STM32F7x2xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 8. STM32F7x3xx power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. Power on reset/power down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10. PVD threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 11. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 19

Figure 13. NRST circuitry timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 14. BYPASS_REG supervisor reset connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 15. STM32CubeMX example screen-shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 16. HSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 17. HSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 18. LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 19. LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 20. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 21. Host to board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 22. JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 23. Typical layout for VDD/VSS pair. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 24. STM32F756NGH6 reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 25. Four layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 26. Six layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 27. Example of bypass cap placed underneath the STM32F7 Series . . . . . . . . . . . . . . . . . . . 44

Figure 28. BGA 0.8mm pitch example of fan-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 29. Via fan-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 30. FMC signal fan-out routing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 31. 143-bumps WLCSP, 0.40 mm pitch routing example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

DocID027559 Rev 5 7/54

AN4661 Power supplies

1 Power supplies

1.1 Introduction

The device requires a 1.8 to 3.6 V operating voltage supply (VDD), which can be reduced

down to 1.7 V with PDR OFF, as detailed in the product datasheets. The embedded linear

voltage regulator is used to supply the internal 1.2 V digital power.

The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM)

can be powered from the VBAT voltage when the main VDD supply is powered off.

1.1.1 Independent A/D converter supply and reference voltage

To improve the conversion accuracy, the ADC has an independent power supply which can

be separately filtered and shielded from noise on the PCB.

•The ADC voltage supply input is available on a separate VDDA pin.

•An isolated supply ground connection is provided on the pin VSSA.

To ensure a better accuracy of low voltage inputs, the user can connect a separate external

reference voltage ADC input on VREF

. The voltage on VREF ranges from 1.8 V to VDDA.

When available (depending on package), VREF– must be externally tied to VSSA.

1.1.2 Independent USB transceivers supply

The USB transceivers are supplied from a separated VDDUSB power supply pin.

The VDDUSB supply can be connected either to VDD or an external independent power

supply (3.0 to 3.6V) for the USB transceivers (refer to Figure 1 and Figure 2). For example,

when the device is powered at 1.8V, an independent power supply 3.3V can be connected

to VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent

from VDD or VDDA but it must be the last supply to be provided and the first to disappear.

The following VDDUSB conditions must be respected:

•During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than

VDD.

•During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than

VDD.

•The VDDSUB rising and falling time rate specifications must be respected (refer to

operating conditions at power-up / power-down (regulator ON) table and operating

conditions at power-up / power-down (regulator OFF) table provided in the product

datasheet).

•In operating mode phase, VDDUSB could be lower or higher than VDD:

– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by

VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.

–TheV

DDUSB supplies both USB transceivers (USB OTG_HS and USB OTG_FS).

If only one USB transceiver is used in the application, the GPIOs associated to the

other USB transceiver are still supplied by VDDUSB.

– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by

VDDUSB are operating between VDD_MIN and VDD_MAX.

Power supplies AN4661

8/54 DocID027559 Rev 5

Figure 1. VDDUSB connected to VDD power supply

Figure 2. VDDUSB connected to external power supply.

In the STM32F7x3xx devices, the USB PHY HS sub-system uses an additional power

supply pin:

•The VDD12OTGHS pin is the output of the PHY HS regulator (1.2 V). An external

capacitor of 2.2 µF must be connected on the VDD12OTGHS pin.

Note: The PHY HS has another OTG_HS_REXT pin needed for calibration. This pin must be

connected to gnd via an external precise resistor (3 Kohm +/- 1%).

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DocID027559 Rev 5 9/54

AN4661 Power supplies

1.1.3 Independent SDMMC2 supply for STM32F767xx/STM32F777xx

and STM32F72xxx/STM32F73xxx devices

The VDDSDMMC is an independent power supply for SDMMC2 peripheral IOs (PD6, PD7,

PG9..12). It can be connected either to VDD or an external independent power supply.

For example, when the device is powered at 1.8V, an independent power supply 3.3V can

be connected to VDDSDMMC. When the VDDSDMMC is connected to a separated power

supply, it is independent from VDD and VDDA but it must be the last supply to be provided

and the first to disappear. The following VDDSDMMC conditions must be respected:

•During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower than

VDD.

•During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always lower

than VDD.

•The VDDSDMMC rising and falling time rate specifications must be respected.

•In the operating mode phase, VDDSDMMC could be lower or higher than VDD: the

associated GPIOs (PD6, PD7, PG9..12) powered by VDDSDMMC are operating between

VDDSDMMC_MIN and VDDSDMMC_MAX. If VDDSDMMC = VDD, the associated GPIOs

Figure 3. VDDSDMMC connected to external power supply

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Power supplies AN4661

10/54 DocID027559 Rev 5

1.1.4 Independent DSI supply for STM32F769xx/STM32F779xx devices

The DSI (Display Serial Interface) sub-system uses several power supply pins which are

independent from the other supply pins:

•The VDDDSI is an independent DSI power supply dedicated for DSI Regulator and MIPI

DPHY. This supply must be connected to global VDD.

•The VCAPDSI pin is the output of DSI Regulator (1.2V) which must be connected

externally to VDD12DSI.

•The VDD12DSI pin is used to supply the MIPI D-PHY, and to supply the clock and data

lanes pins. An external capacitor of 2.2 uF must be connected on VDD12DSI pin.

•The VDDDSI pin is an isolated supply ground used for DSI sub-system.

If the DSI functionality is not used at all, then:

•The VDDDSI pin must be connected to global VDD.

•The VCAPDSI pin must be connected externally to VDD12DSI but the external capacitor

is no more needed.

•The VSSDSI pin must be grounded.

1.1.5 Battery backup domain

Backup domain description

To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when

VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a

battery or by another source.

When the backup domain is supplied by VBAT (analog switch connected to VBAT because

VDD is not present), the following functions are available:

•PC14 and PC15 can be used as LSE pins only.

•PC13 can be used as tamper pin (TAMP1).

•PI8 can be used as tamper pin (TAMP2).

1.1.6 Voltage regulator

The voltage regulator is always enabled after reset. It works in three different modes

depending on the application modes.

•In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories

and digital peripherals).

•In Stop mode, the regulator supplies low power to the 1.2 V domain, preserving the

contents of the registers and SRAM.

•In Standby mode, the regulator is powered down. The contents of the registers and

SRAM are lost except for those concerned with the standby circuitry and the backup

domain.

Note: Depending on the selected package, there are specific pins that should be connected either

to VSS or VDD to activate or deactivate the voltage regulator. Refer to the voltage regulator

section in the datasheet for more details.

Table des matières

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