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User’s Manual

User’s Manual M68HC16Z Series

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M68HC16 Z SERIES

USER’S MANUAL

Paragraph Title Page

TABLE OF CONTENTS

SECTION 1

INTRODUCTION

SECTION 2

NOMENCLATURE

2.1 Symbols and Operators .............................................................................2-1

2.2 CPU16 Register Mnemonics .....................................................................2-2

2.3 Register Mnemonics ..................................................................................2-3

2.4 Conventions ..............................................................................................2-6

SECTION 3

OVERVIEW

3.1 M68HC16 Z-Series MCU Features ...........................................................3-1

3.1.1 Central Processor Unit (CPU16/CPU16L) .........................................3-1

3.1.2 System Integration Module (SIM/SIML) ............................................3-1

3.1.3 Standby RAM (SRAM) ......................................................................3-1

3.1.4 Masked ROM Module (MRM) — (MC68HC16Z2/Z3 Only) ...............3-2

3.1.5 Analog-to-Digital Converter (ADC) ....................................................3-2

3.1.6 Queued Serial Module (QSM) ...........................................................3-2

3.1.7 Multichannel Communication Interface (MCCI) —

(MC68HC16Z4/CKZ4 Only) ..............................................................3-2

3.1.8 General-Purpose Timer (GPT) ..........................................................3-2

3.2 Intermodule Bus ........................................................................................3-2

3.3 System Block Diagram and Pin Assignment Diagrams .............................3-2

3.4 Pin Descriptions ......................................................................................3-11

3.5 Signal Descriptions ..................................................................................3-13

3.6 Internal Register Map ..............................................................................3-16

3.7 Address Space Maps ..............................................................................3-19

SECTION 4

CENTRAL PROCESSOR UNIT

4.1 General ......................................................................................................4-1

4.2 Register Model ..........................................................................................4-1

4.2.1 Accumulators .....................................................................................4-3

4.2.2 Index Registers .................................................................................4-3

4.2.3 Stack Pointer .....................................................................................4-3

4.2.4 Program Counter ...............................................................................4-3

4.2.5 Condition Code Register ...................................................................4-4

4.2.6 Address Extension Register and Address Extension Fields .............4-5

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4.2.7 Multiply and Accumulate Registers ...................................................4-5

4.3 Memory Management ...............................................................................4-5

4.3.1 Address Extension ............................................................................4-6

4.3.2 Extension Fields ................................................................................4-6

4.4 Data Types ................................................................................................4-6

4.5 Memory Organization ................................................................................4-7

4.6 Addressing Modes .....................................................................................4-8

4.6.1 Immediate Addressing Modes ...........................................................4-9

4.6.2 Extended Addressing Modes ..........................................................4-10

4.6.3 Indexed Addressing Modes .............................................................4-10

4.6.4 Inherent Addressing Mode ..............................................................4-10

4.6.5 Accumulator Offset Addressing Mode .............................................4-10

4.6.6 Relative Addressing Modes .............................................................4-10

4.6.7 Post-Modified Index Addressing Mode ............................................4-10

4.6.8 Use of CPU16 Indexed Mode to Replace M68HC11 Direct Mode ..4-11

4.7 Instruction Set .........................................................................................4-11

4.7.1 Instruction Set Summary .................................................................4-11

4.8 Comparison of CPU16 and M68HC11 CPU Instruction Sets ..................4-31

4.9 Instruction Format ...................................................................................4-33

4.10 Execution Model ......................................................................................4-34

4.10.1 Microsequencer ...............................................................................4-35

4.10.2 Instruction Pipeline ..........................................................................4-35

4.10.3 Execution Unit .................................................................................4-35

4.11 Execution Process ...................................................................................4-36

4.11.1 Changes in Program Flow ...............................................................4-36

4.12 Instruction Timing ....................................................................................4-36

4.13 Exceptions ...............................................................................................4-37

4.13.1 Exception Vectors ...........................................................................4-37

4.13.2 Exception Stack Frame ...................................................................4-38

4.13.3 Exception Processing Sequence .....................................................4-39

4.13.4 Types of Exceptions ........................................................................4-39

4.13.4.1 Asynchronous Exceptions .......................................................4-39

4.13.4.2 Synchronous Exceptions .........................................................4-39

4.13.5 Multiple Exceptions .........................................................................4-40

4.13.6 RTI Instruction .................................................................................4-40

4.14 Development Support ..............................................................................4-40

4.14.1 Deterministic Opcode Tracking .......................................................4-40

4.14.1.1 IPIPE0/IPIPE1 Multiplexing .....................................................4-41

4.14.1.2 Combining Opcode Tracking with Other Capabilities ..............4-41

4.14.2 Breakpoints .....................................................................................4-41

4.14.3 Opcode Tracking and Breakpoints ..................................................4-42

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TABLE OF CONTENTS

4.14.4 Background Debug Mode ................................................................4-42

4.14.4.1 Enabling BDM .........................................................................4-42

4.14.4.2 BDM Sources ..........................................................................4-42

4.14.4.3 Entering BDM ..........................................................................4-42

4.14.4.4 BDM Commands .....................................................................4-43

4.14.4.5 Returning from BDM ...............................................................4-43

4.14.4.6 BDM Serial Interface ...............................................................4-44

4.15 Recommended BDM Connection ............................................................4-45

4.16 Digital Signal Processing .........................................................................4-45

SECTION 5

SYSTEM INTEGRATION MODULE

5.1 General ......................................................................................................5-1

5.2 System Configuration ................................................................................5-2

5.2.1 Module Mapping ................................................................................5-2

5.2.2 Interrupt Arbitration ............................................................................5-3

5.2.3 Show Internal Cycles .........................................................................5-3

5.2.4 Register Access ................................................................................5-3

5.2.5 Freeze Operation ..............................................................................5-3

5.3 System Clock ............................................................................................5-4

5.3.1 Clock Sources ...................................................................................5-5

5.3.2 Clock Synthesizer Operation .............................................................5-6

5.3.3 External Bus Clock ..........................................................................5-21

5.3.4 Low-Power Operation ......................................................................5-21

5.4 System Protection ...................................................................................5-24

5.4.1 Reset Status ....................................................................................5-24

5.4.2 Bus Monitor .....................................................................................5-24

5.4.3 Halt Monitor .....................................................................................5-25

5.4.4 Spurious Interrupt Monitor ...............................................................5-25

5.4.5 Software Watchdog .........................................................................5-25

5.4.6 Periodic Interrupt Timer ...................................................................5-27

5.4.7 Interrupt Priority and Vectoring ........................................................5-28

5.4.8 Low-Power STOP Operation ...........................................................5-29

5.5 External Bus Interface .............................................................................5-29

5.5.1 Bus Control Signals .........................................................................5-31

5.5.1.1 Address Bus ............................................................................5-31

5.5.1.2 Address Strobe .......................................................................5-31

5.5.1.3 Data Bus .................................................................................5-31

5.5.1.4 Data Strobe .............................................................................5-31

5.5.1.5 Read/Write Signal ...................................................................5-32

5.5.1.6 Size Signals ............................................................................5-32

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TABLE OF CONTENTS

5.5.1.7 Function Codes .......................................................................5-32

5.5.1.8 Data Size Acknowledge Signals .............................................5-32

5.5.1.9 Bus Error Signal ......................................................................5-33

5.5.1.10 Halt Signal ...............................................................................5-33

5.5.1.11 Autovector Signal ....................................................................5-33

5.5.2 Dynamic Bus Sizing ........................................................................5-33

5.5.3 Operand Alignment .........................................................................5-35

5.5.4 Misaligned Operands ......................................................................5-35

5.5.5 Operand Transfer Cases .................................................................5-35

5.6 Bus Operation .........................................................................................5-36

5.6.1 Synchronization to CLKOUT ...........................................................5-36

5.6.2 Regular Bus Cycle ...........................................................................5-37

5.6.2.1 Read Cycle ..............................................................................5-37

5.6.2.2 Write Cycle ..............................................................................5-38

5.6.3 Fast Termination Cycles ..................................................................5-39

5.6.4 CPU Space Cycles ..........................................................................5-40

5.6.4.1 Breakpoint Acknowledge Cycle ...............................................5-41

5.6.4.2 LPSTOP Broadcast Cycle .......................................................5-42

5.6.5 Bus Exception Control Cycles .........................................................5-43

5.6.5.1 Bus Errors ...............................................................................5-44

5.6.5.2 Double Bus Faults ...................................................................5-45

5.6.5.3 Halt Operation .........................................................................5-45

5.6.6 External Bus Arbitration ...................................................................5-46

5.6.6.1 Show Cycles ...........................................................................5-47

5.7 Reset .......................................................................................................5-48

5.7.1 Reset Exception Processing ...........................................................5-48

5.7.2 Reset Control Logic .........................................................................5-48

5.7.3 Reset Mode Selection .....................................................................5-49

5.7.3.1 Data Bus Mode Selection ........................................................5-50

5.7.3.2 Clock Mode Selection .............................................................5-52

5.7.3.3 Breakpoint Mode Selection .....................................................5-52

5.7.4 MCU Module Pin Function During Reset ........................................5-52

5.7.5 Pin State During Reset ....................................................................5-53

5.7.5.1 Reset States of SIM Pins ........................................................5-54

5.7.5.2 Reset States of Pins Assigned to Other MCU Modules ..........5-54

5.7.6 Reset Timing ...................................................................................5-55

5.7.7 Power-On Reset ..............................................................................5-55

5.7.8 Use of the Three-State Control Pin .................................................5-56

5.7.9 Reset Processing Summary ............................................................5-57

5.7.10 Reset Status Register .....................................................................5-57

5.8 Interrupts .................................................................................................5-58

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5.8.1 Interrupt Exception Processing .......................................................5-58

5.8.2 Interrupt Priority and Recognition ....................................................5-58

5.8.3 Interrupt Acknowledge and Arbitration ............................................5-59

5.8.4 Interrupt Processing Summary ........................................................5-60

5.8.5 Interrupt Acknowledge Bus Cycles ..................................................5-61

5.9 Chip-Selects ............................................................................................5-61

5.9.1 Chip-Select Registers ......................................................................5-63

5.9.1.1 Chip-Select Pin Assignment Registers ...................................5-64

5.9.1.2 Chip-Select Base Address Registers ......................................5-65

5.9.1.3 Chip-Select Option Registers ..................................................5-66

5.9.1.4 PORTC Data Register .............................................................5-67

5.9.2 Chip-Select Operation .....................................................................5-67

5.9.3 Using Chip-Select Signals for Interrupt Acknowledge .....................5-68

5.9.4 Chip-Select Reset Operation ...........................................................5-69

5.10 Parallel Input/Output Ports ......................................................................5-70

5.10.1 Pin Assignment Registers ...............................................................5-70

5.10.2 Data Direction Registers .................................................................5-70

5.10.3 Data Registers .................................................................................5-71

5.11 Factory Test ............................................................................................5-71

SECTION 6

STANDBY RAM MODULE

6.1 SRAM Register Block ................................................................................6-1

6.2 SRAM Array Address Mapping .................................................................6-2

6.3 SRAM Array Address Space Type ............................................................6-2

6.4 Normal Access ..........................................................................................6-2

6.5 Standby and Low-Power Stop Operation ..................................................6-2

6.6 Reset .........................................................................................................6-3

SECTION 7

MASKED ROM MODULE

7.1 MRM Register Block ..................................................................................7-1

7.2 MRM Array Address Mapping ...................................................................7-1

7.3 MRM Array Address Space Type ..............................................................7-2

7.4 Normal Access ..........................................................................................7-2

7.5 Low-Power Stop Mode Operation .............................................................7-3

7.6 ROM Signature ..........................................................................................7-3

7.7 Reset .........................................................................................................7-3

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TABLE OF CONTENTS

SECTION 8

ANALOG-TO-DIGITAL CONVERTER

8.1 General ......................................................................................................8-1

8.2 External Connections ................................................................................8-1

8.2.1 Analog Input Pins ..............................................................................8-2

8.2.2 Analog Reference Pins ......................................................................8-3

8.2.3 Analog Supply Pins ...........................................................................8-3

8.3 Programmer’s Model .................................................................................8-3

8.4 ADC Bus Interface Unit .............................................................................8-3

8.5 Special Operating Modes ..........................................................................8-3

8.5.1 Low-Power Stop Mode ......................................................................8-3

8.5.2 Freeze Mode .....................................................................................8-4

8.6 Analog Subsystem ....................................................................................8-4

8.6.1 Multiplexer .........................................................................................8-4

8.6.2 Sample Capacitor and Buffer Amplifier .............................................8-5

8.6.3 RC DAC Array ...................................................................................8-5

8.6.4 Comparator .......................................................................................8-6

8.7 Digital Control Subsystem .........................................................................8-6

8.7.1 Control/Status Registers ...................................................................8-6

8.7.2 Clock and Prescaler Control ..............................................................8-6

8.7.3 Sample Time .....................................................................................8-7

8.7.4 Resolution .........................................................................................8-7

8.7.5 Conversion Control Logic ..................................................................8-7

8.7.5.1 Conversion Parameters ............................................................8-8

8.7.5.2 Conversion Modes ....................................................................8-8

8.7.6 Conversion Timing ..........................................................................8-12

8.7.7 Successive Approximation Register ................................................8-13

8.7.8 Result Registers ..............................................................................8-13

8.8 Pin Considerations ..................................................................................8-14

8.8.1 Analog Reference Pins ....................................................................8-14

8.8.2 Analog Power Pins ..........................................................................8-14

8.8.3 Analog Supply Filtering and Grounding ...........................................8-16

8.8.4 Accommodating Positive/Negative Stress Conditions .....................8-18

8.8.5 Analog Input Considerations ...........................................................8-19

8.8.6 Analog Input Pins ............................................................................8-21

8.8.6.1 Settling Time for the External Circuit .......................................8-22

8.8.6.2 Error Resulting from Leakage .................................................8-23

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SECTION 9

QUEUED SERIAL MODULE

9.1 General ......................................................................................................9-1

9.2 QSM Registers and Address Map .............................................................9-2

9.2.1 QSM Global Registers .......................................................................9-2

9.2.1.1 Low-Power Stop Mode Operation .............................................9-2

9.2.1.2 Freeze Operation ......................................................................9-3

9.2.1.3 QSM Interrupts ..........................................................................9-3

9.2.2 QSM Pin Control Registers ...............................................................9-4

9.3 Queued Serial Peripheral Interface ...........................................................9-5

9.3.1 QSPI Registers ..................................................................................9-6

9.3.1.1 Control Registers ......................................................................9-6

9.3.1.2 Status Register ..........................................................................9-7

9.3.2 QSPI RAM .........................................................................................9-7

9.3.2.1 Receive RAM ............................................................................9-7

9.3.2.2 Transmit RAM ...........................................................................9-7

9.3.2.3 Command RAM .........................................................................9-8

9.3.3 QSPI Pins ..........................................................................................9-8

9.3.4 QSPI Operation .................................................................................9-8

9.3.5 QSPI Operating Modes .....................................................................9-9

9.3.5.1 Master Mode ...........................................................................9-16

9.3.5.2 Master Wrap-Around Mode .....................................................9-19

9.3.5.3 Slave Mode .............................................................................9-20

9.3.5.4 Slave Wrap-Around Mode .......................................................9-21

9.3.6 Peripheral Chip Selects ...................................................................9-21

9.4 Serial Communication Interface ..............................................................9-21

9.4.1 SCI Registers ..................................................................................9-24

9.4.1.1 Control Registers ....................................................................9-24

9.4.1.2 Status Register ........................................................................9-24

9.4.1.3 Data Register ..........................................................................9-24

9.4.2 SCI Pins ..........................................................................................9-25

9.4.3 SCI Operation ..................................................................................9-25

9.4.3.1 Definition of Terms ..................................................................9-25

9.4.3.2 Serial Formats .........................................................................9-25

9.4.3.3 Baud Clock ..............................................................................9-26

9.4.3.4 Parity Checking .......................................................................9-26

9.4.3.5 Transmitter Operation .............................................................9-27

9.4.3.6 Receiver Operation .................................................................9-28

9.4.3.7 Idle-Line Detection ..................................................................9-29

9.4.3.8 Receiver Wake-Up ..................................................................9-29

9.4.3.9 Internal Loop Mode .................................................................9-30

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SECTION 10

MULTICHANNEL COMMUNICATION INTERFACE

10.1 General ....................................................................................................10-1

10.2 MCCI Registers and Address Map ..........................................................10-2

10.2.1 MCCI Global Registers ....................................................................10-2

10.2.1.1 Low-Power Stop Mode ............................................................10-2

10.2.1.2 Privilege Levels .......................................................................10-3

10.2.1.3 MCCI Interrupts .......................................................................10-3

10.2.2 Pin Control and General-Purpose I/O .............................................10-4

10.3 Serial Peripheral Interface (SPI) ..............................................................10-4

10.3.1 SPI Registers ..................................................................................10-6

10.3.1.1 SPI Control Register (SPCR) ..................................................10-6

10.3.1.2 SPI Status Register (SPSR) ....................................................10-6

10.3.1.3 SPI Data Register (SPDR) ......................................................10-6

10.3.2 SPI Pins ...........................................................................................10-6

10.3.3 SPI Operating Modes ......................................................................10-7

10.3.3.1 Master Mode ...........................................................................10-7

10.3.3.2 Slave Mode .............................................................................10-8

10.3.4 SPI Clock Phase and Polarity Controls ...........................................10-8

10.3.4.1 CPHA = 0 Transfer Format .....................................................10-9

10.3.4.2 CPHA = 1 Transfer Format ...................................................10-10

10.3.5 SPI Serial Clock Baud Rate ..........................................................10-11

10.3.6 Wired-OR Open-Drain Outputs .....................................................10-11

10.3.7 Transfer Size and Direction ...........................................................10-11

10.3.8 Write Collision ...............................................................................10-12

10.3.9 Mode Fault ....................................................................................10-12

10.4 Serial Communication Interface (SCI) ...................................................10-13

10.4.1 SCI Registers ................................................................................10-13

10.4.1.1 SCI Control Registers ...........................................................10-13

10.4.1.2 SCI Status Register ...............................................................10-16

10.4.1.3 SCI Data Register .................................................................10-16

10.4.2 SCI Pins ........................................................................................10-16

10.4.3 Receive Data Pins (RXDA, RXDB) ...............................................10-17

10.4.4 Transmit Data Pins (TXDA, TXDB) ...............................................10-17

10.4.5 SCI Operation ................................................................................10-17

10.4.5.1 Definition of Terms ................................................................10-17

10.4.5.2 Serial Formats .......................................................................10-18

10.4.5.3 Baud Clock ............................................................................10-18

10.4.5.4 Parity Checking .....................................................................10-19

10.4.5.5 Transmitter Operation ...........................................................10-19

10.4.5.6 Receiver Operation ...............................................................10-20

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NEC

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Texas Instruments

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