NXP Semiconductors LPC43 Series Manuel utilisateur

UM10503

LPC43xx ARM Cortex-M4/M0 dual-core microcontroller

Rev. 1.3 — 6 July 2012 User manual

Document information

Info Content

Keywords LPC4350FET256; LPC4350FET180; LPC4350FBD208; LPC4330FET256;

LPC4330FET180; LPC4330FET100; LPC4330FBD144; LPC4320FET100;

LPC4320FBD144; LPC4310FET100; LPC4310FBD144; LPC4357FET256;

LPC4357FET180; LPC4357FBD208; LPC4353FET256; LPC4353FET180;

LPC4353FBD208; LPC43xx, LPC4350, LPC4330, LPC4320, LPC4310,

LPC4357, LPC4353, LPC4337, LPC4333, LPC43Sxx, ARM Cortex-M4, ARM

Cortex-M0, SPIFI, SCT, USB, Ethernet

Abstract LPC4300 user manual

User manual Rev. 1.3 — 6 July 2012 2 of 1269

NXP Semiconductors UM10503

LPC43xx user manual

Revision history

Rev Date Description

1.3 20120706 LPC43xx user manual.

Modifications: •Description of USB CDC device class updated in Section 25.5.26 “USBD_API_INIT_PARAM”and

Section 25.5.27 “USBD_CDC_API”.

•Section 24.7.1 “Susp_CTRL module”added for USB1.

•Section 23.11 “USB power optimization”updated.

•Table 20 “Boot image header use”added.

•AES only available for LPC43Sxx parts.

•Bank, Row, Column addressing for SDRAM devices added in Table 373.

•Parts LPC4337 and LPC4333 added.

1.2 20120608 LPC43xx user manual.

Modifications: •Syncflash removed from Chapter 21.

•Parameter tbupdated in Section 5.3.6.

•Parameters for ISP/IAP command “Copy RAM to flash” updated (Table 1031 and Table 1044).

•Part IDs updated in Table 1036; also see Errata note ES_LPC43X0_A.

•Description of CTRL_DISABLE register updated (see Table 230).

•Table 215 “SGPIO multiplexer” corrected.

•Flash accelerator register waitstate values added (see Table 46 and Table 47).

•Programming procedure for the SDRAM mode register added in Section 21.8.5.

•Clock ramp-up procedures for core clock added in Section 11.2.1.

•Description of the event router updated (see Section 8.3).

User manual Rev. 1.3 — 6 July 2012 3 of 1269

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

NXP Semiconductors UM10503

LPC43xx user manual

1.1 20120510

Modifications: •Reset value of the ETB bit in the ETBCFG register changed to one (see Table 48).

•UART1 FIFOLVL register removed.

•Chapter 46 “LPC43xx flash programming/ISP and IAP” added.

•OTP memory bank 0 changed to reserved.

•Hardware IP checksum feature removed from ethernet block.

•USB frame length adjust register added (see Table 54 and Table 55; for parts with on-chip flash only).

•Flash accelerator control registers added (see Table 46 and Table 47; for parts with on-chip flash

only).

•Support for SAMPLE pin added to the CREG0 register (Table 42).

•Chapter 47 “LPC43xx EEPROM memory” added (for parts with on-chip flash only).

•SDRAM low-power mode removed in Chapter 21.

•Motor control PWM hardware noise filtering removed.

•Description of the QEI register VEL corrected.

•Chapter 41 “LPC43xx I2S interface” updated.

•Remove condition RTC_ALARM = LOW on reset for entering debug mode.

•Ethernet chapter updated: PPS and auxiliary timestamp features removed.

•Chapter 36 “LPC43xx Event monitor/recorder” added (for parts with on-chip flash only).

•Connection of USB0_VBUS/USB1_VBUS signals added (Section 23.5.1).

•Description of ADC GDR register updated (Section 44.6.2).

•Pin reset states updated in Table 128 and Table 129.

•SCT register map updated in Table 645.

•Changed maximum clock frequency for SWD and ETB access to 120 MHz in Chapter 48.

•Reduced and normal power modes removed in Chapter 10.

•AES encryption option added in Table 22 (parts LPC43Sxx only).

•SGPIO register names and descriptions updated.

•Update description of bit 0 in the USBSTS_D and bit 5:0 in ENDPTCOMPLETE registers of USB0/1.

•Update procedure Section 23.10.8.1.2 “Setup packet handling using the trip wire mechanism”.

•Polarity of bit OUTSEL in the SCT EVCTRL register swapped (see Table 670).

•Bit 9 (JTAG enable for the M0 co-processor) added to the CREG5 register (Table 44).

•Description of CCU Auto mode updated (see Section 12.5.3).

•LQFP100 package removed.

•Maximum power consumption in the USB Suspended state corrected according to USB 2.0 ECN

specification (see Section 23.11.2).

1 20111212 Preliminary LPC43xx user manual.

Revision history …continued

Rev Date Description

User manual Rev. 1.3 — 6 July 2012 4 of 1269

1.1 Introduction

The LPC43xx are ARM Cortex-M4 based microcontrollers for embedded applications

which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash, up to 264 kB of

SRAM, advanced configurable peripherals such as the State Configurable Timer (SCT)

and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,

Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.

The LPC43xx operate at CPU frequencies of up to 204 MHz.

The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements

such as low power consumption, enhanced debug features, and a high level of support

block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a

Harvard architecture with separate local instruction and data buses as well as a third bus

for peripherals, and includes an internal prefetch unit that supports speculative branching.

The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD

instructions. A hardware floating-point processor is integrated in the core.

The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which

is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor,

designed as a replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz

performance with a simple instruction set and reduced code size.

1.2 Features

•Cortex-M4 Processor core

–ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.

–ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.

–ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).

–Hardware floating-point unit.

–Non-maskable Interrupt (NMI) input.

–JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four

watch points.

–Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

–System tick timer.

•Cortex-M0 Processor core

–ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4

application processor.

–Running at frequencies of up to 204 MHz.

–JTAG, Serial Wire Debug, and built-in NVIC.

•On-chip memory (flashless parts)

–Up to 264 kB SRAM for code and data use.

UM10503

Chapter 1: Introductory information

Rev. 1.3 — 6 July 2012 User manual

User manual Rev. 1.3 — 6 July 2012 5 of 1269

NXP Semiconductors UM10503

Chapter 1: Introductory information

–Multiple SRAM blocks with separate bus access. Two SRAM blocks can be

powered down individually.

–64 kB ROM containing boot code and on-chip software drivers.

–32 bit general-purpose One-Time Programmable (OTP) memory.

•On-chip memory (parts with on-chip flash)

–Up to 1 MB on-chip dual bank flash memory with flash accelerator.

–16 kB on-chip EEPROM data memory.

–136 kB SRAM for code and data use.

–Multiple SRAM blocks with separate bus access. Two SRAM blocks can be

powered down individually.

–64 kB ROM containing boot code and on-chip software drivers.

–128 bit general-purpose One-Time Programmable (OTP) memory.

•Configurable digital peripherals

–Serial GPIO (SGPIO) interface.

–State Configurable Timer (SCT) subsystem on AHB.

–Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and

outputs to event driven peripherals like the timers, SCT, and ADC0/1.

•Serial interfaces

–Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 60 MB

per second.

–10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping and advanced

time stamping (IEEE 1588-2008 v2).

–One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip high-speed PHY.

–One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY.

–USB interface electrical test software included in ROM USB stack.

–One 550 UART with DMA support and full modem interface.

–Three 550 USARTs with DMA and synchronous mode support and a smart card

interface conforming to ISO7816 specification. One USART with IrDA interface.

–Two C_CAN 2.0B controllers with one channel each.

–Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

–One SPI controller.

–One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I2C-bus specification. Supports data rates of up to

1 Mbit/s.

–One standard I2C-bus interface with monitor mode and with standard I/O pins.

–Two I2S interfaces, each with DMA support and with one input and one output.

User manual Rev. 1.3 — 6 July 2012 6 of 1269

NXP Semiconductors UM10503

Chapter 1: Introductory information

•Digital peripherals

–External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,

and SDRAM devices.

–LCD controller with DMA support and a programmable display resolution of up to

1024H 768V. Supports monochrome and color STN panels and TFT color

panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel

mapping.

–Secure Digital Input Output (SD/MMC) card interface.

–Eight-channel General-Purpose DMA (GPDMA) controller can access all

memories on the AHB and all DMA-capable AHB slaves.

–Up to 164 General-Purpose Input/Output (GPIO) pins with configurable

pull-up/pull-down resistors.

–GPIO registers are located on the AHB for fast access. GPIO ports have DMA

support.

–Up to eight GPIO pins can be selected from all GPIO pins as edge and level

sensitive interrupt sources.

–Two GPIO group interrupt modules enable an interrupt based on a programmable

pattern of input states of a group of GPIO pins.

–Four general-purpose timer/counters with capture and match capabilities.

–One motor control Pulse Width Modulator (PWM) for three-phase motor control.

–One Quadrature Encoder Interface (QEI).

–Repetitive Interrupt timer (RI timer).

–Windowed watchdog timer (WWDT).

–Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes

of battery powered backup registers.

–(Parts with on-chip flash only): Event recorder with three inputs to record event

identification and event time; can be battery powered.

–Alarm timer; can be battery powered.

•Analog peripherals

–One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.

–Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.

Up to eight input channels per ADC.

•Security (LPC43Sxx only)

–AES decryption programmable through an on-chip API.

–Two 128-bit secure OTP memories for AES key storage and customer use.

–Random number generator (RNG) accessible through AES API.

–Unique ID for each device.

•Clock generation unit

–Crystal oscillator with an operating range of 1 MHz to 25 MHz.

–12 MHz Internal RC (IRC) oscillator trimmed to 1 % accuracy over temperature

and voltage.

User manual Rev. 1.3 — 6 July 2012 7 of 1269

NXP Semiconductors UM10503

Chapter 1: Introductory information

–Ultra-low power Real-Time Clock (RTC) crystal oscillator.

–Three PLLs allow CPU operationup to the maximum CPU rate without the need for

a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the

third PLL can be used as audio PLL.

–Clock output.

•Power

–Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip DC-to-DC converter for the

core supply and the RTC power domain.

–RTC power domain can be powered separately by a 3 V battery supply.

–Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep

power-down.

–Processor wake-up from Sleep mode via wake-up interrupts from various

peripherals.

–Wake-up from Deep-sleep, Power-down, and Deep power-down modes via

external interrupts and interrupts generated by battery powered blocks in the RTC

power domain.

–Brownout detect with four separate thresholds for interrupt and forced reset.

–Power-On Reset (POR).

–Available as LBGA256, TFBGA180, and TFBGA100 packages and as LQFP208

and LQFP144 packages.

1.3 Ordering information (flashless parts LPC4350/30/20/10)

Table 1. Ordering information

Type number Package

Name Description Version

LPC4350FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2

LPC4350FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3

LPC4350FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1

LPC4330FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2

LPC4330FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3

LPC4330FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1

LPC4330FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1

LPC4320FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1

LPC4320FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1

LPC4310FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1

LPC4310FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1

User manual Rev. 1.3 — 6 July 2012 8 of 1269

NXP Semiconductors UM10503

Chapter 1: Introductory information

1.4 Ordering information (parts with on-chip flash)

Table 2. Ordering options

Type number Total

SRAM LCD Ethernet USB0

(Host,

Device,

OTG)

USB1

(Host,

Device)/

ULPI

interface

ADC

channels PWM QEI GPIO Package

LPC4350FET256 264 kB yes yes yes yes/yes 8 yes yes 164 LBGA256

LPC4350FET180 264 kB yes yes yes yes/yes 8 yes yes 118 TFBGA180

LPC4350FBD208 264 kB yes yes yes yes/yes 8 yes yes 142 LQFP208

LPC4330FET256 264 kB no yes yes yes/yes 8 yes yes 164 LBGA256

LPC4330FET180 264 kB no yes yes yes/yes 8 yes yes 118 TFBGA180

LPC4330FET100 264 kB no yes yes yes/no 4 no no 49 TFBGA100

LPC4330FBD144 264 kB no yes yes yes/no 8 yes no 83 LQFP144

LPC4320FET100 200 kB no no yes no 4 no no 49 TFBGA100

LPC4320FBD144 200 kB no no yes no 8 yes no 83 LQFP144

LPC4310FET100 168 kB no no no no 4 no no 49 TFBGA100

LPC4310FBD144 168 kB no no no no 8 yes no 83 LQFP144

Table 3. Ordering information

Type number Package

Name Description Version

LPC4357FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2

LPC4357FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3

LPC4357FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1

LPC4353FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2

LPC4353FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3

LPC4353FBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1

LPC4337FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2

LPC4337FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3

LPC4337FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1

LPC4337FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1

LPC4333FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2

LPC4333FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3

LPC4333FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1

LPC4333FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1

User manual Rev. 1.3 — 6 July 2012 9 of 1269

NXP Semiconductors UM10503

Chapter 1: Introductory information

Table 4. Ordering options

Type number Flash Flash

bank A Flash

bank B Total

SRAM LCD Ethernet USB0

(Host,

Device,

OTG)

USB1

(Host,

Device)/

ULPI

interface

ADC

channels GPIO

LPC4357FET256 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 164

LPC4357FET180 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 118

LPC4357FBD208 1 MB 512 kB 512 kB 136 kB yes yes yes yes/yes 8 142

LPC4353FET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 164

LPC4353FET180 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 118

LPC4353FBD208 512 kB 256 kB 256 kB 136 kB yes yes yes yes/yes 8 142

LPC4337FET256 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes 8 164

LPC4337FET180 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes 8 118

LPC4337FET100 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes 4 49

LPC4337FBD144 1 MB 512 kB 512 kB 136 kB no yes yes yes/yes 8 83

LPC4333FET256 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes 8 164

LPC4333FET180 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes 8 118

LPC4333FET100 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes 4 49

LPC4333FBD144 512 kB 256 kB 256 kB 136 kB no yes yes yes/yes 8 83

User manual Rev. 1.3 — 6 July 2012 10 of 1269

NXP Semiconductors UM10503

Chapter 1: Introductory information

1.5 Block diagram (flashless parts)

AES is supported for LPC43Sxx parts only.

Fig 1. LPC43xx Block diagram (flashless parts)

ARM

CORTEX-M4

TEST/DEBUG

INTERFACE

I-code bus

D-code bus

system bus

GPDMA LCD(1) SD/

MMC

ETHERNET(1)

10/100

MAC

IEEE 1588

HIGH-SPEED

USB0(1)

HOST/

DEVICE/OTG

HIGH-SPEED

USB1(1)

HOST/DEVICE

EMC

HIGH-SPEED PHY

32 kB AHB SRAM

16 +16 kB AHB SRAM

SPIFI

AES

HS GPIO

SPI

SGPIO

SCT

64 kB ROM

I2C0

I2S0

I2S1

C_CAN1

MOTOR

CONTROL

PWM(1)

TIMER3

TIMER2

USART2

USART3

SSP1

RI TIMER

QEI(1)

GIMA

BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE

AHB MULTILAYER MATRIX

LPC4350/30/20/10

128 kB LOCAL SRAM

72 kB LOCAL SRAM

10-bit ADC0

10-bit ADC1

C_CAN0

I2C1

10-bit DAC

BRIDGE

RGU

CCU2

CGU

CCU1

ALARM TIMER

CONFIGURATION

REGISTERS

OTP MEMORY

EVENT ROUTER

POWER MODE CONTROL

12 MHz IRC

RTC POWER DOMAIN

BACKUP REGISTERS

RTC OSC

RTC

002aaf772

slaves

masters

ARM

CORTEX-M0

TEST/DEBUG

INTERFACE

= connected to GPDMA

GPIO

INTERRUPTS

GPIO GROUP0

INTERRUPT

GPIO GROUP1

INTERRUPT

WWDT

USART0

UART1

SSP0

TIMER0

TIMER1

SCU

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