Infineon XMC4000 series Manuel utilisateur

Microcontroller

XMC4000

XMC4000 Family

User Guide

Device Guide

POSI F in Triple -Hall Mode

Triple-Hall Commutation Control for BLDC Motors

Edition <201-08-06>

Published by

Infineon Technologies AG

81726 Munich, Germany

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Device Guide XMC4000

Template: IFX_Template_2011-02-24.dot

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Last Trademarks Update 2011-02-24

Device Guide XMC4000

Table of Contents

User Guide 4 <Revision 1.0>, <201-08-06>

Device Guide

Table of Contents

1Triple-Hall Commutation Control for BLDC Motors.....................Fehler! Textmarke nicht definiert.

2Triple-Hall Input Pattern ....................................................................................................................7

2.1 Delayed Hall Input Sampling................................................................................................................7

2.1.1 Shadow Update of Expected Patterns .................................................................................................8

2.2 Verification of Hall Event Input Patterns ..............................................................................................8

2.2.1 Hall Event Verification Outputs ............................................................................................................8

2.3 Administration (Shadow Transfer) of Pattern Compare Values...........................................................9

2.4 Output Pattern Control .........................................................................................................................9

3Triple-Hall Output Pattern for BLDC Motor Commutation Control ...............................................9

3.1 Output Pattern Control by CAPCOM Slices in Multi-Channel Mode....................................................9

3.2 Output Pattern Control by CAPCOM Slices in External Modulation Mode ........................................10

4POSIF Interrupt Registers ...............................................................................................................12

4.1 POSIF interrupts/event requests in Hall Sensor Mode ......................................................................12

4.2 POSIF Interrupts/Event requests in Multi-Channel Mode ..................................................................12

5Getting Started with POSIF in Triple-Hall Mode............................................................................13

5.1 POSIF Global Registers .....................................................................................................................13

5.2 POSIF Setup when using Hall Sensor Mode .....................................................................................13

5.3 POSIF Setup when using Multi-Channel features in Hall Sensor Mode............................................13

5.4 POSIF Input Selections in Hall Sensor Mode ....................................................................................13

5.5 POSIF Operation Mode Associated Registers...................................................................................13

5.5.1 POSIF Associated Configurations of CCU4x/-8x Timers...................................................................13

5.5.2 POSIF Synchronized Start of Timers by HW Initialization .................................................................13

5.5.3 POSIF Optional Setup Selections in Hall Mode.................................................................................13

5.6 Timer Setup........................................................................................................................................14

5.6.1 Ultimate Initialization Sequence .........................................................................................................14

5.6.2 Ultimate Start-Up Enable ...................................................................................................................14

5.6.3 Setting the Timer Counting Modes.....................................................................................................14

5.6.4 Setting Compare Mode Control..........................................................................................................14

5.6.5 Setting the Output Pins PASSIVE / ACTIVE Level Control ...............................................................14

5.6.6 External Events Control Setup Registers...........................................................................................14

5.6.7 Multi-Channel Mode Enable...............................................................................................................14

5.6.8 Multi-Channel Synchronization to Shadow Transfers ........................................................................15

5.7 Using the POSIF Global Registers for Hall Sensor Mode Setup .......................................................15

5.8 Using the POSIF Global and Multi-Channel (MC) Mode Setup Registers.........................................15

5.9 Using the Timer Control Registers for COMPARE Mode ..................................................................15

5.10 Using the Timer Control Registers for MULTI-CHANNEL Mode .......................................................18

5.11 Using the Timer Control Registers for EXTERNAL MODULATION Mode ........................................18

5.11.1 Using the Register Bitfields for EXTERNAL EVENTS CONTROL ....................................................18

5.11.2 Using the External Events Control Registers for START...................................................................18

Device Guide XMC4000

List of Figures

User Guide 5 <Revision 1.0>, <201-08-06>

Device Guide

List of Figures

Figure 1 BLDC Motor Control with Triple-Hall Commutation .............................................................................6

Figure 2 The Triple-Hall Input Samples stage for a BLDC Motor Commutation Control ...................................7

Figure 3 Triple-Hall Input Samples Edge Detection ...........................................................................................7

Figure 4 Triple-Hall Input Samples Verification and Administration of Expected Samples................................8

Figure 5 Triple-Hall BLDC Motor Commutation Control using CAPCOM units in Multi-Channel Mode ..........10

Figure 6 Triple-Hall BLDC Motor Commutation Control by CAPCOM:s in External Modulation Mode ...........11

Device Guide XMC4000

Triple-Hall Communication Control for BLDC Motors

User Guide 6 <Revision 1.0>, <201-08-06>

Device Guide

1 Triple-Hall Communication Control for BLDC Motors

The POSIF module is a universal Position Interface unit. In conjunction with the CAPCOM units CCU4 or CCU8

it offers powerful solutions for motion control systems that use various position sensors or rotary encoders in the

feedback loop. The POSIF Hall Sensors Decoder is one of its main subunits, dedicated for BLDC motor control.

Figure 1 BLDC Motor Control with Triple-Hall Commutation

Device Guide XMC4000

Triple-Hall Input Pattern

User Guide 7 <Revision 1.0>, <201-08-06>

Device Guide

2 Triple-Hall Input Pattern

The Hall Sensor Decoder mode operates in four succesiev stages: 1) The Hall Input Samples stage for the

commutation signals, 2) the Detection & Delay stage for the inputs sampling after any edge transition, 3) the

Verification & Administration stage of expected Hall Patterns and 4) the Output Pattern Control &HW protocol.

Figure 2 The Triple-Hall Input Samples stage for a BLDC Motor Commutation Control

2.1 Delayed Hall Input Sampling

The sampling of each Hall Input pattern can be delayed a certain time after an input transition edge is detected,

in order to reject noise that might appear at these positions. The Input Edge Detection output POSIFx.OUT0 has

to start a CCU4/8 timer that after a certain time triggers the sampling via a selected input: POSIFx.HSD[B...A].

Figure 3 Triple-Hall Input Samples Edge Detection

Device Guide XMC4000

Triple-Hall Input Pattern

User Guide 8 <Revision 1.0>, <201-08-06>

Device Guide

2.1.1 Shadow Update of Expected Patterns

After each occurrence and sampling of a new pattern (Samplen) by the delayed Sample Trigger (ST) and an

event verification by a Hall Event Compare, there should be a Service Request (SR) to Shadow Update the next

(Expectedn+1) pattern. An update path could be a DMA transfer, on the falling edge of the Sample Trigger (ST).

2.2 Verification of Hall Event Input Patterns

See Figure 4.

Each Hall Input pattern (Samplen) is compared to the current pattern (Currentn) and also to the expected pattern

(Expectedn) - by the PIFHRDY trigger. The comparison results will be interpretated: “Hall Glitch”(==Currentn),

“Correct Hall Event (CHE)” (==Expectedn) or “Wrong Hall Event (WHE)”, if (Samplen) is equal to none of those.

Figure 4 Triple-Hall Input Samples Verification and Administration of Expected Samples

2.2.1 Hall Event Verification Outputs

Correct Hall Event (CHE), linked to POSIFx.OUT1, triggers Shadow Transfer of Currentn+1 and Expectedn+1.

Wrong Hall Event (WHE), linked to POSIFx.OUT2, can be used for IDLE control or STOP Run Bit / PWM.

Glitch Hall Event or Wrong Hall Event, both events linked to POSIFx.OUT3, will generate a STOP signal.

Device Guide XMC4000

Triple-Hall Output Pattern for BLDC Motor Commutation Control

User Guide 9 <Revision 1.0>, <201-08-06>

Device Guide

2.3 Administration (Shadow Transfer) of Pattern Compare Values

On each successful “Correct Hall Event (CHE)” there is a Shadow Transfer of the next pattern compare values:

The compare registers “CurrentnPattern” (HALP.HCP) and “ExpectednPattern” (HALP.HEP) are reloaded from

the “Currentn+1“ / “Expectedn+1”shadow registers (HALP.HCPS / HALP.HEPS) that are shadow updated by SW.

2.4 Output Pattern Control

The Multi-Channel-Mode Pattern register MCM.MCMP is linked to the output POSIFx.MOUT[15:0]. Its value will

be updated from the shadow register MCSM.MCMPS by shadow transfer on the Multi-Channel update trigger

PIFMST - i.e. the MC Pattern Update Request POSIFx.OUT6 & Pattern Update Sync POSIFx.MSYNC[D…A].

See Figure 5.

3 Triple-Hall Output Pattern for BLDC Motor Commutation Control

The POSIF module in conjunction with CAPCOM units in multi-channel mode (or in external modulation mode)

enables complete synchronicity between the output state update and the application of a new pattern. This can

be used in Hall Sensor Mode for the direct drive of brushless DC motors with the wanted motor control patterns.

3.1 Output Pattern Control by CAPCOM Slices in Multi-Channel Mode

See Figure 5.

A CCU4/8OUT-pin output level of any slice that has been set in multichannel mode (CC4/8yTC.MCME = 1B),

can be &-controlled in parallel by an external level that is present on its Multi-Channel Input MCI-pin. To get it all

synchronized, a Set Shadow Transfer Enable MCSS and a Pattern Set PSy request complete the HW protocol.

Device Guide XMC4000

Triple-Hall Output Pattern for BLDC Motor Commutation Control

User Guide 10 <Revision 1.0>, <201-08-06>

Device Guide

Figure 5 Triple-Hall BLDC Motor Commutation Control using CAPCOM units in Multi-Channel Mode

3.2 Output Pattern Control by CAPCOM Slices in External Modulation Mode

See Figure 6.

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