Cypress Semiconductor EZ-Host CY7C67300 Manuel utilisateur

CY7C67300

EZ-Host™ Programmable Embedded USB Host and

Peripheral Controller with Automotive AEC Grade Support

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-08015 Rev. *J Revised July 28, 2008

EZ-Host Features

■Single chip programmable USB dual-role (Host/Peripheral)

controllerwithtwoconfigurableSerialInterfaceEngines(SIEs)

and four USB ports

■Support for USB On-The-Go (OTG) protocol

■On-chip 48 MHz 16-bit processor with dynamically switchable

clock speed

■Configurable IO block supporting a variety of IO options or up

to 32 bits of General Purpose IO (GPIO)

■4K x 16 internal masked ROM containing built in BIOS that

supports a communication ready state with access to I2C™

EEPROM Interface, external ROM, UART, or USB

■8K x 16 internal RAM for code and data buffering

■Extended memory interface port for external SRAM and ROM

■16-bit parallel Host Port Interface (HPI) with a DMA/mailbox

data path for an external processor to directly access all of the

on-chip memory and control on-chip SIEs

■Fast serial port supports from 9600 baud to 2.0M baud

■SPI support in both master and slave

■On-chip 16-bit DMA/mailbox data path interface

■Supports 12 MHz external crystal or clock

■3.3V operation

■Automotive AEC grade option (–40°C to 85°C)

■Package option—100-pin TQFP

Typical Applications

EZ-Host is a very powerful and flexible dual role USB controller

that supports a wide variety of applications. It is primarily

intended to enable host capability in applications such as:

■Set top boxes

■Printers

■KVM switches

■Kiosks

■Automotive applications

■Wireless access points

Timer 0 Timer 1

Watchdog

Control

4Kx16

ROM BIOS 8Kx16

RAM

CY16

16-bit RISC CORE

External MEM I/F

(SRAM/ROM)

SIE1

USB-A

USB-B

SIE2

USB-A

USB-B

OTG

Host/

Peripheral

USB Ports

D+,D-

UART I/F

PWM

HSS I/F

I2C

EEPROM I/F

HPI I/F

IDE I/F

SPI I/F

nRESET

A[15:0] D[15:0] CTRL[9:0]

CY7C67300

GPIO [31:0]

PLL

GPIO

SHARED INPUT/OUTPUT PINS

Vbus, ID

Mobile

Power

Booster

CY7C67300 Block Diagram

[+] Feedback

CY7C67300

Document #: 38-08015 Rev. *J Page 2 of 99

Introduction

EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first

full-speed, low cost multiport host/peripheral controller. EZ-Host

is designed to easily interface to most high performance CPUs

to add USB host functionality. EZ-Host has its own 16-bit RISC

processor to act as a coprocessor or operate in standalone

mode. EZ-Host also has a programmable IO interface block

allowing a wide range of interface options.

Functional Overview

An overview of the processor core components are presented in

this section.

Processor Core

EZ-Host has a general purpose 16-bit embedded RISC

processor that runs at 48 MHz.

Clocking

EZ-Host requires a 12 MHz source for clocking. Either an

external crystal or TTL level oscillator may be used. EZ-Host has

an internal PLL that produces a 48 MHz internal clock from the

12 MHz source.

Memory

EZ-Host has a built in 4K × 16 masked ROM and an 8K × 16

internal RAM. The masked ROM contains the EZ-Host BIOS.

The internal RAM can be used for program code or data.

Interrupts

EZ-Host provides 128 interrupt vectors. The first 48 vectors are

hardware interrupts and the following 80 vectors are software

interrupts.

General Timers and Watchdog Timer

EZ-Host has two built in programmable timers and a Watchdog

timer. All three timers can generate an interrupt to the EZ-Host.

Power Management

EZ-Host has one main power saving mode, Sleep. Sleep mode

pauses all operations and provides the lowest power state.

Interface Descriptions

EZ-Host has a wide variety of interface options for connectivity.

With several interface options available, EZ-Host can act as a

seamless data transport between many different types of

devices.

See Table 1 and Table 2 on page 3 to understand how the inter-

faces share pins and which can coexist. Note that some inter-

faces have more then one possible port location selectable

through the GPIO control register [0xC006]. General guidelines

for interfaces are as follows:

■HPI and IDE interfaces are mutually exclusive.

■If16-bitexternalmemoryisrequired,thenHSSandSPIdefault

locations must be used.

■I2C EEPROM and OTG do not conflict with any interfaces.

Note

1. Default interface location.

Table 1. Interface Options for GPIO Pins

GPIO Pins HPI IDE PWM HSS SPI UART I2C OTG

GPIO31 SCL/SDA

GPIO30 SCL/SDA

GPIO29 OTGID

GPIO28 TX

GPIO27 RX

GPIO26 PWM3 CTS[1]

GPIO25

GPIO24 INT IOREADY

GPIO23 nRD IOR

GPIO22 nWR IOW

GPIO21 nCS

GPIO20 A1 CS1

GPIO19 A0 CS0

GPIO18 A2 PWM2 RTS[1]

GPIO17 A1 PWM1 RXD[1]

GPIO16 A0 PWM0 TXD[1]

GPIO15 D15 D15

GPIO14 D14 D14

GPIO13 D13 D13

GPIO12 D12 D12

GPIO11 D11 D11 MOSI[1]

[+] Feedback

CY7C67300

Document #: 38-08015 Rev. *J Page 3 of 99

USB Interface

EZ-Host has two built in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and

low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control, interrupt, bulk,

and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with eight endpoints for each of the two SIEs.

Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support interrupt, bulk (up

to 64 bytes/packet), or isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combination of Host and

Peripheral ports simultaneously as shown in Table 3.

GPIO10 D10 D10 SCK[1]

GPIO9 D9 D9 nSSI[1]

GPIO8 D8 D8 MISO[1]

GPIO7 D7 D7

GPIO6 D6 D6

GPIO5 D5 D5

GPIO4 D4 D4

GPIO3 D3 D3

GPIO2 D2 D2

GPIO1 D1 D1

GPIO0 D0 D0

Table 1. Interface Options for GPIO Pins (continued)

GPIO Pins HPI IDE PWM HSS SPI UART I2C OTG

Note

2. Alternate interface location.

Table 2. Interface Options for External Memory Bus Pins

MEM Pins HPI IDE PWM HSS SPI UART I2C OTG

D15 CTS[2]

D14 RTS[2]

D13 RXD[2]

D12 TXD[2]

D11 MOSI[2]

D10 SCK[2]

D9 nSSI[2]

D8 MISO[2]

D[7:0]

A[18:0]

CONTROL

Table 3. USB Port Configuration Options

Port Configurations Port 1A Port 1B Port 2A Port 2B

OTG OTG – – –

OTG + 2 Hosts OTG – Host Host

OTG + 1 Host OTG – Host –

OTG + 1 Host OTG – – Host

OTG + 1 Peripheral OTG – Peripheral –

OTG + 1 Peripheral OTG – – Peripheral

4 Hosts Host Host Host Host

3 Hosts Any Combination of Ports

2 Hosts Any Combination of Ports

1 Host Any Port

[+] Feedback

CY7C67300

Document #: 38-08015 Rev. *J Page 4 of 99

USB Features

■USB 2.0-compliant for full and low speed

■Up to four downstream USB host ports

■Up to two upstream USB peripheral ports

■Configurableendpointbuffers(pointerandlength),mustreside

in internal RAM

■Up to eight available peripheral endpoints (one control

endpoint)

■Supports control, interrupt, bulk, and isochronous transfers

■Internal DMA channels for each endpoint

■Internal pull up and pull down resistors

■Internal series termination resistors on USB data lines

USB Pins

OTG Interface

EZ-Host has one USB port that is compatible with the USB

On-The-Go supplement to the USB 2.0 specification. The USB

OTG port has a various hardware features to support Session

Request Protocol (SRP) and Host Negotiation Protocol (HNP).

OTG is only supported on USB PORT 1A.

OTG Features

■Internal charge pump to supply and control VBUS

■VBUS valid status (above 4.4V)

■VBUS status for 2.4V< VBUS <0.8V

■ID pin status

■Switchable 2K ohm internal discharge resistor on VBUS

■Switchable 500 ohm internal pull up resistor on VBUS

■Individually switchable internal pull up and pull down resistors

on the USB data lines

OTG Pins

2 Hosts + 1 Peripheral Host Host Peripheral –

2 Hosts + 1 Peripheral Host Host – Peripheral

2 Hosts + 1 Peripheral Peripheral – Host Host

2 Hosts + 1 Peripheral – Peripheral Host Host

1 Host + 1 Peripheral Host – Peripheral –

1 Host + 1 Peripheral Host – – Peripheral

1 Host + 1 Peripheral – Host – Peripheral

1 Host + 1 Peripheral – Host Peripheral –

1 Host + 1 Peripheral Peripheral – Host –

1 Host + 1 Peripheral Peripheral – – Host

1 Host + 1 Peripheral – Peripheral – Host

1 Host + 1 Peripheral – Peripheral Host –

2 Peripherals Peripheral – Peripheral –

2 Peripherals Peripheral – – Peripheral

2 Peripherals – Peripheral – Peripheral

2 Peripherals – Peripheral Peripheral –

1 Peripheral Any Port

Table 3. USB Port Configuration Options (continued)

Port Configurations Port 1A Port 1B Port 2A Port 2B

Table 4. USB Interface Pins

Pin Name Pin Number

DM1A 22

DP1A 23

DM1B 18

DP1B 19

DM2A 9

DP2A 10

DM2B 4

DP2B 5

Table 5. OTG Interface Pins

Pin Name Pin Number

DM1A 22

DP1A 23

OTGVBUS 11

OTGID 41

CSwitchA 13

CSwitchB 12

[+] Feedback

CY7C67300

Document #: 38-08015 Rev. *J Page 5 of 99

External Memory Interface

EZ-Host provides a robust interface to a wide variety of external

memory arrays. All available external memory array locations

can contain either code or data. The CY16 RISC processor

directly addresses a flat memory space from 0x0000 to 0xFFFF.

External Memory Interface Features

■Supports 8-bit or 16-bit SRAM or ROM

■SRAM or ROM can be used for code or data space

■Direct addressing of SRAM or ROM

■Two external memory mapped page registers

External Memory Access Strobes

Access to external memory is sampled asynchronously on the

rising edge of strobes with a minimum of one wait state cycle. Up

to seven wait state cycles may be inserted for external memory

access. Each additional wait state cycle stretches the external

memory access time by 21 ns (you must be running in internal

memorywhen changing wait states). An external memory device

with 12 ns access time is necessary to support 48 MHz code

execution.

Page Registers

EZ-Host allows extended data or program code to be stored in

external SRAM, or ROM. The total size of extended memory can

be up to 512K bytes. The CY16 processor can access extended

memory via two address regions of 0x8000-0x9FFF and

0xA000-0xBFFF. The page register 0xC018 can be used to

control the addressregion0x8000-0x9FFF andthepageregister

0xC01A controls the address region of 0xA000-0xBFFF.

Figure 1 illustrates that when the nXMEMSEL pin is asserted the

upper CPU address pins are driven by the contents of the Page

x registers.

Merge Mode

Merge modes enabled through the External Memory Control

accordance with the following:

■nXMEMSEL is active from 0x8000 to 0xBFFF

■nXRAMSELisactivefrom0x4000to0x7FFFwhenRAMMerge

isdisabled;nXRAMSELisactivefrom0x4000to0xBFFFwhen

RAM Merge is enabled

■nXROMSEL is active from 0xC100 to 0xDFFF when ROM

Merge is disabled; nXROMSEL is active from 0x8000 to

0xDFFF (excluding the 0xC000 to 0xC0FF area) when ROM

Merge is enabled

Program Memory Hole Description

Code residing in the 0xC000-0xC0FF address space is not

accessible by the CPU.

DMA to External Memory Prohibited

EZ-Host supports an internal DMA engine to rapidly move data

between different functional blocks within the chip. This DMA

engine is used for SIE1, SIE2, HPI, SPI, HSS, and IDE but it can

only transfer data between the specified block and internal RAM

or ROM. Setting up the DMA engine to transfer to or from an

external memory space might result in internal RAM data

corruption because the hardware (for example,

HSS/HPI/SIE1/SIE2/IDE) does not explicitly check the address

range. For example, setting up a DMA transfer to external

address 0x8000 might result in a DMA transfer into address

0x0000.

External Memory Related Resource Considerations:

■By default A[18:15] are not available for general addressing

and are driven high on power up. The Upper Address Enable

general addressing purposes.

■47K ohm external pull up on pin A15 for 12 MHz crystal

operation.

■During the 3 ms BIOS boot procedure the CPU external

memory bus is active.

■ROM boot load value 0xC3B6 located at 0xC100.

■HPI, HSS, SPI, SIE1, SIE2, and IDE cannot DMA to external

memory arrays.

■Page 1 banking is always enabled and is in effect from 0x8000

to 0x9FFF.

■Page2 banking isalwaysenabled and isineffectfrom 0xA000

to 0xBFFF.

■CPU memory bus strobes may wiggle when chip selects are

inactive.

Figure 1. Page n Registers External Address Pins Logic

0000 + PC[14:0] 1

PAGEx Register[5:0] + PC[12:0]

nXMEMSEL Pin

A[18:0]

PC = Program Counter

x = 1 or 2

A = CPU Address Bus

Where:

PAGE 1 Register Active Range = 8000h to 9FFFh

PAGE 2 Register Active Range = A000h to BFFFh

Note:

nXMEMSEL Pin Active Range = 8000h to BFFFh

[+] Feedback

CY7C67300

Document #: 38-08015 Rev. *J Page 6 of 99

External Memory Interface Pins

External Memory Interface Block Diagrams

Figure 2 illustrates how to connect a 64k × 8 memory array

(SRAM/ROM) to the EZ-Host external memory interface.

Figure 3 illustrates the interface for connecting a 16-bit ROM or

16-bit RAM to the EZ-Host external memory interface. In 16-bit

mode, up to 256K words of external ROM or RAMare supported.

Note that the address lines do not map directly.

Table 6. External Memory Interface Pins

Pin Name Pin Number

nWR 64

nRD 62

nXMEMSEL (optional nCS) 34

nXROMSEL (ROM nCS) 35

nXRAMSEL (RAM nCS) 36

A18 95

A17 96

A16 97

A15 38

A14 33

A13 32

A12 31

A11 30

A10 27

A9 25

A8 24

A7 20

A6 17

A5 8

A4 7

A3 3

A2 2

A1 1

nBEL/A0 99

nBEH 98

D15 67

D14 68

D13 69

D12 70

D11 71

D10 72

D9 73

D8 74

D7 76

D6 77

D5 78

D4 79

D3 80

D2 81

D1 82

D0 83

Figure 2. Interfacing to 64k × 8 Memory Array

Figure 3. Interfacing up to 256k × 16 for External Code/Data

Table 6. External Memory Interface Pins (continued)

Pin Name Pin Number

EZ-Host

CY7C67300 External Memory Array

64K x 8

A[15:0]

nWR

nRD

nXRAMSEL

A[15:0]

D[7:0] D[7:0]

Interfacing to 64K x 8 External Memory Array

EZ-Host

CY7C67300 External Memory Array

Up to 256k x 16

A[18:1]

nBEL

nBEH

nWR

nRD

nXMEMSEL

A[17:0]

BLE

D[15:0] D[15:0]

Up to 256k x 16 External Code/Data (Page Mode)

BHE

[+] Feedback

CY7C67300

Document #: 38-08015 Rev. *J Page 7 of 99

Figure 4 illustrates the interface for connecting an 8-bit ROM or

8-bit RAM to the EZ-Host external memory interface. In 8-bit

mode, up to 512K bytes of external ROM or RAM are supported.

General Purpose IO Interface (GPIO)

EZ-Host has up to 32 GPIO signals available. Several other

optional interfaces use GPIO pins as well and may reduce the

overall number of available GPIOs.

GPIO Description

All Inputs are sampled asynchronously with state changes

occurring at a rate of up to two 48 MHz clock cycles. GPIO pins

are latched directly into registers, a single flip-flop.

Unused Pin Descriptions

Ensure to tristate unused USB pins with the D+ line pulled high

through the internal pull up resistor and the D– line pulled low

through the internal pull down resistor.

Configure unused GPIO pins as outputs so they are driven low.

UART Interface

EZ-Host has a built in UART interface. The UART interface

supports data rates from 900 to 115.2K baud. It can be used as

a development port or for other interface requirements. The

UART interface is exposed through GPIO pins.

UART Features

■Supports baud rates of 900 to 115.2K

■8-N-1

UART Pins.

I2C EEPROM Interface

EZ-Host provides a master-only I2C interface for external serial

EEPROMs.TheserialEEPROMcanbeusedtostoreapplication

specific code anddata.Usethe I2C interfacefor loadingcode out

of EEPROM, it is not a general I2C interface. The I2C EEPROM

interface is a BIOS implementation and is exposed through

GPIO pins. Refer to the BIOS documentation for additional

details on this interface.

I2C EEPROM Features

■Supports EEPROMs up to 64 KB (512K bit)

■Auto-detection of EEPROM size

I2C EEPROM Pins

Serial Peripheral Interface

EZ-HostprovidesaSPIinterfaceforaddedconnectivity.EZ-Host

may be configured as either an SPI master or SPI slave. The SPI

interface can be exposed through GPIO pins or the External

Memory port.

SPI Features

■Master or slave mode operation

■DMA block transfer and PIO byte transfer modes

■Full duplex or half duplex data communication

■8-byte receive FIFO and 8-byte transmit FIFO

■Selectable master SPI clock rates from 250 kHz to 12 MHz

■Selectable master SPI clock phase and polarity

■Slave SPI signaling synchronization and filtering

■Slave SPI clock rates up to 2 MHz

■Maskable interrupts for block and byte transfer modes

■Individual bit transfer for non-byte aligned serial communi-

cation in PIO mode

■Programmable delay timing for the active/inactive master SPI

clock

■Auto or manual control for master mode slave select signal

■Complete access to internal memory

Figure 4. Interfacing up to 512k × 8 for External Code/Data

Table 7. UART Interface Pins

Pin Name Pin Number

TX 42

RX 43

EZ-Host

CY7C67300 External Memory Array

Up to 512k x8

A[18:0]

nWR

nRD

nXMEMSEL

A[18:0]

D[7:0] D[7:0]

Up to 512k x 8 External Code/Data (Page Mode)

Table 8. I2C EEPROM Interface Pins

Pin Name Pin Number GPIO Number

SMALL EEPROM

SCK 39 GPIO31

SDA 40 GPIO30

LARGE EEPROM

SCK 40 GPIO30

SDA 39 GPIO31

[+] Feedback

CY7C67300

Document #: 38-08015 Rev. *J Page 8 of 99

SPI Pins

The SPI port has a few different pin location options as shown in

Table 9. The port location is selectable via the GPIO control

High-Speed Serial Interface

EZ-Host provides an HSS interface. The HSS interface is a

programmable serial connection with baud rate from 9600 baud

to 2.0M baud. The HSS interface supports both byte and block

mode operations and also hardware and software handshaking.

Complete control of EZ-Host can be accomplished through this

interface via an extensible API and communication protocol. The

HSSinterface can be exposedthrough GPIOpins or the External

Memory port.

HSS Features

■8 bits, no parity code

■Programmable baud rate from 9600 baud to 2M baud

■Selectable 1- or 2-stop bit on transmit

■Programmable inter-character gap timing for Block Transmit

■8-byte receive FIFO

■Glitch filter on receive

■Block mode transfer directly to/from EZ-Host internal memory

(DMA transfer)

■Selectable CTS/RTS hardware signal handshake protocol

■Selectable XON/XOFF software handshake protocol

■Programmable Receive interrupt, Block Transfer Done inter-

rupts

■Complete access to internal memory

HSS Pins

The HSS port has a few different pin location options as shown

in Table 10. The port location is selectable via the GPIO control

Programmable Pulse/PWM Interface

EZ-Host has four built in PWM output channels. Each channel

providesaprogrammable timinggeneratorsequence that canbe

used to interface to various image sensors or other applications.

The PWM interface is exposed through GPIO pins.

Programmable Pulse/PWM Features

■Four independent programmable waveform generators

■Programmable predefined frequencies ranging from 5.90 KHz

to 48 MHz

■Configurable polarity

■Continuous and one-shot mode available

Programmable Pulse/PWM Pins.

Table 9. SPI Interface Pins

Pin Name Pin Number

Default Location

nSSI 56 or 65

SCK 61

MOSI 60

MISO 66

Alternate Location

nSSI 73

SCK 72

MOSI 71

MISO 74

Table 10. HSS Interface Pins

Pin Name Pin Number

Default Location

CTS 44

RTS 53

RXD 54

TXD 55

Alternate Location

CTS 67

RTS 68

RXD 69

TXD 70

Table 11. PWM Interface Pins

Pin Name Pin Number

PWM3 44

PWM2 53

PWM1 54

PWM0 55

[+] Feedback

CY7C67300

Document #: 38-08015 Rev. *J Page 9 of 99

Host Port Interface

EZ-Host has an HPI interface. The HPI interface provides DMA

access to the EZ-Host internal memory by an external host, plus

a bidirectional mailbox register for supporting high level commu-

nication protocols. This port is designed to be the primary

high-speed connection to a host processor. Complete control of

EZ-Host can be accomplished through this interface via an

extensible API and communication protocol. Other than the

hardware communication protocols, a host processor has

identical control over EZ-Host whether connecting to the HPI or

HSS port. The HPI interface is exposed through GPIO pins.

HPI Features

■16-bit data bus interface

■16 MB/s throughput

■Auto-incrementofaddresspointerforfastblockmodetransfers

■Direct memory access (DMA) to internal memory

■Bidirectional Mailbox register

■Byte swapping

■Complete access to internal memory

■Complete control of SIEs through HPI

■Dedicated HPI status register

HPI Pins

The two HPI address pins are used to address one of four

possible HPI port registers as shown in Table 13.

IDE Interface

EZ-Host has an IDE interface. The IDE interface supports PIO

mode 0-4 as specified in the Information Technology-AT

Attachment–4 with Packet Interface Extension (ATA/ATAPI-4)

Specification, T13/1153D Rev 18. There is no need for firmware

to use programmable wait states. The CPU read/write cycle is

automatically extended as needed for direct CPU to IDE

read/write accesses.

The EZ-Host IDE interface also has a BLOCK transfer mode that

allows EZ-Host to read/write large blocks of data to/from the IDE

data register and move it to/from the EZ-Host on-chip memory

directly without intervention of the CPU. The IDE interface is

exposed through GPIO pins. Table 14 on page 10 lists the

achieved throughput for maximum block mode data transfer rate

(with IDE_IORDY true) for the various IDE PIO modes.

Table 12. HPI Interface Pins [3, 4]

Pin Name Pin Number

INT 46

nRD 47

nWR 48

nCS 49

A1 50

A0 52

D15 56

D14 57

D13 58

D12 59

Notes

3. HPI_INT is for the Outgoing Mailbox interrupt.

4. HPI strobes are negative logic sampled on rising edge.

D11 60

D10 61

D9 65

D8 66

D7 86

D6 87

D5 89

D4 90

D3 91

D2 92

D1 93

D0 94

Table 13. HPI Addressing

HPI A[1:0] A1 A0

HPI Data 0 0

HPI Mailbox 0 1

HPI Address 1 0

HPI Status 1 1

Table 12. HPI Interface Pins (continued)[3, 4]

[+] Feedback

CY7C67300

Document #: 38-08015 Rev. *J Page 10 of 99

IDE Features

■Programmable IO mode 0–4

■Block mode transfers

■Directmemoryaccessto/frominternalmemorythroughtheIDE

data register

IDE Pins

Charge Pump Interface

VBUS for the USB OTG port can be produced by EZ-Host using

its built in charge pump and some external components. Ensure

the circuit connections look similar to the following diagram.

Component details:

■D1 and D2: Schottky diodes with a current rating greater than

60 mA

■C1: Ceramic capacitor with a capacitance of 0.1 µF

■C2: Make capacitor value no more that 6.5 µF since that is the

maximumcapacitanceallowedbytheUSBOTGspecifications

for a dual role device. The minimum value of C2 is 1 µF. There

are no restrictions on the type of capacitor for C2.

If the VBUS charge pump circuit is not to be used, CSWITCHA,

CSWITCHB, and OTGVBUS can be left unconnected.

Charge Pump Features

■Meets OTG Supplement Requirements, see Table 134, DC

Characteristics: Charge Pump on page 84 for details.

Charge Pump Pins

Table 14. IDE Throughput

Mode ATA/ATAPI-4

Min Cycle Time Actual

Min Cycle Time ATA/ATPI-4

Max Transfer Rate Actual

Max Transfer Rate

PIO Mode 0 600 ns 30T = 625 ns 3.33 MB/s 3.2 MB/s

PIO Mode 1 383 ns 20T = 416.7 ns 5.22 MB/s 4.8 MB/s

PIO Mode 2 240 13T = 270.8 ns 8.33 MB/s 7.38 MB/s

PIO Mode 3 180 ns 10T = 208.3 ns 11.11 MB/s 9.6 MB/s

PIO Mode 4 120 ns 8T = 166.7 ns 16.67 MB/s 12.0 MB/s

T = System clock period = 1/48 MHz.

Table 15. IDE Interface Pins

Pin Name Pin Number

IORDY 46

IOR 47

IOW 48

CS1 50

CS0 52

A2 53

A1 54

A0 55

D15 56

D14 57

D13 58

D12 59

D11 60

D10 61

D9 65

D8 66

D7 86

D6 87

D5 89

D4 90

D3 91

D2 92

D1 93

D0 94

Figure 5. Charge Pump

Table 16. Charge Pump Interface Pins

Pin Name Pin Number

OTGVBUS 11

CSwitchA 13

CSwitchB 12

VBUS

D1 D2

CSWITCHA

CSWITCHB

OTGVBUS

CY7C67300

[+] Feedback

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