Cypress Semiconductor CY7C1380DV25 Manuel utilisateur

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05546 Rev. *E Revised Feburary 15, 2007

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• 2.5V core power supply

• Fast clock-to-output times, 2.6 ns (for 250-MHz device)

• Provides high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel® Pentium®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• CY7C1380DV25/CY7C1382DV25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non

Pb-free 165-ball FBGA package.

CY7C1380FV25/CY7C1382FV25 available in Pb-free and

non Pb-free 119-ball BGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

Functional Description [1]

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18

SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive edge triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE1), depth expansion chip enables (CE2and

CE3 [2]), burst control inputs (ADSC, ADSP, and ADV), write

enables (BWX, and BWE), and global write (GW).

Asynchronous inputs include the output enable (OE) and the

ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP) or

address strobe controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see Pin Definitions on page 6 and Truth Table [4,

5, 6, 7, 8] on page 9 for further details). Write cycles can be one

to two or four bytes wide as controlled by the byte write control

inputs. GW when active LOW causes all bytes to be written.

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 operates from a +2.5V core power supply

while all outputs may operate with a +2.5 supply. All inputs and

outputs are JEDEC-standard and JESD8-5-compatible.

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.0 3.4 ns

Maximum Operating Current 350 300 275 mA

Maximum CMOS Standby Current 70 70 70 mA

Notes:

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE3, CE2are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable

[+] Feedback

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document #: 38-05546 Rev. *E Page 2 of 29

Logic Block Diagram – CY7C1380DV25/CY7C1380FV25 [3] (512K x 36)

Logic Block Diagram – CY7C1382DV25/CY7C1382FV25 [3] (1M x 18)

ADDRESS

ADV

CLK BURST

COUNTER

AND

LOGIC

CLR

ADSP

ADSC

MODE

BWE

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

OUTPUT

BUFFERS

PIPELINED

ENABLE

INPUT

REGISTERS

A0, A1, A

BW C

MEMORY

ARRAY

DQs

DQP A

DQP B

DQP C

DQP D

SLEEP

CONTROL

[1:0]

DQ A , DQP

BYTE

WRITE REGISTER

DQ B , DQP

BYTE

WRITE REGISTER

DQ C , DQP

BYTE

WRITE REGISTER

DQ D , DQP D

BYTE

WRITE REGISTER

DQ A , DQP

BYTE

WRITE DRIVER

DQ B , DQP

BYTE

WRITE DRIVER

DQ C , DQP

BYTE

WRITE DRIVER

DQ D,DQP

BYTE

WRITE DRIVER

A0, A1, A ADDRESS

ADV

CLK

BURST

COUNTER AND

LOGIC

ADSC

DQP

WRITE REGISTER

DQP

WRITE REGISTER

ENABLE

SENSE

MEMORY

ARRAY

CE2

CE3

BWE

PIPELINED

ENABLE

DQs

DQP A

DQP B

OUTPUT

INPUT

DQP

WRITE DRIVER

OUTPUT

BUFFERS

DQP

WRITE DRIVER

ZZ SLEEP

CONTROL

Note:

3. CY7C1380F and CY7C1382F have only 1 Chip Enable (CE1).

[+] Feedback

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document #: 38-05546 Rev. *E Page 3 of 29

Pin Configurations

NC/72M

NC/36M

DQP

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

DQc

DDQ

SSQ

DDQ

SSQ

DDQ

DQP

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1380DV25

(512K X 36)

NC/72M

NC/36M

DDQ

SSQ

DQP

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DQP

SSQ

DDQ

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1382DV25

(1M x 18)

100-pin TQFP Pinout (3 Chip Enable)

[+] Feedback

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document #: 38-05546 Rev. *E Page 4 of 29

Pin Configurations (continued)

2345671

VDDQ

NC/288M

NC/144M

DQPC

DQC

DQD

DQC

DQD

AA AA

ADSP VDDQ

DQC

VDDQ

DQC

VDDQ

DQD

VDDQ

VDD

CLK

VDD

VSS

NC/576M

NC/1G

TDOTCKTDITMS

NC/36MNC/72M

VDDQ

AAA

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADSC

CE1

ADV

VSS

VSS DQPA

MODE

DQPD

DQPB

BWB

BWC

NC VDD NC

BWA

BWE

BWD

2345671

VDDQ

NC/288M

NC/144M

NCDQB

DQB

AA AA

ADSP VDDQ

VDDQ

NC/72M

VDDQ

VDD

CLK

VDD

VSS

NC/576M

NC/1G

TDOTCKTDITMS

VDDQ

A NC/36M A

DQA

DQB

DQA

VDD

DQB

VDD

DQB

ADSC

CE1

ADV

VSS

VSS NC

MODE

DQPB

DQPA

BWB

NC VDD NC

BWA

BWE

CY7C1382FV25 (1M x 18)

CY7C1380FV25 (512K x 36)

119-Ball BGA Pinout

[+] Feedback

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document #: 38-05546 Rev. *E Page 5 of 29

Pin Configurations (continued)

165-Ball FBGA Pinout (3 Chip Enable)

CY7C1380DV25 (512K x 36)

234 5671

TDO

NC/288M

NC/144M

DQP

CE3

BWE

ACE2

MODE

NC/36M

NC/72M

DDQ

CLK GW

DDQ

TCK

TDI

DDQ

TMS

891011

ADV

ADSC

OE ADSP

ANC/576M

DDQ

NC/1G DQP

DDQ

DQP

DDQ

CY7C1382DV25 (1M x 18)

234 5671

TDO

NC/288M

NC/144M

DQP

ACE

BWE

ACE2

MODE

NC/36M

NC/72M

DDQ

NC BW

CLK GW

DDQ

TCKA0

TDI

NC V

DDQ

TMS

891011

ADV

ADSC

OE ADSP

ANC/576M

DDQ

NC/1G DQP

DDQ

NCV

DDQ

[+] Feedback

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document #: 38-05546 Rev. *E Page 6 of 29

Pin Definitions

Name IO Description

A0, A1, A Input-

Synchronous

Address inputs used to select one of the address locations.Sampled at the rising

edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled

active. A1: A0 are fed to the two-bit counter.

BWA, BWB

BWC, BWD

Input-

Synchronous

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to

the SRAM. Sampled on the rising edge of CLK.

GW Input-

Synchronous

Global write enable input, active LOW. When asserted LOW on the rising edge of

CLK, a global write is conducted (all bytes are written, regardless of the values on BWX

and BWE).

BWE Input-

Synchronous

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal

must be asserted LOW to conduct a byte write.

CLK Input-

Clock

Clock input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

CE1Input-

Synchronous

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE2and CE3to select or deselect the device. ADSP is ignored if CE1

is HIGH. CE1 is sampled only when a new external address is loaded.

CE2 [2] Input-

Synchronous

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE1and CE3to select or deselect the device. CE2 is sampled only

when a new external address is loaded.

CE3 [2] Input-

Synchronous

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE1and CE2to select or deselect the device. CE3 is sampled only

when a new external address is loaded.

OE Input-

Asynchronous

Output enable, asynchronous input, active LOW. Controls the direction of the IO

pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are

tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle

when emerging from a deselected state.

ADV Input-

Synchronous

Advance input signal, sampled on the rising edge of CLK, active LOW. When

asserted, it automatically increments the address in a burst cycle.

ADSP Input-

Synchronous

Address strobe from processor, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are

both asserted, only ADSP is recognized. ASDP is ignored when CE1is deasserted

HIGH.

ADSC Input-

Synchronous

Address strobe from controller, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are

both asserted, only ADSP is recognized.

ZZ Input-

Asynchronous

ZZ sleep input. This active HIGH input places the device in a non-time critical sleep

condition with data integrity preserved. For normal operation, this pin has to be LOW

or left floating. ZZ pin has an internal pull down.

DQs, DQPXIO-

Synchronous

Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the previous clock rise

of the read cycle. The direction of the pins is controlled by OE. When OE is asserted

LOW, the pins behave as outputs. When HIGH, DQs and DQPXare placed in a tri-state

condition.

VDD Power Supply Power supply inputs to the core of the device.

VSS Ground Ground for the core of the device.

[+] Feedback

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document #: 38-05546 Rev. *E Page 7 of 29

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise (tCO) is 2.6 ns

(250-MHz device).

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 supports secondary cache in systems using

either a linear or interleaved burst sequence. The interleaved

burst order supports Pentium®and i486™processors. The

linear burst sequence is suited for processors that use a linear

burst sequence. The burst order is user selectable, and is

determined by sampling the MODE input. Accesses can be

initiated with either the processor address strobe (ADSP) or

the controller address strobe (ADSC). Address advancement

through the burst sequence is controlled by the ADV input. A

two-bit on-chip wraparound burst counter captures the first

address in a burst sequence and automatically increments the

address for the rest of the burst access.

Byte write operations are qualified with the byte write enable

(BWE) and byte write select (BWX) inputs. A global write

enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self timed write circuitry.

Three synchronous chip selects (CE1, CE2, CE3) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE1

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

CE1, CE2, CE3are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1

is HIGH. The address presented to the address inputs (A) is

stored into the address advancement logic and the address

corresponding data is allowed to propagate to the input of the

output registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within 2.6 ns (250-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are

always tri-stated during the first cycle of the access. After the

first cycle of the access, the outputs are controlled by the OE

signal. Consecutive single Read cycles are supported. Once

the SRAM is deselected at clock rise by the chip select and

either ADSP or ADSC signals, its output will tri-state

immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE1, CE2, CE3are all asserted active. The address

presented to A is loaded into the address register and the

address advancement logic while being delivered to the

memory array. The write signals (GW, BWE, and BWX) and

ADV inputs are ignored during this first cycle.

VSSQ IO Ground Ground for the IO circuitry.

VDDQ IO Power Supply Power supply for the IO circuitry.

MODE Input-

Static

Selects burst order. When tied to GND selects linear burst sequence. When tied to

VDD or left floating selects interleaved burst sequence. This is a strap pin and must

remain static during device operation. Mode pin has an internal pull up.

TDO JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

JTAG feature is not used, this pin must be disconnected. This pin is not available on

TQFP packages.

TDI JTAG serial input

Synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

feature is not used, this pin can be disconnected or connected to VDD. This pin is not

available on TQFP packages.

TMS JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

feature is not used, this pin can be disconnected or connected to VDD. This pin is not

available on TQFP packages.

TCK JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be

connected to VSS. This pin is not available on TQFP packages.

NC – No Connects. Not internally connected to the die

NC/(36M,72M,

144M, 288M,

576M, 1G)

–These pins are not connected. They will be used for expansion to the 36M, 72M,

144M, 288M, 576M and 1G densities.

Pin Definitions (continued)

Name IO Description

[+] Feedback

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document #: 38-05546 Rev. *E Page 8 of 29

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the

corresponding address location in the memory array. If GW is

HIGH, then the write operation is controlled by BWE and BWX

signals.

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 provides byte write capability that is

described in the write cycle descriptions table. Asserting the

byte write enable input (BWE) with the selected byte write

(BWX) input, will selectively write to only the desired bytes.

Bytes not selected during a byte write operation will remain

unaltered. A synchronous self timed write mechanism has

been provided to simplify the write operations.

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 is a common IO device, the output enable

(OE) must be deserted HIGH before presenting data to the

DQs inputs. Doing so will tri-state the output drivers. As a

safety precaution, DQs are automatically tri-stated whenever

a write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following

conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP

is deasserted HIGH, (3) CE1, CE2, CE3are all asserted active,

and (4) the appropriate combination of the write inputs (GW,

BWE, and BWX) are asserted active to conduct a write to the

desired byte(s). ADSC triggered write accesses require a

single clock cycle to complete. The address presented to A is

loaded into the address register and the address

advancement logic while being delivered to the memory array.

The ADV input is ignored during this cycle. If a global write is

conducted, the data presented to the DQs is written into the

corresponding address location in the memory core. If a byte

write is conducted, only the selected bytes are written. Bytes

not selected during a byte write operation will remain

unaltered. A synchronous self timed write mechanism has

been provided to simplify the write operations.

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 is a common IO device, the output enable

(OE) must be deserted HIGH before presenting data to the

DQs inputs. Doing so will tri-state the output drivers. As a

safety precaution, DQs are automatically tri-stated whenever

a write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 provides a two-bit wraparound counter, fed

by A1: A0, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed

specifically to support Intel Pentium applications. The linear

burst sequence is designed to support processors that follow

a linear burst sequence. The burst sequence is user selectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation sleep mode. Two

clock cycles are required to enter into or exit from this sleep

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the sleep mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the sleep mode. CE1, CE2, CE3, ADSP, and ADSC must

remain inactive for the duration of tZZREC after the ZZ input

returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 80 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[+] Feedback

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document #: 38-05546 Rev. *E Page 9 of 29

Truth Table [4, 5, 6, 7, 8]

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State

Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State

Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State

Sleep Mode, Power Down None X X X H X X X X X X Tri-State

Read Cycle, Begin Burst External L H L L L X X X L L-H Q

Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State

Write Cycle, Begin Burst External L H L L H L X L X L-H D

Read Cycle, Begin Burst External L H L L H L X H L L-H Q

Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State

Read Cycle, Continue Burst Next X X X L H H L H L L-H Q

Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

Write Cycle, Continue Burst Next X X X L H H L L X L-H D

Write Cycle, Continue Burst Next H X X L X H L L X L-H D

Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State

Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q

Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State

Write Cycle, Suspend Burst Current X X X L H H H L X L-H D

Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes:

4. X = Don't Care, H = Logic HIGH, L = Logic LOW.

5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after

the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't

care for the remainder of the write cycle

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

[+] Feedback

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Document #: 38-05546 Rev. *E Page 10 of 29

Truth Table for Read/Write [6, 9]

Function (CY7C1380DV25/CY7C1380FV25) GW BWE BWDBWCBWBBWA

Read HHXXXX

Read HLHHHH

Write Byte A – (DQA and DQPA) HLHHHL

Write Byte B – (DQB and DQPB)HLHHLH

Write Bytes B, A H L H H L L

Write Byte C – (DQCand DQPC) HLHLHH

Write Bytes C, A H L H L H L

Write Bytes C, B H L H L L H

Write Bytes C, B, A H L H L L L

Write Byte D – (DQD and DQPD) HL LHHH

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

WriteBytesD,C,B HLLLLH

WriteAllBytes HLLLLL

WriteAllBytes LXXXXX

Truth Table for Read/Write [6, 9]

Function (CY7C1382DV25/CY7C1382FV25) GW BWE BWBBWA

Read H H X X

Read H L H H

Write Byte A – (DQA and DQPA)HLHL

Write Byte B – (DQBand DQPB) HLLH

Write Bytes B, A H L L L

Write All Bytes H L L L

Write All Bytes L X X X

Note:

9. Table only lists a partial listing of the byte write combinations. Any combination of BWXis valid. Appropriate write will be done based on which byte write is active.

[+] Feedback

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