Cypress Semiconductor CY62148ESL Manuel utilisateur

CY62148ESL MoBL

4-Mbit (512K x 8) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 001-50045 Rev. ** Revised January 21, 2009

Features

■

Very high speed: 55 ns

■

Wide voltage range: 2.2V to 3.6V

and 4.5V to 5.5V

■

Ultra low standby power

❐

Typical standby current: 1 μA

❐

Maximum standby current: 7 μA

■

Ultra low active power

❐

Typical active current: 2 mA at f = 1 MHz

■

Easy memory expansion with CE and OE features

■

Automatic power down when deselected

■

CMOS for optimum speed and power

■

Available in Pb-free 32-pin STSOP package

Functional Description

The CY62148ESL is a high performance CMOS static RAM

organized as 512K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL

) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption. Placing the device into standby mode reduces

power consumption by more than 99 percent when deselected

(CE HIGH). The eight input and output pins (IO

through IO

) are

placed in a high impedance state when the device is deselected

(CEHIGH),theoutputsaredisabled(OE HIGH),or duringa write

operation (CE LOW and WE LOW).

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight IO pins (IO

through IO

) is

then written into the location specified on the address pins (A

through A

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins appear on the IO pins.

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

A0IO0

IO7

IO1

IO2

IO3

IO4

IO5

IO6

SENSE AMPS

POWER

DOWN

A13

A14

A15

A16

A17

ROW DECODER

COLUMN DECODER

512K x 8

ARRAY

INPUT BUFFER

A10

A11

A12

A18

Logic Block Diagram

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CY62148ESL MoBL

Document #: 001-50045 Rev. ** Page 2 of 10

Pin Configuration

Figure 1. 32-Pin STSOP (Top View)

Product Portfolio

Product Range V

Range (V)

[1]

Speed

(ns)

Power Dissipation

Operating I

, (mA) Standby, I

SB2

(μA)

f = 1 MHz f = f

max

Typ

[2]

Max Typ

[2]

Max Typ

[2]

Max

CY62148ESL Industrial 2.2V to 3.6V and 4.5V to 5.5V 55 2 2.5 15 20 1 7

A10

CE1

IO0

IO1

IO2

IO3

IO4

IO5

IO6

IO7

GND

STSOP

Top View

(not to scale)

Notes

1. Data sheet specifications are not guaranteed for V

in the range of 3.6V to 4.5V.

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V

= V

CC(typ)

, T

= 25°C.

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CY62148ESL MoBL

Document #: 001-50045 Rev. ** Page 3 of 10

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature.................................. –65°C to +150°C

Ambient Temperature with

Power Applied .............................................. 55°C to +125°C

Supply Voltage to Ground

Potential ...........................................................–0.5V to 6.0V

DC Voltage Applied to Outputs

in High-Z State

[3, 4]

..........................................–0.5V to 6.0V

DC Input Voltage

[3, 4]

.......................................–0.5V to 6.0V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage.......................................... > 2001V

(MIL-STD-883, Method 3015)

Latch Up Current....................................................> 200 mA

Operating Range

Device Range Ambient

Temperature V

CC[5]

CY62148ESL Industrial –40°C to +85°C 2.2V to 3.6V,

and

4.5V to 5.5V

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

55 ns

UnitMin Typ

[2]

Max

Output HIGH Voltage 2.2 < V

< 2.7 I

= –0.1 mA 2.0 V

2.7 < V

< 3.6 I

= –1.0 mA 2.4

4.5 < V

< 5.5 I

= –1.0 mA 2.4

Output LOW Voltage 2.2 < V

< 2.7 I

= 0.1 mA 0.4 V

2.7 < V

< 3.6 I

= 2.1 mA 0.4

4.5 < V

< 5.5 I

= 2.1 mA 0.4

Input HIGH Voltage 2.2 < V

< 2.7 1.8 V

+ 0.3 V

2.7 < V

< 3.6 2.2 V

+ 0.3

4.5 < V

< 5.5 2.2 V

+ 0.5

IL [6]

Input LOW Voltage 2.2 < V

< 2.7 –0.3 0.4 V

2.7 < V

< 3.6 –0.3 0.6

4.5 < V

< 5.5 –0.5 0.6

Input Leakage Current GND <V

< V

–1 +1 μA

OutputLeakageCurrent GND <V

,Output Disabled –1 +1 μA

Operating Supply

Current f = f

max

= 1/t

= V

CCmax

OUT

= 0 mA, CMOS levels 15 20 mA

f = 1 MHz 2 2.5

SB1

Automatic CE Power

DownCurrent—CMOS

Inputs

CE > V

− 0.2V, V

– 0.2V or V

<0.2V,

f = f

max

(Address and Data Only), f = 0 (OE and WE),

= V

CC(max)

17μA

SB2

Automatic CE Power

DownCurrent—CMOS

Inputs

CE > V

– 0.2V, V

> V

– 0.2V or V

< 0.2V,

f = 0, V

CC(max)

17μA

Notes

3. V

(min) = –2.0V for pulse durations less than 20 ns.

4. V

(max) = V

+ 0.75V for pulse durations less than 20 ns.

5. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V

(min) and 200 μs wait time after V

stabilization.

6. Under DC conditions the device meets a V

of 0.8V (for V

range of 2.7V to 3.6V and 4.5V to 5.5V) and 0.6V (for V

range of 2.2V to 2.7V). However, in dynamic

conditions Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. Refer to AN13470 for details.

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CY62148ESL MoBL

Document #: 001-50045 Rev. ** Page 4 of 10

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions Max Unit

Input Capacitance T

= 25°C, f = 1 MHz,

= V

CC(typ)

10 pF

OUT

Output Capacitance 10 pF

Thermal Resistance

Tested initially and after any design or process changes that may affect these parameters.

Parameter Description Test Conditions STSOP Unit

Thermal Resistance

(Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch, two layer printed

circuit board 49.02 °C/W

Thermal Resistance

(Junction to Case) 14.07 °C/W

Figure 2. AC Test Loads and Waveforms

Parameters 2.50V 3.0V 5.0V Unit

R1 16667 1103 1800 Ω

R2 15385 1554 990 Ω

8000 645 639 Ω

1.20 1.75 1.77 V

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND 90%

10% 90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalentto:

THEVENIN

EQUIVALENT

ALL INPUT PULSES

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CY62148ESL MoBL

Document #: 001-50045 Rev. ** Page 5 of 10

Data Retention Characteristics

Over the Operating Range

Parameter Description Conditions Min Typ

[2]

Max Unit

for Data Retention 1.5 V

CCDR

Data Retention Current CE > V

– 0.2V,

– 0.2V or V

< 0.2V V

= 1.5V 1 7 μA

CDR [7]

Chip Deselect to Data

Retention Time 0ns

R [8]

Operation Recovery Time t

Data Retention Waveform

CC(min)

CDR

>1.5V

DATA RETENTION MODE

Notes

7. Tested initially and after any design or process changes that may affect these parameters.

8. Full device operation requires linear V

ramp from V

to V

CC(min)

>100 μs or stable at V

CC(min)

>100 μs.

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CY62148ESL MoBL

Document #: 001-50045 Rev. ** Page 6 of 10

Switching Characteristics

Over the Operating Range

[9]

Parameter Description 55 ns Unit

Min Max

Read Cycle

Read Cycle Time 55 ns

Address to Data Valid 55 ns

OHA

Data Hold from Address Change 10 ns

ACE

CE LOW to Data Valid 55 ns

DOE

OE LOW to Data Valid 25 ns

LZOE

OE LOW to Low Z

[10]

5ns

HZOE

OE HIGH to High Z

[10, 11]

20 ns

LZCE

CE LOW to Low Z

[10]

10 ns

HZCE

CE HIGH to High Z

[10, 11]

20 ns

CE LOW to Power Up 0 ns

CE HIGH to Power Up 55 ns

Write Cycle

[12]

Write Cycle Time 55 ns

SCE

CE LOW to Write End 40 ns

Address Setup to Write End 40 ns

Address Hold from Write End 0 ns

Address Setup to Write Start 0 ns

PWE

WE Pulse Width 40 ns

Data Setup to Write End 25 ns

Data Hold from Write End 0 ns

HZWE

WE LOW to High Z

[10, 11]

20 ns

LZWE

WE HIGH to Low Z

[10]

10 ns

Notes

9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns),timing reference levels of V

CC(typ)

/2, input pulse

levels of 0 to V

CC(typ)

, and output loading of the specified I

as shown in AC Test Loads and Waveforms on page 4.

10.At any given temperature and voltage condition, t

HZCE

is less than t

LZCE

, t

HZOE

is less than t

LZOE

, and t

HZWE

is less than t

LZWE

for any given device.

11. t

HZOE

, t

HZCE

, and t

HZWE

transitions are measured when the output enter a high impedance state.

12.The internal write time of the memory is defined by the overlap of WE, CE = V

. All signals must be ACTIVE to initiate a write and any of these signals can terminate

a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

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CY62148ESL MoBL

Document #: 001-50045 Rev. ** Page 7 of 10

Switching Waveforms

Figure 3. Read Cycle No. 1 (Address Transition Controlled)

[13, 14]

Figure 4. Read Cycle No. 2 (OE Controlled)

[14, 15]

Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)

[16, 17]

PREVIOUS DATA VALID DATA VALID

OHA

ADDRESS

DATA OUT

50%

DATA VALID

ACE

DOE

LZOE

LZCE

HIGH IMPEDANCE

HZOE

HZCE

IMPEDANCE

HIGH

ADDRESS

DATA OUT

SUPPLY

CURRENT

DATA VALID

PWE

SCE

HZOE

ADDRESS

DATA IO

NOTE

Notes

13.Device is continuously selected. OE, CE = V

14.WE is HIGH for read cycles.

15.Address valid before or similar to CE transition LOW.

16.Data IO is high impedance if OE = V

17.If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.

18.During this period, the IOs are in output state. Do not apply input signals.

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CY62148ESL MoBL

Document #: 001-50045 Rev. ** Page 8 of 10

Figure 6. Write Cycle No. 2 (CE Controlled)

[16, 17]

Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)

[17]

Truth Table

CE WE OE Inputs/Outputs Mode Power

H X X High Z Deselect/Power Down Standby (I

)

L H L Data Out Read Active (I

)

L H H High Z Output Disabled Active (I

)

L L X Data in Write Active (I

)

Switching Waveforms

(continued)

DATA VALID

PWE

SCE

ADDRESS

DATA IO

DATA VALID

LZWE

PWE

SCE

HZWE

ADDRESS

DATA IO

NOTE

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CY62148ESL MoBL

Document #: 001-50045 Rev. ** Page 9 of 10

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

55 CY62148ESL-55ZAXI 51-85094 32-Pin STSOP (Pb-Free) Industrial

Package Diagram

Figure 8. 32-Pin Shrunk Thin Small Outline Package (8 x 13.4 mm), 51-85094

51-85094-*D

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Document #: 001-50045 Rev. ** Revised January 21, 2009 Page 10 of 10

MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the

trademarks of their respective holders.

CY62148ESL MoBL

circuitry otherthan circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,

life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical

components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for thesole purpose of creating custom software and or firmware insupport of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document History Page

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at cypress.com/sales.

Products

PSoC psoc.cypress.com

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Document Title: CY62148ESL MoBL

4-Mbit (512K x 8) Static RAM

Document Number: 001-50045

Rev. ECN No. Orig. of

Change Submission

Date Description of Change

** 2612938 VKN/PYRS 01/21/09 New data sheet

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