Cypress Semiconductor CY7C1020BN Manuel utilisateur

32K x 16 Static RAM

CY7C1020BN

Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600

Document #: 001-06443 Rev. ** Revised February 1, 2006

Features

•Highspeed

—t

AA = 12, 15 ns

• CMOS for optimum speed/power

• Low active power

— 825 mW (max.)

• Low CMOS standby power (L version only)

— 2.75 mW (max.)

• Automatic power-down when deselected

• Independent control of upper and lower bits

• Available in 44-pin TSOP II and 400-mil SOJ

Functional Description

The CY7C1020BN is a high-performance CMOS static RAM

organized as 32,768 words by 16 bits. This device has an

automatic power-down feature that significantly reduces

power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O1through I/O8), is

written into the location specified on the address pins (A0

through A15). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O9through I/O16) is written into the location

specified on the address pins (A0through A15).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O1to I/O8. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O9to I/O16. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

The input/output pins (I/O1through I/O16) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

aredisabled(BHE,BLEHIGH), orduring awrite operation(CE

LOW, and WE LOW).

The CY7C1020BN is available in standard 44-pin TSOP Type

II and 400-mil-wide SOJ packages.

Logic Block Diagram Pin Configuration

14 31

Top View

SOJ / TSOP II

15 29

VCC

A15

A14

A13

A12

VSS

I/O16

I/O3

I/O1

I/O2

BHE

I/O4

21 23

24 NC

VSS

I/O7

I/O5

I/O6

I/O8

BLE

VCC

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

A10

A11

32K x 16

RAM Array I/O1–I/O8

ROW DECODER

COLUMN DECODER

A10

A11

A12

A13

A14

SENSE AMPS

DATA IN DRIVERS

I/O9–I/O16

BLE

BHE

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CY7C1020BN

Document #: 001-06443 Rev. ** Page 2 of 8

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VCC to Relative GND[1] ....–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State[1] ......................................–0.5V to VCC+0.5V

DC Input Voltage[1]...................................–0.5V to VCC+0.5V

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.....................................................>200 mA

Selection Guide

7C1020BN-12 7C1020BN-15

Maximum Access Time (ns) 12 15

Maximum Operating Current (mA) 140 130

Maximum CMOS Standby Current (mA) 3 3

L0.5 0.5

Operating Range

Range Ambient

Temperature[2] VCC

Commercial 0×C to +70×C 5V ± 10%

Industrial –40×C to +85×C 5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter Description Test

Conditions 7C1020BN-12 7C1020BN-15 UnitMin. Max. Min. Max.

VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V

VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V

VIH Input HIGH Voltage 2.2 6.0 2.2 6.0 V

VIL Input LOW Voltage[1] –0.5 0.8 –0.5 0.8 V

IIX Input Load Current GND < VI< VCC –1 +1 –1 +1 µA

IOZ Output Leakage Current GND < VI <VCC, Output Disabled –1 +1 –1 +1 µA

IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND –300 –300 mA

ICC VCC Operating Supply Current VCC =Max.,IOUT =0mA,f=fMAX =1/tRC 140 130 mA

ISB1 Automatic CE Power-Down

Current—TTL Inputs Max. VCC, CE > VIH

VIN > VIH or VIN < VIL, f = fMAX 20 20 mA

ISB2 Automatic CE Power-Down

Current—CMOS Inputs Max. VCC, CE > VCC – 0.3V,

VIN > VCC – 0.3V, or VIN < 0.3V,

f = 0

3 3 mA

L0.5 0.5 mA

Capacitance[4]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz,

VCC = 5.0V 8pF

COUT Output Capacitance 8pF

Notes:

1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.

2. TAis the case temperature.

3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

4. Tested initially and after any design or process changes that may affect these parameters.

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CY7C1020BN

Document #: 001-06443 Rev. ** Page 3 of 8

AC Test Loads and Waveforms

Switching Characteristics[5] Over the Operating Range

Parameter Description

7C1020BN-12 7C1020BN-15

UnitMin. Max. Min. Max.

Read Cycle

tRC Read Cycle Time 12 15 ns

tAA Address to Data Valid 12 15 ns

tOHA Data Hold from Address Change 3 3 ns

tACE CE LOW to Data Valid 12 15 ns

tDOE OE LOW to Data Valid 6 7 ns

tLZOE OE LOW to Low Z[6] 0 0 ns

tHZOE OE HIGH to High Z[6, 7] 6 7 ns

tLZCE CE LOW to Low Z[6] 3 3 ns

tHZCE CE HIGH to High Z[6, 7] 6 7 ns

tPU CE LOW to Power-Up 0 0 ns

tPD CE HIGH to Power-Down 12 15 ns

tDBE Byte Enable to Data Valid 6 7 ns

tLZBE Byte Enable to Low Z 0 0 ns

tHZBE Byte Disable to High Z 6 7 ns

Write Cycle[8]

tWC Write Cycle Time 12 15 ns

tSCE CE LOW to Write End 910 ns

tAW Address Set-Up to Write End 810 ns

tHA Address Hold from Write End 0 0 ns

tSA Address Set-Up to Write Start 0 0 ns

tPWE WE Pulse Width 810 ns

tSD Data Set-Up to Write End 6 8 ns

tHD Data Hold from Write End 0 0 ns

tLZWE WE HIGH to Low Z[6] 3 3 ns

tHZWE WE LOW to High Z[6, 7] 6 7 ns

tBW Byte Enable to End of Write 8 9 ns

Notes:

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified

IOL/IOH and 30-pF load capacitance.

6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state

voltage.

8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate

a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal

that terminates the write.

90%

10%

3.0V

GND

90%

10%

ALL INPUT PULSES

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

R 481ΩR 481Ω

255ΩR2

255Ω

167 Equivalent to: THÉVENIN

EQUIVALENT 1.73V

30 pF

Rise Time: 1 V/ns Fall Time: 1 V/ns

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CY7C1020BN

Document #: 001-06443 Rev. ** Page 4 of 8

Switching Waveforms

Read Cycle No. 1[9, 10]

Read Cycle No. 2 (OE Controlled)[10, 11]

Notes:

9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL.

10.WE is HIGH for read cycle.

11.Address valid prior to or coincident with CE transition LOW.

PREVIOUS DATA VALID DATA VALID

tRC

tAA

tOHA

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tHZBE

tPD

HIGH

ICC

ISB

IMPEDANCE

ADDRESS

DATA OUT

VCC

SUPPLY

tDBE

tLZBE

tHZCE

BHE,BLE

CURRENT

ICC

ISB

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CY7C1020BN

Document #: 001-06443 Rev. ** Page 5 of 8

Write Cycle No. 1 (CE Controlled)[12, 13]

Write Cycle No. 2 (BLE or BHE Controlled)

Notes:

12.Data I/O is high impedance if OE or BHE and/or BLE= VIH.

13.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

Switching Waveforms (continued)

tHD

tSD

tSCE

tSA

tHA

tAW

tPWE

tWC

DATA I/O

ADDRESS

BHE,BLE

tHD

tSD

tBW

tSA

tHA

tAW

tPWE

tWC

tSCE

DATA I/O

ADDRESS

BHE,BLE

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CY7C1020BN

Document #: 001-06443 Rev. ** Page 6 of 8

Write Cycle No. 3 (WE Controlled, OE LOW)

Truth Table

CE OE WE BLE BHE I/O1–I/O8I/O9–I/O16 Mode Power

H X X X X High Z High Z Power-Down Standby (ISB)

L L H L L Data Out Data Out Read – All bits Active (ICC)

L H Data Out High Z Read – Lower bits only Active (ICC)

H L High Z Data Out Read – Upper bits only Active (ICC)

L X L L L Data In Data In Write – All bits Active (ICC)

L H Data In High Z Write – Lower bits only Active (ICC)

H L High Z Data In Write – Upper bits only Active (ICC)

L H H X X High Z High Z Selected, Outputs Disabled Active (ICC)

L X X H H High Z High Z Selected, Outputs Disabled Active (ICC)

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

12 CY7C1020BN-12VC 51-85082 44-Lead (400-Mil) Molded SOJ Commercial

CY7C1020BN-12VXC 51-85082 44-Lead (400-Mil) Molded SOJ (Pb-free) Commercial

CY7C1020BN-12ZC 51-85087 44-pin TSOP Type II Commercial

CY7C1020BN-12ZXC 51-85087 44-pin TSOP Type II (Pb-free) Commercial

15 CY7C1020BN-15ZC 51-85087 44-pin TSOP Type II Commercial

CY7C1020BN-15ZXC 51-85087 44-pin TSOP Type II (Pb-free) Commercial

Please contact local sales representative regarding availability of these parts.

Switching Waveforms (continued)

tHD

tSD

tSCE

tHA

tAW

tPWE

tWC

tBW

DATA I/O

ADDRESS

BHE,BLE

tSA

tLZWE

tHZWE

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CY7C1020BN

Document #: 001-06443 Rev. ** Page 7 of 8

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

All product and company names mentioned in this document may be the trademarks of their respective holders.

Package Diagrams

51-85082-*B

44-Lead (400-Mil) Molded SOJ (51-85082)

51-85087-*A

44-Pin TSOP II (51-85087)

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CY7C1020BN

Document #: 001-06443 Rev. ** Page 8 of 8

Document History Page

Document Title: CY7C1020BN 32K x 16 Static RAM

Document #: 001-06443

REV. ECN NO. Issue

Date Orig. of

Change Description of Change

** 426812 See ECN NXR New Data Sheet

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