Xilinx ALINX AC6150 Manuel utilisateur

Xilinx ALINX Core Board

AC6150

User Manual

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Version Record

Version

Date

Release By

Description

Rev 1.0

2020-11-08

Rachel Zhou

First Release

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Table of Contents

Version Record.......................................................................................................2

Part 1: AC6150 core board.................................................................................. 4

Part 2: FPGA.......................................................................................................... 5

Part 2.1: JTAG Interface...............................................................................6

Part 3: DDR3 DRAM............................................................................................. 7

Part 4: SPI Flash....................................................................................................9

Part 5: Crystal oscillator on Core Board.......................................................... 11

Part 6: LED Light on Core Board......................................................................12

Part 7: AC6150 Power Supply.......................................................................... 14

Part 8: Power interface on Core Board........................................................... 16

Part 9: Expansion Ports......................................................................................17

Part 10: Structure Diagram................................................................................21

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Part 1: AC6150 core board

FPGA+ DDR3 core board is based on XILINX's SPARTAN6 series

XC6SLX150-2FG484C. This chip develops a high-performance core board

with high speed, high bandwidth and high capacity. It is suitable for video

image processing and high-speed data acquisition.

This core board uses MICRON's MT41J128M16LA-187E DDR3 chip with

a capacity of 2Gbit; 16bit bus mode, read and write data bandwidth between

FPGA and DDR3 is up to 10Gb; this configuration can meet the needs of 4

channels of 1080p video processing.

This core board also extends 168 IO ports (84 pairs of LVDS differential

pairs), which is a good choice for users who need a lot of IO. Moreover, the

FPGA chip to the interface is treated with the same length, and the core board

size is only 60*60 (mm), which is very suitable for secondary development.

Front View

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Rear View

Part 2: FPGA

As mentioned above, the FPGA model we use is XC6SLX150-2FG484C,

which belongs to Xilinx's SPARTAN6 series. The speed grade is 2, and the

temperature grade is Commercial grade. This model is a FGG484 package

with 484 pins. Xilinx SPARTAN6 FPGA naming rules as below

Figure 2-1: The Specific Chip Model Definition of SPARTAN6 Series

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Figure 2-2: FPGA chip on the core board

The main parameters of the FPGA chip XC7A100T are as follows

Name

Specific parameters

Logic Cells

147,443

Slices

23038

CLB flip-flops

184,304

Block RAM（kb）

4,824

Clock Management Unit (CMT)

DSP Processing Unit (DSP48A1 Slices)

180

DDR Controller (Memory Controller Blocks)

Chip Package

BGA484, Spacing 1.0mm

Speed Grade

-2

Temperature Grade

Commercial

Part 2.1: JTAG Interface

First introduce the configuration and debugging interface of the FPGA:

JTAG interface. JTAG test holes (2.5mm single-row interface) are reserved on

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the core board. Users can connect the pin headers on the core board and

connect the download and core JTAG ports with DuPont cable. To achieve core

board program download and debug of the FPGA chip without the carrier board.

The following Figure 3-2-3 shows the JTAG interface on the core board:

Figure 2-3: JTAG Interface on the core board

Part 3: DDR3 DRAM

Figure 3-1 detailed part of the DDR3 schematic (For details, please refer to

the schematic provided by us.)

Figure 3-1: DDR3 schematic

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In addition, the normal operation of DDR3 requires DDR3 address line and

control line to provide termination voltage VTT and DDR3 chip reference

voltage VREF, VTT and VREF voltage are both 0.75V, the following Figure 3-2

is the power part schematic.

Figure 3-2: DDR3 Power for VTT/VREF

Figure 3-3: DDR3 Power Circuit on the FPGA Board

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DDR3 is connected to the BANK3 of the FPGA.

DDR3 Pin Assignment

Pin Name

FPGA Pin

Pin Name

FPGA Pin

DDR3_A[0]

DDR3_A[11]

DDR3_A[1]

DDR3_A[12]

DDR3_A[2]

DDR3_A[13]

DDR3_A[3]

DDR3_A[14]

DDR3_A[4]

DDR3_BA[0]

DDR3_A[5]

DDR3_BA[1]

DDR3_A[6]

DDR3_BA[2]

DDR3_A[7]

DDR3_nCAS

DDR3_A[8]

DDR3_CKE

DDR3_A[9]

DDR3_CLK_P

DDR3_A[10]

DDR3_CLK_N

DDR3_nRAS

DDR3_DQ[8]

DDR3_nWE

DDR3_DQ[9]

DDR3_ODT

DDR3_DQ[10]

DDR3_RESET

DDR3_DQ[11]

DDR3_LDM

DDR3_DQ[12]

DDR3_UDM

DDR3_DQ[13]

DDR3_DQ[0]

DDR3_DQ[14]

DDR3_DQ[1]

DDR3_DQ[15]

DDR3_DQ[2]

DDR3_LDQS_P

DDR3_DQ[3]

DDR3_LDQS_N

DDR3_DQ[4]

DDR3_UDQS_P

DDR3_DQ[5]

DDR3_UDQS_N

DDR3_DQ[6]

DDR3_DQ[7]

Part 4: SPI Flash

The FPGA core board AC6150 is equipped with one 64MBit SPI FLASH,

and the model is W25Q64BV, which uses the 3.3V CMOS voltage standard.

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Due to the non-volatile nature of SPI FLASH, it can be used as a boot device

for the system to store the boot image of the system. These images mainly

include FPGA bit files, core application code and other user data files. The

specific models and related parameters of SPI FLASH are shown in Table 4-1.

Position

Model

Capacity

Factory

W25Q64BV

64M Bit

Winbond

Table 4-1: SPI FLASH Specification

Figure 4-1: SPI Flash schematic

Figure 4-2: W25Q64BV chip on the FPGA Board

Table des matières

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