Xilinx Virtex-6 FPGA Manuel utilisateur

Virtex-6 FPGA

Configurable Logic Block

User Guide

UG364 (v1.2) February 3, 2012

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Virtex-6 FPGA CLB User Guide www.xilinx.com UG364 (v1.2) February 3, 2012

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Revision History

The following table shows the revision history for this document.

Date Version Revision

06/24/09 1.0 Initial Xilinx release.

09/16/09 1.1 Add Virtex-6 HXT devices to Table 2. Updated discussions at Look-Up Table (LUT),

page 11, and Static Read Operation, page 29. CLB labeling change in figures throughout

document (Figure 6 through Figure 13, Figure 15, Figure 17, Figure 27 through

Figure 29), including clarifying the TDS/TDH functions, descriptions, and notes in

Table 7, page 39 and Table 8, page 42.

02/03/12 1.2 In Enable – WE/WED, updated second sentence to say that an inactive write enable

prevents writing to memory cells. In Inverting Clock Pins, updated second sentence to

“positive edge of the clock.”

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UG364 (v1.2) February 3, 2012

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preface: About This Guide

Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Virtex-6 FPGA CLB

CLB Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Slice Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

CLB / Slice Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

General Slice Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Slice Distributed RAM Timing Model and Parameters (Available in SLICEM only) 38

Slice SRL Timing Model and Parameters (Available in SLICEM only) . . . . . . . . . . . . 41

Slice Carry-Chain Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

CLB Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Distributed RAM Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Shift Registers (SRLs) Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Other Shift Register Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Multiplexer Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Carry Chain Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table of Contents

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UG364 (v1.2) February 3, 2012

Preface

About This Guide

This guide serves as a technical reference describing the Virtex®-6 FPGA configurable

logic blocks (CLBs). Usually, the logic synthesis software assigns the CLB resources

without system designer intervention. It can be advantageous for the designer to

understand certain CLB details, including the varying capabilities of the look-up tables

(LUTs), the physical direction of the carry propagation, the number and distribution of the

available flip-flops, and the availability of the very efficient shift registers. This guide

describes these and other features of the CLB in detail.

Additional Documentation

The following documents are also available for download at

http://www.xilinx.com/support/documentation/virtex-6.htm.

• Virtex-6 Family Overview

The features and product selection of the Virtex-6 family are outlined in this overview.

• Virtex-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and Switching Characteristic specifications for the

Virtex-6 family.

• Virtex-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum

I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and

thermal specifications.

• Virtex-6 FPGA Configuration Guide

This all-encompassing configuration guide includes chapters on configuration

interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG

configuration, reconfiguration techniques, and readback through the SelectMAP and

JTAG interfaces.

• Virtex-6 FPGA Clocking Resources User Guide

This guide describes the clocking resources available in all Virtex-6 devices, including

the MMCM and PLLs.

• Virtex-6 FPGA Memory Resources User Guide

The functionality of the block RAM and FIFO are described in this user guide.

• Virtex-6 FPGA SelectIO Resources User Guide

This guide describes the SelectIO™ resources available in all Virtex-6 devices.

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6www.xilinx.com Virtex-6 FPGA CLB User Guide

UG364 (v1.2) February 3, 2012

Preface: About This Guide

• Virtex-6 FPGA GTH Transceivers User Guide

This guide describes the GTH transceivers available in all Virtex-6 HXT FPGAs except

the XC6VHX250T and the XC6VHX380T in the FF1154 package..

• Virtex-6 FPGA GTX Transceivers User Guide

This guide describes the GTX transceivers available in all Virtex-6 FPGAs except the

XC6VLX760.

• Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide

This guide describes the dedicated Tri-Mode Ethernet Media Access Controller

available in all Virtex-6 FPGAs except the XC6VLX760.

• Virtex-6 FPGA DSP48E1 Slice User Guide

This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and

provides configuration examples.

• Virtex-6 FPGA System Monitor User Guide

The System Monitor functionality available in all Virtex-6 devices is outlined in this

guide.

• Virtex-6 FPGA PCB Design Guide

This guide provides information on PCB design for Virtex-6 devices, with a focus on

strategies for making design decisions at the PCB and interface level.

Additional Support Resources

To search the database of silicon and software questions and answers or to create a

technical support case in WebCase, see the Xilinx website at:

http://www.xilinx.com/support.

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UG364 (v1.2) February 3, 2012

Virtex-6 FPGA CLB

CLB Overview

The Configurable Logic Blocks (CLBs) are the main logic resources for implementing

sequential as well as combinatorial circuits. Each CLB element is connected to a switch

matrix for access to the general routing matrix (shown in Figure 1). A CLB element

contains a pair of slices. These two slices do not have direct connections to each other, and

each slice is organized as a column. Each slice in a column has an independent carry chain.

For each CLB, slices in the bottom of the CLB are labeled as SLICE(0), and slices in the top

of the CLB are labeled as SLICE(1).

The Xilinx tools designate slices with the following definitions. An “X” followed by a

number identifies the position of each slice in a pair as well as the column position of the

slice. The “X” number counts slices starting from the bottom in sequence 0, 1 (the first CLB

column); 2, 3 (the second CLB column); etc. A “Y” followed by a number identifies a row of

slices. The number remains the same within a CLB, but counts up in sequence from one

CLB row to the next CLB row, starting from the bottom. Figure 2 shows four CLBs located

in the bottom-left corner of the die.

X-Ref Target - Figure 1

Figure 1: Arrangement of Slices within the CLB

Switch

Matrix

Slice(1)

COUTCOUT

CINCIN

Slice(0)

CLB

ug364_01_040209

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UG364 (v1.2) February 3, 2012

CLB Overview

Slice Description

Every slice contains four logic-function generators (or look-up tables), eight storage

elements, wide-function multiplexers, and carry logic. These elements are used by all slices

to provide logic, arithmetic, and ROM functions. In addition to this, some slices support

two additional functions: storing data using distributed RAM and shifting data with 32-bit

registers. Slices that support these additional functions are called SLICEM; others are

called SLICEL. SLICEM (shown in Figure 3) represents a superset of elements and

connections found in all slices. SLICEL is shown in Figure 4.

Each CLB can contain zero or one SLICEM. Every other CLB column contains a SLICEMs.

In addition, the two CLB columns to the left of the DSP48E columns both contain a SLICEL

and a SLICEM.

X-Ref Target - Figure 2

Figure 2: Row and Column Relationship between CLBs and Slices

Slice

X1Y1

COUTCOUT

CINCIN

Slice

X0Y1

CLB

ug364_02_040209

Slice

X1Y0

COUTCOUT

Slice

X0Y0

CLB

Slice

X3Y1

COUTCOUT

CINCIN

Slice

X2Y1

CLB

Slice

X3Y0

COUTCOUT

Slice

X2Y0

CLB

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UG364 (v1.2) February 3, 2012

CLB Overview

X-Ref Target - Figure 3

Figure 3: Diagram of SLICEM

A6:A1

COUT

DI2

DI1

MC31WEN

DI1

MC31WEN

DI1

MC31WEN

DI1

MC31WEN

ug364_03_040209

DX DMUX

CMUX

BMUX

AMUX

Reset Type

FF/LAT

INIT1

INIT0

SRHI

SRLO

FF/LAT

INIT1

INIT0

SRHI

SRLO

FF/LAT

INIT1

INIT0

SRHI

SRLO

FF/LAT

INIT1

INIT0

SRHI

SRLO

CIN

0/1

WEN

Sync/Async

FF/LAT

A6:A1

C6:1

D6:1

A6:A1

B6:1

A6:A1

W6:W1

A6:1

CLK

CE Q

CK SR

SRHI

SRLO

INIT1

INIT0

CE Q

CK SR

SRHI

SRLO

INIT1

INIT0

CE Q

CK SR

SRHI

SRLO

INIT1

INIT0

CE Q

CK SR

SRHI

SRLO

INIT1

INIT0

DI2

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UG364 (v1.2) February 3, 2012

CLB Overview

X-Ref Target - Figure 4

Figure 4: Diagram of SLICEL

A6:A1

COUT

ug364_04_040209

DX DMUX

CMUX

BMUX

AMUX

Reset Type

FF/LAT

INIT1

INIT0

SRHI

SRLO

FF/LAT

INIT1

INIT0

SRHI

SRLO

FF/LAT

INIT1

INIT0

SRHI

SRLO

FF/LAT

INIT1

INIT0

SRHI

SRLO

CIN

0/1

Sync/Async

FF/LAT

A6:A1

C6:1

D6:1

A6:A1

B6:1

A6:A1

A6:1

CLK

CE Q

CK SR

SRHI

SRLO

INIT1

INIT0

CE Q

CK SR

SRHI

SRLO

INIT1

INIT0

CE Q

CK SR

SRHI

SRLO

INIT1

INIT0

CE Q

CK SR

SRHI

SRLO

INIT1

INIT0

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