Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Manuel utilisateur

Video In to

AXI4-Stream v1.0

Product Guide

PG043 April 24, 2012

Video In to AXI4-Stream www.xilinx.com 2

PG043 April 24, 2012

Table of Contents

Chapter 1: Overview

Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Licensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 2: Product Specification

Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Core Interfaces and Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 3: Customizing and Generating the Core

Graphical User Interface (GUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 4: Designing with the Core

General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

System Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Module Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Chapter 5: Constraining the Core

Required Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Device, Package, and Speed Grade Selections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Clock Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Banking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Transceiver Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Video In to AXI4-Stream www.xilinx.com 3

PG043 April 24, 2012

I/O Standard and Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 6: Detailed Example Design

Appendix A: Additional Resources

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Notice of Disclaimer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Video In to AXI4-Streamt www.xilinx.com 4

PG043 April 24, 2012 Product Specification

Introduction

The Xilinx LogiCORE™ IP Video In to

AXI4-Stream core is designed to interface from

a video source (clocked parallel video data with

synchronization signals - active video with

either syncs, blanks or both) to the AXI4-Stream

Video Protocol Interface. This core works in

conjunction with the timing detector portion of

the Xilinx Video Timing Controller (VTC) core.

This core provides a bridge between a video

input and video processing cores with

AXI4-Stream Video Protocol interfaces.

Features

• Video (clocked parallel video data with

synchronization signals - active video with

either syncs, blanks or both) input

• AXI4-Stream Video Protocol interface for

output

• Interface to Xilinx Video Timing Controller

core for video timing generation

• Handles asynchronous clock boundary

crossing between video clock domain and

AXI4-Stream clock domain

• Selectable FIFO depth from 64 -8192

locations

• Selectable input data width of 8-64 bits

LogiCORE IP Video In to

AXI4-Stream v1.0

LogiCORE IP Facts Table

Core Specifics

Supported

Device Family(1)

Zynq-7000, Artix-7, Virtex®-7, Kintex®-7,

Virtex-6, Spartan®-6

Supported User

Interfaces AXI4-Stream(2)

Resources See Ta bl e 2- 1.

Provided with Core

Documentation Product Guide

Design Files Verilog Source Code

Example Design Not Provided

Tes t Bench Not Provided

Constraints File Not Provided

Simulation

Models Verilog Source Code

Tested Design Tools

Design Entry

Tools ISE 14.1

Simulation(3)Mentor Graphics ModelSim, Xilinx®ISim

Synthesis Tools Xilinx Synthesis Technology (XST)

Support

Provided by Xilinx, Inc.

1. For a complete listing of supported devices, see the release

notes for this core.

2. Video protocol as defined in the Video IP: AXI Feature

Adoption section of UG761 AXI Reference Guide.

3. For the supported versions of the tools, see the ISE Design

Suite 14: Release Notes Guide.

Video In to AXI4-Stream www.xilinx.com 5

PG043 April 24, 2012

Chapter 1

Overview

Many Xilinx video processing cores utilize the AXI-4 Stream video protocol to transfer video

between cores. Between systems, video is commonly transmitted with explicit blanking and

sync signals for horizontal and vertical timing, and a data valid signal. DVI is an example of

such a transmission mode. The Video In to AXI4-Stream core converts incoming video with

explicit sync and timing to the AXI4-Stream Video protocol in order to interface to Xilinx

video processing cores that use this protocol.

The Video In to AXI-4 Stream core accepts video inputs. For the purposes of this document,

video is defined as parallel video data along with a pixel clock and one of the following sets

of timing signals:

•Vsync,Hsync,andDE

• Vblank, Hblank, and DE

• Vsync, Hsync, Vbank, Hblank, and DE

Any of these sets of signals is sufficient for the operation of the Video In to AXI4-Stream

core. The particular choice is important to the VTC detector, so the generation of the VTC

core should specify which set of timing signals will be used. The output side of the core is

an AXI4-Stream interface in master mode. This interface consists of parallel video data,

tdata, handshaking signals tvalid and tready, and two flags, tlast and tuser which

serve to identify certain pixels in the video stream. The flag tlast designates the last valid

pixel of each line, and is also known as the end of line (EOL). The flag tuser designates the

first valid pixel of a frame, and is known as start of frame (SOF). These two flags are

necessary to identify pixel locations on the AXI4 stream bus because there are no sync or

blank signals. Only active pixel are carried on the bus. The Video IP: AXI Feature Adoption

section of the UG761 AXI Reference Guide describes the video over AXI4 Stream Video

protocol in detail.

Video In to AXI4-Stream www.xilinx.com 6

PG043 April 24, 2012

Feature Summary

A Video In to AXI4-Stream core with a video timing generator block diagram is shown in

Figure 1-1

The core is designed to be used in parallel with the detector functionality of the Video

Timing Controller (VTC). The video timing detector detects the line standard of the

incoming video, and makes the detected timing values, such as the number of active pixels

per line and the number of active lines available to video processing cores downstream of

the Video In to AXI4-Stream core via an AXI4-Lite interface. It is recommended to connect

the “locked” status output of video timing detector to the axis_enable input of the Video

In to AXI4-Stream core in order to inhibit the AXI4-Stream bus when the video input is

missing or unstable.

Feature Summary

The Video In to AXI4-Stream core converts a video input, consisting of parallel video data,

video syncs, blanks and data enable, to an AXI4-Stream master bus that follows the

AXI4-Stream Video protocol. The core provides a pass thru of all timing signals for the Xilinx

video timing controller, although the signals for the Video timing Controller are not

required to pass through the Video In to AXI4 Stream core.

The core handles the asynchronous clock boundary crossing between the video clock

domain and the AXI4-Stream clock domain. The data width is selectable from 8 to 64 bits,

X-Ref Target - Figu re 1-1

Figure 1-1: Block Diagram of Video In to AXI4-Stream Core and Usage with the Video Timing Controller

Video In to AXI4-Stream www.xilinx.com 7

PG043 April 24, 2012

Applications

depending on the number of components required for the video format, and the number of

bits per component. There is an input FIFO with selectable depth from 32 to 8192 locations.

Applications

• Video input to AXI4-Stream Video Protocol interface for parallel, clocked video sources

°DVI

°HDMI

°Image Sensors

°Other clocked, parallel video sources

Licensing

The Video In to AXI4-Stream core is provided at no cost with the Xilinx tools. Use of it is

covered by the standard software license, and there are no further licensing requirements

needed to use it in a design. Source code for this core is provided to enable customers to

modify the core to meet their own unique requirements if necessary. Use of this core or any

portions of this core is only allowed on a Xilinx device.

Video In to AXI4-Stream www.xilinx.com 8

PG043 April 24, 2012 Product Specification

Chapter 2

Product Specification

Standards Compliance

The Video In to AXI4-Stream core is compliant with the AXI4-Stream Video Protocol and

AXI4-Lite interconnect standards. Refer to the Video IP: AXI Feature Adoption section of the

UG761 AXI Reference Guide for additional information.

Performance

The following sections detail the performance characteristics of the Video In to

AXI4-Stream core.

Maximum Frequencies

This section contains typical clock frequencies for the target devices. The maximum

achievable clock frequency can vary. The maximum achievable clock frequency and all

resource counts can be affected by other tool options, additional logic in the FPGA device,

using a different version of Xilinx tools and other factors. Refer to in Table 2 -1 through

Tab le 2-6 for device-specific information.

Latency

When the downstream processing block on the AXI4-Stream bus can take data at the pixel

rate or faster, the typical latency through the Video In to AXI4-Stream core is 6 cycles of

vid_in_clk + 3 cycles of aclk.

If the downstream block takes pixels at a slower rate, the FIFO will be used to even out the

mismatch in the input and output rates over the course of lines and frames. This storage of

pixels in the FIFO will add to the latency and will vary according to the data flow in and out

of the core.

Video In to AXI4-Stream www.xilinx.com 9

PG043 April 24, 2012 Product Specification

Resource Utilization

Throughput

The average data rates of active pixels on the AXI4-Stream interface matches the average

rate of active pixels in on the Video bus. However, the clock rates of the input and output

need not match. Furthermore, since the AXI4-Stream bus does not carry blank pixels, the

clock rate can be lower than the video clock rate and still have sufficient bandwidth to meet

the average rate requirement. Additional FIFO depth is required in order to smooth the

mismatch in instantaneous rates. Both the input video pixel clock (Fvclk) and the rate of the

AXI4-Stream Clock (Faclk) is limited by the overall Fmax.

If Faclk is equal to or greater than Fvclk, only the minimum buffer size (32 locations) is

required. This assumes that the cores connected downstream of the Video In to

AXI4-Stream core can sink data at the full video rate. e.g. The downstream core can accept

data in a virtually continuous stream with gaps occurring only following EOL, and each line

consecutively with line gaps only preceding SOF. In this scenario, the FIFO will go empty

after the EOL on each line.

If Faclk is less than Fvclk, additional buffering is required. The FIFO must be large enough to

handle the differential in the rate that pixels are coming in on the video clock, and the

slower rate that they can go out on the AXI4-Stream bus using aclk. For aclk frequencies

above the line average but below that of vclk, the input FIFO depth must be:

FIFO depth min =32 + Active Pixels * Fvclk/Faclk

If the downstream processing core accepts data at a lower rate than the aclk, additional

buffering is required in an amount sufficient to prevent the FIFO from overflowing during

the course of a frame.

Resource Utilization

The information presented in Table 2-1 through Table 2- 6 is a guide to the resource

utilization and maximum clock frequency of the Video In to AXI4-Stream core for Virtex-7,

Kintex-7, Artix-7, Zynq-7000, Virtex-6, and Spartan-6 FPGA families. The design was tested

using ISE®v14.1 tools with default tool options for characterization data.

Note: Data width in the following tables refers to the aggregate data width of all the video

components into and out of the core. For example, RGB data with 8-bits per component has a data

width of 24.

Table 2-1: Spartan-6

Data Width FIFO Depth LUTs FFs RAM 16/8 Fmax (MHz)

8 32 83 104 0/0 223

24 1024 147 161 1/1 209

64 8192 204 264 33/0 129

Video In to AXI4-Stream www.xilinx.com 10

PG043 April 24, 2012 Product Specification

Core Interfaces and Register Space

Port Descriptions

The Video In to AXI4-Stream core uses industry standard control and data interfaces to

connect to other system components. The following sections describe the various interfaces

available with the core. Figure 2-1 illustrates an I/O diagram of the Video In to AXI4-Stream

Table 2-2: Virtex-7