Texas Instruments MSP432P401R Manuel utilisateur

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

MSP432P401R, MSP432P401M

SLAS826F –MARCH 2015–REVISED MARCH 2017

MSP432P401R, MSP432P401M SimpleLink™ Mixed-Signal Microcontrollers

1 Device Overview

1.1 Features

• Core

– ARM®32-Bit Cortex®-M4F CPU With Floating-

Point Unit and Memory Protection Unit

– Frequency up to 48 MHz

– ULPBench™ Benchmark:

– 192.3 ULPMark™-CP

– Performance Benchmark:

– 3.41 CoreMark/MHz

– 1.22 DMIPS/MHz (Dhrystone 2.1)

• Advanced Low-Power Analog Features

– 14-Bit 1-MSPS SAR ADC With 13.2 ENOB

Native and Capability to Reach 16 ENOB With

Oversampling, Differential and Single-Ended

Inputs

– Internal Voltage Reference With 10-ppm/°C

Typical Stability

– Two Analog Comparators

• Memories

– Up to 256KB of Flash Main Memory (Organized

Into Two Banks Enabling Simultaneous

Read/Execute During Erase)

– 16KB of Flash Information Memory (Used for

BSL, TLV, and Flash Mailbox)

– Up to 64KB of SRAM (Including 6KB of Backup

Memory)

– 32KB of ROM With MSP432™ Peripheral Driver

Libraries

• Ultra-Low-Power Operating Modes

– Active: 80 µA/MHz

– Low-Frequency Active: 83 µA at 128 kHz

– LPM3 (With RTC): 660 nA

– LPM3.5 (With RTC): 630 nA

– LPM4: 500 nA

– LPM4.5: 25 nA

• Development Kits and Software (See Tools and

Software)

– MSP-EXP432P401R LaunchPad™

Development Kit

– MSP-TS432PZ100 100-Pin Target Board

– SimpleLink™ MSP432 Software Development

Kit (SDK)

• Operating Characteristics

– Wide Supply Voltage Range: 1.62 V to 3.7 V

– Temperature Range (Ambient): –40°C to 85°C

• Flexible Clocking Features

– Tunable Internal DCO (up to 48 MHz)

– 32.768 kHz Low-Frequency Crystal Support

(LFXT)

– High-Frequency Crystal Support (HFXT) up to

48 MHz

– Low-Frequency Internal Reference Oscillator

(REFO)

– Very Low-Power Low-Frequency Internal

Oscillator (VLO)

– Module Oscillator (MODOSC)

– System Oscillator (SYSOSC)

• Code Security Features

– JTAG and SWD Lock

– IP Protection (up to Four Secure Flash Zones,

Each With Configurable Start Address and Size)

• Enhanced System Features

– Programmable Supervision and Monitoring of

Supply Voltage

– Multiple-Class Resets for Better Control of

Application and Debug

– 8-Channel DMA

– RTC With Calendar and Alarm Functions

• Timing and Control

– Up to Four 16-Bit Timers, Each With up to Five

Capture, Compare, PWM Capability

– Two 32-Bit Timers, Each With Interrupt

Generation Capability

• Serial Communication

– Up to Four eUSCI_A Modules

– UART With Automatic Baud-Rate Detection

– IrDA Encode and Decode

– SPI (up to 16 Mbps)

– Up to Four eUSCI_B Modules

– I2C (With Multiple-Slave Addressing)

– SPI (up to 16 Mbps)

• Flexible I/O Features

– Ultra-Low-Leakage I/Os (±20 nA Maximum)

– All I/Os With Capacitive-Touch Capability

– Up to 48 I/Os With Interrupt and Wake-up

Capability

– Up to 24 I/Os With Port Mapping Capability

– Eight I/Os With Glitch Filtering Capability

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• Encryption and Data Integrity Accelerators

– 128-, 192-, or 256-Bit AES Encryption and

Decryption Accelerator

– 32-Bit Hardware CRC Engine

• JTAG and Debug Support

– 4-Pin JTAG and 2-Pin SWD Debug Interfaces

– Serial Wire Trace

– Power Debug and Profiling of Applications

1.2 Applications

• Industrial and Automation

– Glass Breakage Detectors

– Smart Thermostats

– Access Panels

– Gas Monitors

– Field Transmitters

– Process Automation

– Home Automation

• Metering

– Flow Meters

– Electric Meters

– Communication Modules

• Test and Measurement

– Digital Multimeters

– Wireless Digital Multimeters

– Contactless and Hand-Held Digital Meters

• Health and Fitness

– Watches

– Activity Monitors

– Fitness Accessories

– Blood Glucose Meters

• Consumer Electronics

– Mobile Devices

– Sensor Hubs

1.3 Description

The SimpleLink MSP432P401x microcontrollers (MCUs) are optimized wireless host MCUs with an

integrated 14-bit analog-to-digital converter (ADC) capable of up to 16 ENOB delivering ultra-low-power

performance including 80 µA/MHz in active power and 660 nA in standby power with FPU and DSP

extensions. As an optimized wireless host MCU, the MSP432P401x allows developers to add high-

precision analog and memory extension to applications based on SimpleLink wireless connectivity

solutions.

The MSP432P401x devices are part of the SimpleLink microcontroller (MCU) platform, which consists of

Wi-Fi®,Bluetooth®low energy, Sub-1 GHz, and host MCUs. All share a common, easy-to-use

development environment with a single core software development kit (SDK) and rich tool set. A one-time

integration of the SimpleLink platform lets you add any combination of devices from the portfolio into your

design. The ultimate goal of the SimpleLink platform is to achieve 100 percent code reuse when your

design requirements change. For more information, visit www.ti.com/simplelink.

MSP432P401x devices are supported by a comprehensive ecosystem of tools, software, documentation,

training, and support to get your development started quickly. The MSP-EXP432P401R LaunchPad

development kit or MSP-TS432PZ100 target socket board (with additional MCU sample) along with the

free SimpleLink MSP432 SDK is all you need to get started.

(1) For the most current part, package, and ordering information for all available devices, see the Package

Option Addendum in Section 9, or see the TI website.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 9.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE(2)

MSP432P401RIPZ

MSP432P401MIPZ LQFP (100) 14 mm × 14 mm

MSP432P401RIZXH

MSP432P401MIZXH NFBGA (80) 5 mm × 5 mm

MSP432P401RIRGC

MSP432P401MIRGC VQFN (64) 9 mm × 9 mm

PCM

Power

Control

Manager

PSS

Power

Supply

System

Clock

System

RTC_C

Real-Time

Clock

WDT_A

Watchdog

Timer

I/O Ports

P1 to P10

78 I/Os

I/O Ports

6 I/Os

Flash

256KB

128KB

RSTCTL

Reset

Controller

SYSCTL

System

Controller

AES256

Security

Encryption,

Decryption

CRC32

ADC14

14 bit,

1 Msps,

SAR A/D

Comp_E0,

Comp_E1

Analog

Comparator

REF_A,

Voltage

Reference

TA0, TA1,

TA2,TA3

Timer_A

16 Bit

5 CCR

Timer32

2 x 32-bit

Timers

eUSCI_A0,

eUSCI_A1,

eUSCI_A2,

eUSCI_A3

(UART,

IrDA, SPI)

eUSCI_B0,

eUSCI_B1,

eUSCI_B2,

eUSCI_B3

(I C, SPI)

Bus

Control

Logic

DMA

8 Channels

Capacitive Touch IO 0,

Capacitive Touch IO 1

Address

Data

LFXIN,

HFXIN

LFXOUT,

HFXOUT

DCOR

LPM3.5 Domain

P1.x to P10.x PJ.x

Backup

Memory

SRAM

6KB

CPU

MPU

NVIC, SysTick

FPB, DWT

ARM

Cortex™-M4F

ITM, TPIU

JTAG, SWD

SRAM

(includes

Backup

Memory)

64KB

32KB

ROM

(Peripheral

Driver

Library)

32KB

MSP432P401R, MSP432P401M

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1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the MSP432P401R and MSP432P401M devices.

Figure 1-1. MSP432P401R, MSP432P401M Functional Block Diagram

The CPU and all of the peripherals in the device interact with each other through a common AHB matrix.

In some cases, there are bridges between the AHB ports and the peripherals. These bridges are

transparent to the application from a memory map perspective and, therefore, are not shown in the block

diagram.

MSP432P401R, MSP432P401M

SLAS826F –MARCH 2015–REVISED MARCH 2017

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Table of Contents

1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 2

1.3 Description............................................ 2

1.4 Functional Block Diagram ............................ 3

2 Revision History ......................................... 5

3 Device Comparison ..................................... 6

3.1 Related Products ..................................... 7

4 Terminal Configuration and Functions.............. 8

4.1 Pin Diagrams ......................................... 8

4.2 Pin Attributes........................................ 11

4.3 Signal Descriptions.................................. 17

4.4 Pin Multiplexing ..................................... 27

4.5 Buffer Types......................................... 27

4.6 Connection for Unused Pins ........................ 27

5 Specifications........................................... 28

5.1 Absolute Maximum Ratings ........................ 28

5.2 ESD Ratings ........................................ 28

5.3 Recommended Operating Conditions............... 28

5.4 Recommended External Components ............. 29

5.5 Operating Mode VCC Ranges ....................... 29

5.6 Operating Mode CPU Frequency Ranges ......... 30

5.7 Operating Mode Peripheral Frequency Ranges .... 30

5.8 Operating Mode Execution Frequency vs Flash

Wait-State Requirements ........................... 31

5.9 Current Consumption During Device Reset......... 31

5.10 Current Consumption in LDO-Based Active

Modes – Dhrystone 2.1 Program ................... 31

5.11 Current Consumption in DC-DC-Based Active

Modes – Dhrystone 2.1 Program ................... 32

5.12 Current Consumption in Low-Frequency Active

Modes – Dhrystone 2.1 Program ................... 32

5.13 Typical Characteristics of Active Mode Currents for

CoreMark Program.................................. 33

5.14 Typical Characteristics of Active Mode Currents for

Prime Number Program............................. 34

5.15 Typical Characteristics of Active Mode Currents for

Fibonacci Program.................................. 35

5.16 Typical Characteristics of Active Mode Currents for

While(1) Program ................................... 36

5.17 Typical Characteristics of Low-Frequency Active

Mode Currents for CoreMark Program.............. 37

5.18 Current Consumption in LDO-Based LPM0 Modes.38

5.19 Current Consumption in DC-DC-Based LPM0

Modes ............................................... 38

5.20 Current Consumption in Low-Frequency LPM0

Modes ............................................... 38

5.21 Current Consumption in LPM3, LPM4 Modes ...... 39

5.22 Current Consumption in LPM3.5, LPM4.5 Modes .. 39

5.23 Current Consumption of Digital Peripherals ........ 40

5.24 Thermal Resistance Characteristics ................ 40

5.25 Timing and Switching Characteristics............... 41

6 Detailed Description ................................... 90

6.1 Overview ............................................ 90

6.2 Processor and Execution Features ................. 90

6.3 Memory Map ........................................ 91

6.4 Memories on the MSP432P401x .................. 111

6.5 DMA................................................ 114

6.6 Memory Map Access Details ...................... 115

6.7 Interrupts........................................... 117

6.8 System Control..................................... 119

6.9 Peripherals......................................... 124

6.10 Code Development and Debug.................... 134

6.11 Performance Benchmarks ......................... 136

6.12 Input/Output Diagrams............................. 138

6.13 Device Descriptors (TLV).......................... 176

6.14 Identification........................................ 178

7 Applications, Implementation, and Layout...... 180

7.1 Device Connection and Layout Fundamentals .... 180

7.2 Peripheral and Interface-Specific Design

Information ......................................... 181

8 Device and Documentation Support.............. 183

8.1 Getting Started and Next Steps ................... 183

8.2 Device and Development Tool Nomenclature..... 183

8.3 Tools and Software ................................ 184

8.4 Documentation Support............................ 186

8.5 Related Links ...................................... 187

8.6 Community Resources............................. 188

8.7 Trademarks ........................................ 188

8.8 Electrostatic Discharge Caution ................... 188

8.9 Export Control Notice.............................. 188

8.10 Glossary............................................ 188

9 Mechanical, Packaging, and Orderable

Information............................................. 188

MSP432P401R, MSP432P401M

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from July 26, 2016 to March 7, 2017 Page

• Added "SimpleLink" branding, including updates to the titles of referenced documents.................................... 1

• Reorganized contents of Section 1.1,Features .................................................................................. 1

• Updated Section 1.2,Applications ................................................................................................. 2

• Updated Section 1.3,Description................................................................................................... 2

• Updated lists of software and tools in Section 8.3,Tools and Software.................................................... 185

Product Folder Links: MSP432P401R MSP432P401M

MSP432P401R, MSP432P401M

SLAS826F –MARCH 2015–REVISED MARCH 2017

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3 Device Comparison

Table 3-1 summarizes the features of the MSP432P401x microcontrollers.

(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.

(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a

number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output

generators, respectively.

Table 3-1. Device Comparison(1)

DEVICE FLASH

(KB) SRAM

(KB) ADC14

(Channels) COMP_E0

(Channels) COMP_E1

(Channels) Timer_A(2)

eUSCI

20-mA

DRIVE I/O TOTAL

I/Os PACKAGE

CHANNEL

UART,

IrDA, SPI

CHANNEL

SPI, I2C

MSP432P401RIPZ 256 64 24 ext, 2 int 8 8 5, 5, 5, 5 4 4 4 84 100 PZ

MSP432P401MIPZ 128 32 24 ext, 2 int 8 8 5, 5, 5, 5 4 4 4 84 100 PZ

MSP432P401RIZXH 256 64 16 ext, 2 int 6 8 5, 5, 5 3 4 4 64 80 ZXH

MSP432P401MIZXH 128 32 16 ext, 2 int 6 8 5, 5, 5 3 4 4 64 80 ZXH

MSP432P401RIRGC 256 64 12 ext, 2 int 2 4 5, 5, 5 3 3 4 48 64 RGC

MSP432P401MIRGC 128 32 12 ext, 2 int 2 4 5, 5, 5 3 3 4 48 64 RGC

MSP432P401R, MSP432P401M

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3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TI Microcontrollers Low-power and high-performance MCUs, with wired and wireless

connectivity options.

Products for SimpleLink MSP432 MCUs SimpleLink MSP432 MCUs with an ultra-low-power ARM

Cortex-M4 core are optimized for Internet-of-Things sensor node applications. With an

integrated 14-bit ADC, the family enables acquisition and processing of high-precision

signals without sacrificing power and is an optimal host MCU for TI's SimpleLink wireless

connectivity solutions.

Companion Products for MSP432P401R Review products that are frequently purchased or used with

this product.

Reference Designs for MSP432P401R The TI Designs Reference Design Library is a robust reference

design library that spans analog, embedded processor, and connectivity. Created by TI

experts to help you jump start your system design, all TI Designs include schematic or block

diagrams, BOMs, and design files to speed your time to market. Search and download

designs at ti.com/tidesigns.

1P10.1/UCB3CLK

2P10.2/UCB3SIMO/UCB3SDA

3P10.3/UCB3SOMI/UCB3SCL

4P1.0/UCA0STE

5P1.1/UCA0CLK

6P1.2/UCA0RXD/UCA0SOMI

7P1.3/UCA0TXD/UCA0SIMO

8P1.4/UCB0STE

9P1.5/UCB0CLK

10P1.6/UCB0SIMO/UCB0SDA

11P1.7/UCB0SOMI/UCB0SCL

12VCORE

13DVCC1

14VSW

15DVSS1

16P2.0/PM_UCA1STE

17P2.1/PM_UCA1CLK

18P2.2/PM_UCA1RXD/PM_UCA1SOMI

19P2.3/PM_UCA1TXD/PM_UCA1SIMO

20P2.4/PM_TA0.1

21P2.5/PM_TA0.2

22P2.6/PM_TA0.3

23P2.7/PM_TA0.4

24P10.4/TA3.0/C0.7

25P10.5/TA3.1/C0.6

P7.4/PM_TA1.4/C0.5

P7.5/PM_TA1.3/C0.4

P7.6/PM_TA1.2/C0.3

P7.7/PM_TA1.1/C0.2

P8.0/UCB3STE/TA1.0/C0.1

P8.1/UCB3CLK/TA2.0/C0.0

P3.0/PM_UCA2STE

P3.1/PM_UCA2CLK

P3.2/PM_UCA2RXD/PM_UCA2SOMI

P3.3/PM_UCA2TXD/PM_UCA2SIMO

P3.4/PM_UCB2STE

P3.5/PM_UCB2CLK

P3.6/PM_UCB2SIMO/PM_UCB2SDA

P3.7/PM_UCB2SOMI/PM_UCB2SCL

AVSS3

PJ.0/LFXIN

PJ.1/LFXOUT

AVSS1

DCOR

AVCC1

P8.2/TA3.2/A23

P8.3/TA3CLK/A22

P8.4/A21

P8.5/A20

P8.6/A19

51 P8.7/A18

52 P9.0/A17

53 P9.1/A16

54 P6.0/A15

55 P6.1/A14

56 P4.0/A13

57 P4.1/A12

58 P4.2/ACLK/TA2CLK/A11

59 P4.3/MCLK/RTCCLK/A10

60 P4.4/HSMCLK/SVMHOUT/A9

61 P4.5/A8

62 P4.6/A7

63 P4.7/A6

64 P5.0/A5

65 P5.1/A4

66 P5.2/A3

67 P5.3/A2

68 P5.4/A1

69 P5.5/A0

70 P5.6/TA2.1/VREF+/VeREF+/C1.7

71 P5.7/TA2.2/VREF-/VeREF-/C1.6

72 DVSS2

73 DVCC2

74 P9.2/TA3.3

75 P9.3/TA3.4

P6.2/UCB1STE/C1.5

P6.3/UCB1CLK/C1.4

P6.4/UCB1SIMO/UCB1SDA/C1.3

P6.5/UCB1SOMI/UCB1SCL/C1.2

P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1

P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0

DVSS3

RSTn/NMI

AVSS2

PJ.2/HFXOUT

PJ.3/HFXIN

AVCC2

P7.0/PM_SMCLK/PM_DMAE0

P7.1/PM_C0OUT/PM_TA0CLK

P7.2/PM_C1OUT/PM_TA1CLK

P7.3/PM_TA0.0

PJ.4/TDI

PJ.5/TDO/SWO

SWDIOTMS

SWCLKTCK

P9.4/UCA3STE

P9.5/UCA3CLK

P9.6/UCA3RXD/UCA3SOMI

P9.7/UCA3TXD/UCA3SIMO

100

P10.0/UCB3STE

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4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout of the 100-pin PZ package.

A. The secondary digital functions on Ports P2, P3, and P7 are fully mappable. This pinout shows only the default

mapping. See Section 6.9.2 for details.

B. A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.

C. UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD

D. SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI

E. I2C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL

Figure 4-1. 100-Pin PZ Package (Top View)

A1 A2 A3 A4 A5 A6 A7 A8 A9

B1 B2 B3 B4 B5 B6 B7 B8 B9

C1 C2

D1 D2 D4 D5 D6 D7 D8 D9

E1 E2 E4 E5 E6 E7 E8 E9

F1 F2 F4 F5 F8 F9

G1 G2 G4 G5 G8 G9

J1 J2 J4 J5 J6 J7 J8 J9

H1 H2 H4 H5 H6 H7 H8 H9

C4 C5 C6 C7 C8 C9

P1.0 SWCLKTCK PJ.5 P7.3 PJ.3

RSTn/NMI

P6.5 P6.4 P6.2

P1.1 SWDIOTMS PJ.4 P7.2 P7.0 P6.7 P6.6

P1.5 VCORE P1.2 P7.1 DVSS3 P5.5 P5.7

P1.6 DVCC1 P1.4 P5.3 P5.4 P5.6

P1.7 VSW P5.0 P5.1 P5.2

P2.1 DVSS1 P4.7

P2.5 P2.6 P8.1 P3.2 P3.5 P4.2 P4.3 P4.4

P2.7 P7.5 P8.0 P3.1 P3.4 P3.7 P6.1 P4.1 P4.0

P7.4 P7.6 P3.0 P3.3 P3.6 PJ.0 PJ.1 DCOR P6.0

PJ.2

P6.3

DVCC2

AVCC2

P1.3 AVSS2

P2.2 P2.0 AVSS3 DVSS2

P2.4 P2.3 AVSS1 AVCC1 P4.5

P7.7

P4.6

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Figure 4-2 shows the pinout of the 80-pin ZXH package.

A. A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.

B. UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD

C. SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI

D. I2C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL

Figure 4-2. 80-Pin ZXH Package (Top View)

1P1.0/UCA0STE

2P1.1/UCA0CLK

3P1.2/UCA0RXD/UCA0SOMI

4P1.3/UCA0TXD/UCA0SIMO

5P1.4/UCB0STE

6P1.5/UCB0CLK

7P1.6/UCB0SIMO/UCB0SDA

8P1.7/UCB0SOMI/UCB0SCL

DVSS1

VSW 11

DVCC1

VCORE

13P2.0/PM_UCA1STE

14P2.1/PM_UCA1CLK

15P2.2/PM_UCA1RXD/PM_UCA1SOMI

16P2.3/PM_UCA1TXD/PM_UCA1SIMO

P8.0/UCB3STE/TA1.0/C0.1

P8.1/UCB3CLK/TA2.0/C0.0

P3.0/PM_UCA2STE

P3.1/PM_UCA2CLK

P3.2/PM_UCA2RXD/PM_UCA2SOMI

P3.3/PM_UCA2TXD/PM_UCA2SIMO

P3.4/PM_UCB2STE

P3.5/PM_UCB2CLK

P3.6/PM_UCB2SIMO/PM_UCB2SDA

P3.7/PM_UCB2SOMI/PM_UCB2SCL

AVCC1

DCOR

AVSS1

PJ.0/LFXIN

PJ.1/LFXOUT

AVSS3

33 P4.2/ACLK/TA2CLK/A11

34 P4.3/MCLK/RTCCLK/A10

35 P4.4/HSMCLK/SVMHOUT/A9

36 P4.5/A8

37 P4.6/A7

38 P4.7/A6

39 P5.0/A5

40 P5.1/A4

41 P5.2/A3

42 P5.3/A2

43 P5.4/A1

44 P5.5/A0

45 P5.6/TA2.1/VREF+/VeREF+/C1.7

46 P5.7/TA2.2/VREF-/VeREF-/C1.6

47 DVSS2

48 DVCC2

P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1

P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0

DVSS3

RSTn/NMI

AVSS2

PJ.2/HFXOUT

PJ.3/HFXIN

AVCC2

P7.0/PM_SMCLK/PM_DMAE0

P7.1/PM_C0OUT/PM_TA0CLK

P7.2/PM_C1OUT/PM_TA1CLK

P7.3/PM_TA0.0

PJ.4/TDI

PJ.5/TDO/SWO

SWDIOTMS

SWCLKTCK

MSP432P401R, MSP432P401M

SLAS826F –MARCH 2015–REVISED MARCH 2017

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Figure 4-3 shows the pinout of the 64-pin RGC package.

A. The secondary digital functions on Ports P2, P3, and P7 are fully mappable. This pinout shows only the default

mapping. See Section 6.9.2 for details.

B. A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.

C. TI recommends connecting the thermal pad on the QFN package to DVSS.

D. UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD

E. SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI

F. I2C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL

Figure 4-3. 64-Pin RGC Package (Top View)

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