Texas Instruments MSP430 series Manuel utilisateur

MSP430F23x

MSP430F24x(1)

MSP430F2410

www.ti.com

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

MIXED SIGNAL MICROCONTROLLER

1FEATURES

23• Low Supply-Voltage Range, 1.8 V to 3.6 V • On-Chip Comparator

• Ultra-Low Power Consumption • Supply Voltage Supervisor/Monitor With

Programmable Level Detection

– Active Mode: 270 µA at 1 MHz, 2.2 V • Brownout Detector

– Standby Mode (VLO): 0.3 µA • Bootstrap Loader

– Off Mode (RAM Retention): 0.1 µA • Serial Onboard Programming, No External

• Ultra-Fast Wake-Up From Standby Mode in Programming Voltage Needed, Programmable

Less Than 1 µs Code Protection by Security Fuse

• 16-Bit RISC Architecture, 62.5-ns Instruction • Family Members Include:

Cycle Time – MSP430F233

• Basic Clock Module Configurations: – 8KB+256B Flash Memory,

– Internal Frequencies up to 16 MHz – 1KB RAM

– Internal Very Low-Power LF Oscillator – MSP430F235

– 32-kHz Crystal – 16KB+256B Flash Memory

– Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1% – 2KB RAM

– Resonator – MSP430F247, MSP430F2471 (1)

– External Digital Clock Source – 32KB+256B Flash Memory

– External Resistor – 4KB RAM

• 12-Bit Analog-to-Digital (A/D) Converter With – MSP430F248, MSP430F2481

Internal Reference, Sample-and-Hold, and – 48KB+256B Flash Memory

Autoscan Feature – 4KB RAM

• 16-Bit Timer_A With Three Capture/Compare – MSP430F249, MSP430F2491

Registers – 60KB+256B Flash Memory

• 16-Bit Timer_B With Seven Capture/Compare – 2KB RAM

With Shadow Registers – MSP430F2410

• Four Universal Serial Communication – 56KB+256B Flash Memory

Interfaces (USCI) – 4KB RAM

– USCI_A0 and USCI_A1 • Available in 64-Pin QFP and 64-Pin QFN

– Enhanced UART Supporting Auto-Baudrate Packages (See Available Options)

Detection • For Complete Module Descriptions, See

– IrDA Encoder and Decoder MSP430x2xx Family User’s Guide (SLAU144)

– Synchronous SPI

– USCI_B0 and USCI_B1 (1) The MSP430F24x1 devices are identical to the MSP430F24x

– I2C™ devices, with the exception that the ADC12 module is not

– Synchronous SPI implemented on the MSP430F24x1.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430 is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

MSP430F23x

MSP430F24x(1)

MSP430F2410

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION

The Texas Instruments MSP430™ family of ultra-low power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The calibrated digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less

than 1 µs.

The MSP430F23x, MSP430F24x(1), and MSP430F2410 series are microcontroller configurations with two built-

in 16-bit timers, a fast 12-bit A/D converter (not MSP430F24x1), a comparator, four (two in MSP430F23x)

universal serial communication interface (USCI) modules, and up to 48 I/O pins. The MSP430F24x1 devices are

identical to the MSP430F24x devices, with the exception that the ADC12 module is not implemented. The

MSP430F23x devices are identical to the MSP430F24x devices, with the exception that a reduced Timer_B, one

USCI module, and less RAM are integrated.

Typical applications include sensor systems, industrial control applications, and hand-held meters.

Table 1. Available Options

PACKAGED DEVICES(1)(2)

TAPLASTIC 64-PIN QFP (PM) PLASTIC 64-PIN QFN (RGC)

MSP430F233TPM MSP430F233TRGC

MSP430F235TPM MSP430F235TRGC

MSP430F247TPM MSP430F247TRGC

MSP430F2471TPM MSP430F2471TRGC

-40°C to 105°C MSP430F248TPM MSP430F248TRGC

MSP430F2481TPM MSP430F2481TRGC

MSP430F249TPM MSP430F249TRGC

MSP430F2491TPM MSP430F2491TRGC

MSP430F2410TPM MSP430F2410TRGC

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Development Tool Support

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and

programming through easy to use development tools. Recommended hardware options include the following:

• Debugging and Programming Interface

– MSP-FET430UIF (USB)

– MSP-FET430PIF (Parallel Port)

• Debugging and Programming Interface with Target Board

– MSP-FET430U64 (PM package)

• Standalone Target Board

– MSP-TS430PM64 (PM package)

• Production Programmer

– MSP-GANG430

P1.7/TA2 AVSS

P6.2/A2

P2.0/ACLK/CA2

P6.1/A1

P2.1/TAINCLK/CA3

P6.0/A0

P2.2/CAOUT/TA0/CA4

RST/NMI

P2.3/CA0/TA1

TCK

P2.4/CA1/TA2

TDO/TDI

P2.7/TA0/CA7

TDI/TCLK

P2.6/ADC12CLK/CA6

XT2IN

P3.0/UCB0STE/UCA0CLK

XT2OUT

P3.1/UCB0SIMO/UCB0SDA

P5.7/TBOUTH/SVSOUT

P3.2/UCB0SOMI/UCB0SCL

P5.6/ACLK

P3.3/UCB0CLK/UCA0STE

P5.5/SMCLK

P3.4/UCA0TXD/UCA0SIMO

P4.4

XOUT

P5.3

P6.3/A3

P5.4/MCLK

DVCC

P5.2

P6.4/A4

P4.7/TBCLK

P6.7/A7/SVSIN

P5.1

P6.5/A5

P5.0

P6.6/A6

P4.6

VREF+

P4.5XIN

P4.1/TB1P1.0/TACLK/CAOUT

P4.3VeREF+

P4.2/TB2V /Ve

REF- REF-

P4.0/TB0P1.1/TA0

P3.7P1.2/TA1

P3.5/UCA0RXD/UCA0SOMIP1.4/SMCLK

P3.6P1.3/TA2

TMS

P2.5/R /CA5

OSC

P1.6/TA1

DVSS

P1.5/TA0 AVCC

409

472

463

436

3910

3613

3316

3415

PM OR RGC PACKAGE

(TOP VIEW)

MSP430F23x

MSP430F24x(1)

MSP430F2410

www.ti.com

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

Device Pinout, MSP430F23x

P1.7/TA2 AVSS

P6.2/A2

P2.0/ACLK/CA2

P6.1/A1

P2.1/TAINCLK/CA3

P6.0/A0

P2.2/CAOUT/TA0/CA4

RST/NMI

P2.3/CA0/TA1

TCK

P2.4/CA1/TA2

TDO/TDI

P2.7/TA0/CA7

TDI/TCLK

P2.6/ADC12CLK/CA6

XT2IN

P3.0/UCB0STE/UCA0CLK

XT2OUT

P3.1/UCB0SIMO/UCB0SDA

P5.7/TBOUTH/SVSOUT

P3.2/UCB0SOMI/UCB0SCL

P5.6/ACLK

P3.3/UCB0CLK/UCA0STE

P5.5/SMCLK

P3.4/UCA0TXD/UCA0SIMO

P4.4/TB4

XOUT

P5.3/UCB1CLK/UCA1STE

P6.3/A3

P5.4/MCLK

DVCC

P5.2/UCB1SOMI/UCB1SCL

P6.4/A4

P4.7/TBCLK

P6.7/A7/SVSIN

P5.1/UCB1SIMO/UCB1SDA

P6.5/A5

P5.0/UCB1STE/UCA1CLK

P6.6/A6

P4.6/TB6

VREF+

P4.5/TB5XIN

P4.1/TB1P1.0/TACLK/CAOUT

P4.3/TB3VeREF+

P4.2/TB2V /Ve

REF- REF-

P4.0/TB0P1.1/TA0

P3.7/UCA1RXD/UCA1SOMIP1.2/TA1

P3.5/UCA0RXD/UCA0SOMIP1.4/SMCLK

P3.6/UCA1TXD/UCA1SIMO

P1.3/TA2

TMS

P2.5/R /CA5

OSC

P1.6/TA1

DVSS

P1.5/TA0 AVCC

409

472

463

436

3910

3613

3316

3415

PM OR RGC PACKAGE

(TOP VIEW)

MSP430F2410,

MSP430F24x

MSP430F23x

MSP430F24x(1)

MSP430F2410

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

www.ti.com

Device Pinout, MSP430F24x, MSP430F2410

P1.7/TA2 AVSS

P6.2

P2.0/ACLK/CA2

P6.1

P2.1/TAINCLK/CA3

P6.0

P2.2/CAOUT/TA0/CA4

RST/NMI

P2.3/CA0/TA1

TCK

P2.4/CA1/TA2

TDO/TDI

P2.7/TA0/CA7

TDI/TCLK

P2.6/ADC12CLK/CA6

XT2IN

P3.0/UCB0STE/UCA0CLK

XT2OUT

P3.1/UCB0SIMO/UCB0SDA

P5.7/TBOUTH/SVSOUT

P3.2/UCB0SOMI/UCB0SCL

P5.6/ACLK

P3.3/UCB0CLK/UCA0STE

P5.5/SMCLK

P3.4/UCA0TXD/UCA0SIMO

P4.4/TB4

XOUT

P5.3/UCB1CLK/UCA1STE

P6.3

P5.4/MCLK

DVCC

P5.2/UCB1SOMI/UCB1SCL

P6.4

P4.7/TBCLK

P6.7/A7/SVSIN

P5.1/UCB1SIMO/UCB1SDA

P6.5

P5.0/UCB1STE/UCA1CLK

P6.6

P4.6/TB6

VREF+

P4.5/TB5XIN

P4.1/TB1P1.0/TACLK/CAOUT

P4.3/TB3DVSS

P4.2/TB2DVSS

P4.0/TB0P1.1/TA0

P3.7/UCA1RXD/UCA1SOMIP1.2/TA1

P3.5/UCA0RXD/UCA0SOMIP1.4/SMCLK

P3.6/UCA1TXD/UCA1SIMO

P1.3/TA2

TMS

P2.5/R /CA5

OSC

P1.6/TA1

DVSS

P1.5/TA0 AVCC

409

472

463

436

3910

3613

3316

3415

PM OR RGC PACKAGE

(TOP VIEW)

MSP430F24x1

MSP430F23x

MSP430F24x(1)

MSP430F2410

www.ti.com

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

Device Pinout, MSP430F24x1

Oscillators

Basic Clock

System+

RAM

2kB

1kB

BOR

SVS/SVM

RST/NMI

DVCC DVSS

MCLK

Watchdog

WDT+

15/16-Bit

Timer_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

XOUT/

XT2OUT

JTAG

Interface

Ports

P1/P2

2x8 I/O

Interrupt

capability

USCI A0

UART/LIN,

IrDA, SPI

USCI B0

SPI, I2C

Comp_A+

Flash

16kB

8kB

Timer_B3

3 CC

Registers,

Shadow

Reg

ADC12

12-Bit

Channels

Ports

P3/P4

P5/P6

4x8 I/O

AVCC AVSS P1.x/P2.x

2x8

P3.x/P4.x

P5.x/P6.x

4x8

XIN/

XT2IN

SMCLK

ACLK

MDB

MAB

Hardware

Multiplier

MPY,

MPYS,

MAC,

MACS

MSP430F23x

MSP430F24x(1)

MSP430F2410

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

www.ti.com

Functional Block Diagram, MSP430F23x

Oscillators

Basic Clock

System+

RAM

2kB

4kB

BOR

SVS/SVM

RST/NMI

DVCC DVSS

MCLK

Watchdog

WDT+

15/16-Bit

Timer_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

XOUT/

XT2OUT

JTAG

Interface

Ports

P1/P2

2x8 I/O

Interrupt

capability

USCI A0

UART/LIN,

IrDA, SPI

USCI B0

SPI, I2C

Comp_A+

Flash

60kB

56kB

48kB

32kB

Timer_B7

7 CC

Registers,

Shadow

Reg

ADC12

12-Bit

Channels

Ports

P3/P4

P5/P6

4x8 I/O

AVCC AVSS P1.x/P2.x

2x8

P3.x/P4.x

P5.x/P6.x

4x8

XIN/

XT2IN

SMCLK

ACLK

MDB

MAB

Hardware

Multiplier

MPY,

MPYS,

MAC,

MACS

USCI A1

UART/LIN,

IrDA, SPI

USCI B1

SPI, I2C

MSP430F23x

MSP430F24x(1)

MSP430F2410

www.ti.com

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

Functional Block Diagram, MSP430F24x, MSP430F2410

Oscillators

Basic Clock

System+

RAM

2kB

4kB

BOR

SVS/SVM

RST/NMI

DVCC DVSS

MCLK

Watchdog

WDT+

15/16-Bit

Timer_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

XOUT/

XT2OUT

JTAG

Interface

Ports

P1/P2

2x8 I/O

Interrupt

capability

USCI A0

UART/LIN,

IrDA, SPI

USCI B0

SPI, I2C

Comp_A+

Flash

60kB

48kB

32kB

Timer_B7

7 CC

Registers,

Shadow

Reg

Ports

P3/P4

P5/P6

4x8 I/O

AVCC AVSS P1.x/P2.x

2x8

P3.x/P4.x

P5.x/P6.x

4x8

XIN/

XT2IN

SMCLK

ACLK

MDB

MAB

Hardware

Multiplier

MPY,

MPYS,

MAC,

MACS

USCI A1

UART/LIN,

IrDA, SPI

USCI B1

SPI, I2C

MSP430F23x

MSP430F24x(1)

MSP430F2410

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

www.ti.com

Functional Block Diagram, MSP430F24x1

MSP430F23x

MSP430F24x(1)

MSP430F2410

www.ti.com

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

Table 2. Terminal Functions, MSP430F23x

TERMINAL I/O DESCRIPTION

NAME NO.

AVCC 64 Analog supply voltage, positive. Supplies only the analog portion of ADC12.

AVSS 62 Analog supply voltage, negative. Supplies only the analog portion of ADC12.

DVCC 1 Digital supply voltage, positive. Supplies all digital parts.

DVSS 63 Digital supply voltage, negative. Supplies all digital parts.

P1.0/TACLK/CAOUT 12 I/O General-purpose digital I/O / Timer_A, clock signal TACLK input/Comparator_A output

P1.1/TA0 13 I/O General-purpose digital I/O / Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit

P1.2/TA1 14 I/O General-purpose digital I/O / Timer_A, capture: CCI1A input, compare: Out1 output

P1.3/TA2 15 I/O General-purpose digital I/O / Timer_A, capture: CCI2A input, compare: Out2 output

P1.4/SMCLK 16 I/O General-purpose digital I/O / SMCLK signal output

P1.5/TA0 17 I/O General-purpose digital I/O / Timer_A, compare: Out0 output

P1.6/TA1 18 I/O General-purpose digital I/O / Timer_A, compare: Out1 output

P1.7/TA2 19 I/O General-purpose digital I/O / Timer_A, compare: Out2 output

P2.0/ACLK/CA2 20 I/O General-purpose digital I/O / ACLK output/Comparator_A input

P2.1/TAINCLK/CA3 21 I/O General-purpose digital I/O / Timer_A, clock signal at INCLK

General-purpose digital I/O / Timer_A, capture: CCI0B input/Comparator_A output/BSL

P2.2/CAOUT/TA0/CA4 22 I/O receive/Comparator_A input

P2.3/CA0/TA1 23 I/O General-purpose digital I/O / Timer_A, compare: Out1 output/Comparator_A input

P2.4/CA1/TA2 24 I/O General-purpose digital I/O / Timer_A, compare: Out2 output/Comparator_A input

General-purpose digital I/O / input for external resistor defining the DCO nominal frequency/Comparator_A

P2.5/ROSC/CA5 25 I/O input

P2.6/ADC12CLK/CA6 26 I/O General-purpose digital I/O / conversion clock - 12-bit ADC/Comparator_A input

P2.7/TA0/CA7 27 I/O General-purpose digital I/O / Timer_A, compare: Out0 output/Comparator_A input

P3.0/UCB0STE/ UCA0CLK 28 I/O General-purpose digital I/O / USCI_B0 slave transmit enable/USCI A0 clock input/output

P3.1/UCB0SIMO/UCB0SDA 29 I/O General-purpose digital I/O / USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode

P3.2/UCB0SOMI/ UCB0SCL 30 I/O General-purpose digital I/O / USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode

P3.3/UCB0CLK/UCA0STE 31 I/O General-purpose digital I/O / USCI_B0 clock input/output, USCI A0 slave transmit enable

General-purpose digital I/O / USCI_A0 transmit data output in UART mode, slave data in/master out in SPI

P3.4/UCA0TXD/ UCA0SIMO 32 I/O mode

P3.5/UCA0RXD/ General-purpose digital I/O / USCI_A0 receive data input in UART mode, slave data out/master in in SPI

33 I/O

UCA0SOMI mode

P3.6 34 I/O General-purpose digital I/O

P3.7 35 I/O General-purpose digital I/O

P4.0/TB0 36 I/O General-purpose digital I/O / Timer_B, capture: CCI0A/B input, compare: Out0 output

P4.1/TB1 37 I/O General-purpose digital I/O / Timer_B, capture: CCI1A/B input, compare: Out1 output

P4.2/TB2 38 I/O General-purpose digital I/O / Timer_B, capture: CCI2A/B input, compare: Out2 output

P4.3 39 I/O General-purpose digital I/O

P4.4 40 I/O General-purpose digital I/O

P4.5 41 I/O General-purpose digital I/O

P4.6 42 I/O General-purpose digital I/O

P4.7/TBCLK 43 I/O General-purpose digital I/O / Timer_B, clock signal TBCLK input

P5.0 44 I/O General-purpose digital I/O

P5.1 45 I/O General-purpose digital I/O

P5.2 46 I/O General-purpose digital I/O

P5.3 47 I/O General-purpose digital I/O

P5.4/MCLK 48 I/O General-purpose digital I/O / main system clock MCLK output

P5.5/SMCLK 49 I/O General-purpose digital I/O / submain system clock SMCLK output

P5.6/ACLK 50 I/O General-purpose digital I/O / auxiliary clock ACLK output

General-purpose digital I/O / switch all PWM digital output ports to high impedance - Timer_B TB0 to

P5.7/TBOUTH/SVSOUT 51 I/O TB6/SVS comparator output

P6.0/A0 59 I/O General-purpose digital I/O / analog input A0 - 12-bit ADC

P6.1/A1 60 I/O General-purpose digital I/O / analog input A1 - 12-bit ADC

P6.2/A2 61 I/O General-purpose digital I/O / analog input A2 - 12-bit ADC

MSP430F23x

MSP430F24x(1)

MSP430F2410

SLAS547I –JUNE 2007–REVISED DECEMBER 2012

www.ti.com

Table 2. Terminal Functions, MSP430F23x (continued)

TERMINAL I/O DESCRIPTION

NAME NO.

P6.3/A3 2 I/O General-purpose digital I/O / analog input A3 - 12-bit ADC

P6.4/A4 3 I/O General-purpose digital I/O / analog input A4 - 12-bit ADC

P6.5/A5 4 I/O General-purpose digital I/O / analog input A5 - 12-bit ADC

P6.6/A6 5 I/O General-purpose digital I/O / analog input A6 - 12-bit ADC

P6.7/A7/SVSIN 6 I/O General-purpose digital I/O / analog input A7 - 12-bit ADC/SVS input

XT2OUT 52 O Output terminal of crystal oscillator XT2

XT2IN 53 I Input port for crystal oscillator XT2

RST/NMI 58 I Reset input, nonmaskable interrupt input, or bootstrap loader start (in flash devices)

TCK 57 I Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start.

TDI/TCLK 55 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.

TDO/TDI 54 I/O Test data output. TDO/TDI data output or programming data input terminal.

TMS 56 I Test mode select. TMS is used as an input port for device programming and test.

VeREF+ 10 I Input for an external reference voltage

VREF+ 7 O Output of positive terminal of the reference voltage in the ADC12

Negative terminal for the reference voltage for both sources, the internal reference voltage, or an external

VREF-/VeREF- 11 I applied reference voltage

XIN 8 I Input for crystal oscillator XT1. Standard or watch crystals can be connected.

XOUT 9 O Output for crystal oscillator XT1. Standard or watch crystals can be connected.

QFN Pad NA NA QFN package pad connection to DVSS recommended

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