3.3.2.1 IO Link Transceiver TIOL111DMWR
The TIOL111DMWR family of transceivers implements the IO-Link interface for industrial bidirectional, point-to
point communication. There are eight IO Link PHYs used in our Board. Each PHY is connected to a M12
connector. The PRG0_PRU1 and GPMC signals are connected to the enable, RX ,TX and Fault signals of the
PHYs via Muxes. The L+ pin requires 24 V, which is provided via the DC Jack.
3.3.2.2 Smart Switch TPS4H160BQPWPRQ1
The TPS4H160-Q1 device is fully protected quad channel smart high-side switch with four integrated 160-mΩ
NMOS power FET. The PRG0_PRU1 and GPMC signals from HSE connector is connected to MUX which routes
the signals either to Test Header or to the TPS4H160-Q1. The selection is done using on board jumpers. The
OUT pins from the high side switch is connected to the L+ signals of the eight M12 Connectors. The OUT
pins are controlled by Enable signals coming from the Mux. SEL and SEH are two pins to multiplex the shared
current-sense function among the four channels. The current sense analog output is grounded via 768Ω and
is connected to the AM64x EVM board via the ADC connector 68683-310LF . A 3.33K resistor is connected to
ground from the current limit pin to set the current limit threshold to 0.6A.
3.3.2.3 Serializer SN65HVS882
The SN65HVS882 is an eight channel, digital-input serializer for high-channel density digital input modules
in industrial automation. In combination with galvanic isolators the device completes the interface between
the high voltage signals on the field-side and the low-voltage signals on the controller side. Input signals are
current-limited and then validated by internal debounce filters. Each digital input operates as a controlled current
sink limiting the input current to a maximum value of I LIM. The current limit is derived from the reference current
via I LIM = n × IREF, and IREF is determined by IREF = VREF/RLIM. Thus, changing the current limit requires
the change of RLIM to a different value via: RLIM = n × VREF/I LIM. While the device is specified for a current
limit of 3.6 mA, (via RLIM = 25 kΩ) The DI signals from the M12 connectors are connected to the input channels
of the serializer. The serializer is SPI compatible Upon a low-level at the load input, LD, the information of the
field inputs, IP0 to IP7 is latched into the shift register. Taking LD high again blocks the parallel inputs of the shift
register from the field inputs. A low-level at the clock-enable input, CE, enables the clock signal, CLK, to serially
shift the data to the serial output, SOP. Data is clocked at the rising edge of CLK. Thus, after eight consecutive
clock cycles all field input data have been clocked out of the shift register and the information of the serial input,
SIP, appears at the serial output, SOP.
3.3.2.4 INA253
The INA253 features a 2-mΩ, precision, current-sensing resistor and a 80-V common-mode, zero-drift topology,
precision, excellent common-mode rejection ratio (CMRR), and features enhanced pulse width modulation
(PWM) rejection current-sensing amplifier integrated into a single package. High precision measurements are
enabled through the matching of the shunt resistor value and the current-sensing amplifier gain providing a
highly-accurate, system-calibrated solution.
3.3.2.5 LED Driver TLC59282
The TLC59282 is a 16-channel, constant-current sink driver. Each channel can be individually controlled via a
simple serial communications protocol that is compatible with 3.3 V or 5 V CMOS logic levels, depending on the
operating VCC. Once the serial data buffer is loaded, a rising edge on LATCH transfers the data to the LEDx
outputs. The BLANK pin can be used to turn off all OUTn outputs during power-on and output data latching to
prevent unwanted image displays during these times. The constant-current value of all 16 channels is set by a
single external resistor.
System Description www.ti.com
8TMDS64DC01EVM and TMDS243DC01EVM User's Guide SPRUJ06 – OCTOBER 2021
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