Texas Instruments PGA112 Manuel utilisateur

User's GuideSBOU073 – February 2009

PGA112 Evaluation Module

This user’s guide describes the characteristics, operation, and use of the PGA112 evaluation module(EVM). It covers all pertinent areas involved to properly use this EVM board. The document includes thephysical printed circuit board layout, schematic diagrams, and circuit descriptions.

Contents1 Overview ...................................................................................................................... 22 System Setup ................................................................................................................ 43 PGA112EVM Hardware Setup ............................................................................................. 94 PGA112 Software Overview .............................................................................................. 165 Bill of Materials ............................................................................................................. 23

List of Figures

1 Hardware Included with the PGA112EVM ................................................................................ 32 PGA112EVM Hardware Setup ............................................................................................. 43 PGA112_Test_Board Block Diagram ..................................................................................... 54 PGA112_Test_Board Schematic .......................................................................................... 65 USB_DAQ_Platform Block Diagram ...................................................................................... 96 Typical Hardware Connections ........................................................................................... 107 Connecting the Two EVM PCBs ......................................................................................... 118 Connecting Power to the EVM ........................................................................................... 129 Connecting the USB Cable ............................................................................................... 1310 PGA112EVM Default Jumper Settings .................................................................................. 1411 PGA112EVM Software—Functioning Properly ......................................................................... 1612 PGA112EVM Software—No Communication With the USB DAQ Platform ........................................ 1713 Scaled Inputs to PGA112/113 ............................................................................................ 1814 Selection of Internal Reference or DAC Reference .................................................................... 1815 PGA112/113 Bit Read Tables ............................................................................................ 1916 PGA112 Measurement Module Tab ..................................................................................... 2017 PGA112/113 Self-Test Function .......................................................................................... 22

List of Tables

1 Signal Definition of J1 (25-Pin Male DSUB) on PGA112_Test_Board ............................................... 72 Signal Definition of J2 (25-Pin Female DSUB) on PGA112_Test_Board ............................................ 83 PGA112_Test_Board Jumper Functions ................................................................................ 154 USB DAQ Platform Jumper Settings .................................................................................... 155 PGA112_Test_Board Parts List .......................................................................................... 23

Microsoft, Windows are registered trademarks of Microsoft Corporation.SPI is a trademark of Motorola Inc.I

C is a trademark of NXP Semiconductors.All other trademarks are the property of their respective owners.

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1 Overview

1.1 PGA112EVM Hardware

1.2 Related Documentation from Texas Instruments

1.3 If You Need Assistance

Overview

www.ti.com

This document provides the information needed to set up and operate the PGA112EVM evaluationmodule, a test platform for the PGA112 and PGA113 programmable gain amplifiers . For a more detaileddescription of the PGA112 family, please refer to the product data sheet (SBOS424 ) available from theTexas Instruments web site at http://www.ti.com . Additional support documents are listed in the section ofthis guide entitled Related Documentation from Texas Instruments .

The PGA112EVM is an evaluation module that is used to fully evaluate the PGA112 and PGA113programmable gain amplifiers. The PGA112EVM consists of two printed circuit boards (PCBs). One board(the USB DAQ Platform) generates the digital signals required to communicate with the PGA112, which ispart of the second board (PGA112_Test_Board), as well as support and configuration circuitry.

Throughout this document, the abbreviation EVM and the term evaluation module are synonymous withthe PGA112EVM.

Figure 1 shows the hardware included with the PGA112EVM kit. Contact the factory if any component ismissing. It is highly recommended that you check the TI web site at http://www.ti.com to verify that youhave the latest software. It is also recommended that you watch the QuickStart Video (included on thecompact disk) before using the PGA112EVM.

The complete kit includes the following items:•PGA112 test PCB•USB DAQ platform PCB•USB cable•CD-ROM containing this user's guide, product software, and a demonstration video

The following document provides information regarding Texas Instruments integrated circuits used in theassembly of the PGA112EVM. This user's guide is available from the TI web site under literature numberSBOU073 . Any letter appended to the literature number corresponds to the document revision that iscurrent at the time of the writing of this document. Newer revisions may be available from the TI web siteat http://www.ti.com/ , or call the Texas Instruments Literature Response Center at (800) 477-8924 or theProduct Information Center at (972) 644-5580. When ordering, identify the document by both title andliterature number.

Document Literature Number

PGA112 Product Data Sheet SBOS424USB DAQ Platform Users Guide SBOU056OPA333 Product Data Sheet SBOS351ADS1100 Product Data Sheet SBAS239

If you have questions about the PGA112 evaluation module, send an e-mail to the Linear ApplicationTeam at [email protected] . Include PGA112EVM as the subject heading.

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Overview

Figure 1. Hardware Included with the PGA112EVM

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1.4 Information About Cautions and Warnings

2 System Setup

USB DAQ

Platform

PGA112/113

Test Board

EVM

Power

Optional External DC and AC

source connection

AC DC

Optional DVM or

Oscilloscope

connection

System Setup

www.ti.com

This document contains caution statements.

CAUTION

This is an example of a caution statement. A caution statement describes asituation that could potentially damage your software or equipment.

The information in a caution or a warning is provided for your protection. Please read each cautioncarefully.

Figure 2 shows the system setup for the PGA112EVM. The PC runs software that communicates with theUSB DAQ Platform. The USB DAQ Platform generates the analog and digital signals used tocommunicate with the PGA112_Test_Board. Connectors on the PGA112_Test_Board allow the user toconnect the system power, precise analog inputs, and digital controls that select these analog inputs.

Figure 2. PGA112EVM Hardware Setup

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2.1 Theory of Operation for PGA112_Test_Board Hardware

PGA112/

PGA113

V Supply

Switched 5.0V Power

DUT

General-Purpose Digital I/O

SPI Communication

MUX Logic Control

Analog DAC settings

for the inputs

Analog-to-digital

inputs for precision

measurements

Connection to

Optional External

Source

25-Pin

Male DSUB Signals

From USB DAQ Platform

25-Pin

Female DSUB Signals

From USB DAQ Platform

Optional

External SPI

Address

Jumpers

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System Setup

Figure 3 presents a block diagram of the PGA112_Test_Board. The functionality of this PCB is relativelysimple. It provides connections to the I

C™ and general-purpose input/outputs (GPIO) on the USB DAQPlatform board. It also provides connection points for external connections of the shunt voltage, busvoltage, and GND.

Figure 3. PGA112_Test_Board Block Diagram

See Figure 4 for an illustration of the PGA112_Test_Board schematic. The J1 connector ports theanalog-to-digital converters (ADCs), digital-to analog converters (DACs), and SPI™ control. The J2connector ports the control bits for the input and output switches.

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System Setup

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Figure 4. PGA112_Test_Board Schematic

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2.2 Signal Definitions of J1 (25-Pin Male DSUB)

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System Setup

Table 1 lists the different signals connected to J1 on the PGA112_Test_Board. This table also identifiessignals connected to pins on J1 that are not used on the GA112_Test_Board.

Table 1. Signal Definition of J1 (25-Pin Male DSUB) on PGA112_Test_Board

J1 Pin Signal Used On This EVM? PGA112 Pin

1 DAC A Yes DAC12 DAC B Yes DAC23 DAC C Yes DAC34 DAC D Yes V

REF

_DAC5 ADS1+ Yes ADS1+6 ADS1– Yes ADS1–7 ADS2+ Yes ADS2+8 ADS2– Yes ADS2–9 I2C_SCK No —10 I2C_SDA2 No —11 ONE_WIRE No —12 I2C_SCK_ISO No —13 I2C_SDA_ISO No —14 XTR_LOOP+ No —15 XTR_LOOP– No —16 INA– No —17 V

DUT

Yes V

DUT

18 V

No V

19 +15V No —20 –15V No —21 GND Yes GND22 SPI_SCK Yes SPI_SCK23 SPI_CS1 Yes SPI_CS124 SPI_DOUT Yes SPI_DOUT25 SPI_DIN1 Yes SPI_DIN1

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2.3 Signal Definition of J2 (25-Pin Female DSUB)

System Setup

www.ti.com

Table 2 summarizes the different signals connected to J2 on the PGA112_Test_Board. This table alsoidentifies signals connected to pins on J2 that are not used on the PGA112_Test_Board.

Table 2. Signal Definition of J2 (25-Pin Female DSUB) on PGA112_Test_Board

J2 Pin Signal Used On This EVM? PGA112 Pin

1 NC No —2 CTRL1 Yes CTRL13 CTRL2 Yes CTRL24 CTRL3 Yes CTRL35 CTRL4 Yes CTRL46 CTRL5 Yes CTRL57 CTRL6 Yes CTRL68 CTRL7 Yes CTRL79 CTRL8 Yes CTRL810 MEAS1 No —11 MEAS2 No —12 MEAS3 No —13 MEAS4 No —14 MEAS5 No —15 MEAS6 No —16 MEAS7 No —17 MEAS8 No —18 SPI_SCK Yes SPI_SCK19 SPI_CS2 Yes SPI_CS220 SPI_DOUT2 Yes SPI_DOUT221 SPI_DIN2 Yes SPI_DIN222 V

DUT

Yes V

DUT

23 V

Yes V

24 GND Yes GND25 GND Yes GND

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2.4 Theory of Operation For USB_DAQ_Platform

TUSB3210

8052 C

with USB Interface

and UART

USB Bus

From Computer

3.3V

Regulator

Adjustable

Regulator

(2.7V to 5.5V)

VmC

3.3V

V_USB

8Kx8 Byte

EEPROM

Buffers and

Latches

Power

Switching

(2.7V to 5.5V)

DUT

Switched Power

I C, SPI

Control Bits, and

Measure Bits

External

Power

Reset Button

and

Power-On Reset

USB DAQ

Platform

3 PGA112EVM Hardware Setup

3.1 Electrostatic Discharge Warning

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PGA112EVM Hardware Setup

Figure 5 shows the block diagram for the USB DAQ Platform. This platform is a general-purpose dataacquisition system that is used on several different Texas Instruments evaluation modules. The details ofits operation are included in a separate document (available for download at www.ti.com). The blockdiagram shown in Figure 5 gives a brief overview of the platform. The primary control device on the USBDAQ Platform is the TUSB3210 .

Figure 5. USB_DAQ_Platform Block Diagram

The PGA112EVM hardware setup involves connecting the two PCBs of the EVM together, applyingpower, connecting the USB cable, and setting the jumpers. This section presents the details of thisprocedure.

Many of the components on the PGA112EVM are susceptible to damage by electrostatic discharge (ESD).Customers are advised to observe proper ESD handling precautions when unpacking and handling theEVM, including the use of a grounded wrist strap at an approved ESD workstation.

CAUTION

Failure to observe ESD handling procedures may result in damage to EVMcomponents.

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3.2 Typical Hardware Connections

PGA112EVM Hardware Setup

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The PGA112EVM hardware setup involves connecting the two PCBs of the EVM together, applyingpower, and connecting an external shunt and load. The external connections may be the real-worldsystem that the PGA112 will be incorporated into. Figure 6 shows the typical hardware connections.

Figure 6. Typical Hardware Connections

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