Texas Instruments LMK05318EVM Manuel utilisateur

LMK05318EVM

User's Guide

Literature Number: SNAU236A

June 2018–Revised December 2018

2SNAU236A–June 2018–Revised December 2018

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Table of Contents

Contents

Preface ........................................................................................................................................ 5

1 EVM Quick Start................................................................................................................... 7

1.1 Device Revision Identification .......................................................................................... 8

1.2 Default EVM Configuration.............................................................................................. 8

2 Device Under Test .............................................................................................................. 10

2.1 Device Start-Up Modes ................................................................................................ 10

3 EVM Configuration ............................................................................................................. 11

3.1 Power Supply ........................................................................................................... 13

3.2 Logic Inputs and Outputs.............................................................................................. 15

3.3 XO Input ................................................................................................................. 18

3.4 Reference Clock Inputs ............................................................................................... 20

3.5 Clock Outputs ........................................................................................................... 20

3.6 Status Outputs and LEDs.............................................................................................. 21

4 EVM Schematics ................................................................................................................ 22

5 EVM Layouts...................................................................................................................... 33

6 EVM Bill of Materials........................................................................................................... 45

Appendix A Software .................................................................................................................. 51

A.1 Software Installation (One-Time).................................................................................... 51

A.2 TICS Pro Usage for LMK05318 ..................................................................................... 51

Revision History.......................................................................................................................... 52

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SNAU236A–June 2018–Revised December 2018

List of Figures

1 LMK05318EVM With Default Jumper and DIP Switch Settings ....................................................... 6

2 Key Components - EVM Top Side ...................................................................................... 12

3 Key Components - EVM Bottom Side ................................................................................... 13

4 Default Power Jumper Configuration .................................................................................... 14

5 XO Input Interface (1 of 2) - 48.0048-MHz Oscillator and SMA Ports .............................................. 19

6 XO Input Interface (2 of 2) - LMK61E2 Oscillator ..................................................................... 20

7 Clock Input Interface - PRIREF (Similar for SECREF)................................................................ 20

8 Clock Output Interface - OUT0 (Similar for OUT1-OUT7) ............................................................ 21

9 Schematic 1 - Power Supplies............................................................................................ 22

10 Schematic 2 - Power Distribution ........................................................................................ 23

11 Schematic 3 - DC-DC Regulator ......................................................................................... 24

12 Schematic 4 - LMK05318 and XO Input Interfaces.................................................................... 25

13 Schematic 5 - Clock Input Interfaces .................................................................................... 26

14 Schematic 6 - Clock Output Interfaces (OUT0 to OUT3) ............................................................. 27

15 Schematic 7 - Clock Outputs (OUT4 to OUT7) ........................................................................ 28

16 Schematic 8 - Logic I/O Interfaces....................................................................................... 29

17 Schematic 9 - USB MCU and I2C/SPI Jumper Block.................................................................. 30

18 Schematic 10 - LMK61E2 Oscillator..................................................................................... 31

19 Schematic 11 - DUT Test Socket ........................................................................................ 32

20 Top Composite View....................................................................................................... 33

21 Top Solder Mask ........................................................................................................... 34

22 Layer 1 (Top Side) - Clock I/Os, Logic, and Power Routing, Ground Fill........................................... 35

23 Layer 2 - Ground Plane ................................................................................................... 36

24 Layer 3 - Logic Routing, Ground Fill..................................................................................... 37

25 Layer 4 - Power Routing, Ground Fill.................................................................................... 38

26 Layer 5 - Power and Ground Planes .................................................................................... 39

27 Layer 6 - Logic Routing, Ground Fill..................................................................................... 40

28 Layer 7 - Ground Plane ................................................................................................... 41

29 Layer 8 (Bottom Side, View From Top) - Logic and Power Routing, Ground Fill.................................. 42

30 Bottom Solder Mask ....................................................................................................... 43

31 Bottom Composite View................................................................................................... 44

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List of Tables

1 Default Jumper and DIP Switch Settings ................................................................................ 7

2 Device Revision IDs......................................................................................................... 8

3 Default Configuration - EEPROM Start-Up Modes ..................................................................... 9

4 Device Start-Up Modes.................................................................................................... 10

5 Key EVM Components .................................................................................................... 11

6 Suggested DUT Power Configurations.................................................................................. 14

7 Suggested XO Power Configurations.................................................................................... 15

8 Logic Pin Mapping Tables................................................................................................. 15

9 Logic Pin Descriptions - EEPROM + I2C Mode (HW_SW_CTRL = 0) .............................................. 16

10 Logic Pin Descriptions - EEPROM + SPI Mode (HW_SW_CTRL = Float) ........................................ 17

11 Logic Pin Descriptions - ROM + I2C Mode (HW_SW_CTRL = 1).................................................... 18

12 Bill of Materials ............................................................................................................. 45

SNAU236A–June 2018–Revised December 2018

Preface

SNAU236A–June 2018–Revised December 2018

Introduction

Overview

The LMK05318EVM is an evaluation module for the LMK05318 Network Clock Generator and

Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.

The LMK05318 integrates two Analog PLLs (APLL) and one Digital PLL (DPLL) with programmable loop

bandwidth. The EVM includes SMA connectors for clock inputs, oscillator inputs, and clock outputs to

interface the device with 50-Ωtest equipment. The onboard XO allows the LMK05318 to be evaluated in

free-running, locked, or holdover mode of operation. The EVM can be configured through the onboard

USB microcontroller (MCU) interface using a PC with TI's TICS Pro software graphical user interface

(GUI). TICS Pro can be used to program the LMK05318 registers and on-chip EEPROM, which enables a

custom clock configuration on power up.

Trademarks

All trademarks are the property of their respective owners.

Features

• LMK05318 DUT:

– DPLL with programmable loop bandwidth for input jitter and wander attenuation

– Two Analog PLLs (APLLs) for flexible low-jitter clock generation

– Two clock inputs supporting hitless switching and holdover

– Eight differential clock outputs, or combination of differential and up to eight LVCMOS clocks

– On-chip EEPROM for custom start-up clocks

• SMA ports for clock input, oscillator inputs, and clock outputs

• Onboard oscillator options: 48.0048-MHz XO and LMK61E2 (I2C-programmable)

• USB MCU interface for I2C/SPI and GPIO pin control using TICS Pro GUI

• Status LEDs for power supplies and device status indicators

What is Included

• LMK05318EVM

• Mini-USB cable

What is Needed

• Windows PC with TICS Pro Software GUI

• Test Equipment

– DC power supply (5 V, 1 A)

– Real-time oscilloscope

– Source signal analyzer

– Precision frequency counter

– Signal generator / reference clock

What is Needed

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Introduction

Figure 1. LMK05318EVM With Default Jumper and DIP Switch Settings

SNAU236A–June 2018–Revised December 2018

LMK05318EVM User's Guide

User's Guide

SNAU236A–June 2018–Revised December 2018

LMK05318EVM User's Guide

1 EVM Quick Start

This quick start guide can be followed to evaluate the LMK05318 DUT with the default EVM and device

configurations summarized in Section 1.2 and Table 3.

1. Verify the EVM default jumper and DIP switch settings shown in Figure 1 and Table 1:

Table 1. Default Jumper and DIP Switch Settings

CATEGORY REF DES POSITION DESCRIPTION

Power

JP1 Tie pins 1-2 DUT VDD = 3.3 V from LDO1

JP2 Tie pins 1-2 DUT VDDO = 1.8 V from LDO2

JP3 Tie pins 1-2 LDO3 IN powered from VIN1 external supply

JP4 Tie pins 1-2 1.8 V selected as LDO2 output voltage

JP16 Tie pins 1-2 VDDGPIO = 3.3 V

JP17 Tie pins 1-2 XO VCC = 3.3 V from LDO3

JP21 Tie pins 2-3 LMK61E2 VCC = GND (Powered off)

JP22 Tie pins 2-3 DC-DC Regulator VIN = GND (Powered off)

JP23 Tie pins 2-3

Communication JP20 Tie pins 1-2, 3-4,

11-12, and 13-14 DUT I2C connected to MCU

S9 S9[1:2] = OFF LMK61E2 I2C not connected to MCU

DUT Control

Pins

JP18 Tie pins 2-3 REFSEL = 0: PRIREF selected if using Manual Pin mode

JP19 Tie pins 2-3 HW_SW_CTRL = 0: EEPROM+I2C Start-up Mode selected

S2 S2[1:3] = OFF

S2[4] = ON STATUS0 = Hi-Z: Output state shown on D7. Pin not connected to MCU.

S3 S3[1:3] = OFF

S3[4] = ON STATUS1/FDEC = Hi-Z: Output state shown on D8. Pin not connected to

MCU.

S5 S5[1] = ON

S5[2:3] = OFF GPIO0/SYNCN = 1: SYNC deasserted. Pin not connected from MCU.

S6 S6[1] = OFF

S6[2:3] = ON GPIO1/SCS = 0: I2C slave address = 0x64. Pin connected to MCU.

S7 S7[1] = OFF

S7[2:3] = ON GPIO2/SDO/FINC = 0: Not used by default. Pin connected to MCU.

DUT Loop Filter

Pins

S1 S1[1] = ON

S1[2:4] = OFF LF1 = 0.47 μF

S10 S10[1] = ON

S10[2] = OFF LF2 = 0.1 μF

2. Connect +5 V from an external DC power supply (1-A limit) across the VIN1 and GND terminals of

header J1 (pins 1 and 4).

3. Toggle switch S4 (PDN/RESET) to reinitialize the DUT registers from on-chip EEPROM, if needed.

4. Check that the LEDs D7 and D8 are both ON if there is no valid clock input on PRIREF or SECREF.

This indicates that the DPLL is not locked and that the DPLL holdover is active.

a. When the DPLL is not locked, the clock outputs will free-run and track the frequency stability and

accuracy of the XO (Y1).

5. Connect an external 25-MHz single-ended clock input to either the PRIREF or SECREF SMA port to

EVM Quick Start

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LMK05318EVM User's Guide

lock the DPLL.

6. Check that the LEDs D7 and D8 are both OFF after a valid clock input is detected. This indicates the

that DPLL is locked and that the DPLL holdover is not active.

a. When the DPLL is locked, the output clocks should track the frequency accuracy of the clock input.

7. Check for any clock outputs on the OUT[0:7] SMA ports. TI recommends the following best practices

when making noise-sensitive performance measurements:

a. Use an appropriate balun to interface a differential output clock to the single-ended input of an RF

test equipment (phase noise or spectrum analyzer).

b. Properly terminate any active output clock trace by placing a 0-Ωload on the SMA port to minimize

noise due to reflections. Otherwise, disable any unused outputs by register programming.

NOTE: OUT7_P/N traces are DC-coupled to its SMA ports to allow evaluation of low-frequency

outputs (like 1 PPS) as well as LVCMOS or HCSL output types. Add an external DC blocking

cap between the OUT7 port and the input of any test equipment that cannot tolerate DC

bias.

8. Connect the USB cable from connector J35 to the PC and configure the device through the TICS Pro

software to program the LMK05318 through the USB interface.

a. See Appendix A for TICS Pro installation and usage.

TICS Pro uses the "USB2ANY" API software driver to control the USB MCU interfaces (I2C/SPI and Logic

pins) on the EVM. TICS Pro can be used to access the device registers and program the device EEPROM

for a different start-up configuration.

1.1 Device Revision Identification

Pre-production devices may have been distributed to customers as engineering sample parts or mounted

on pre-release EVMs. If a pre-production device or EVM is detected, TI recommends that the user replace

the pre-production device with a production device or EVM when available. Production samples and EVMs

can be ordered from product folder or requested through your local TI Field Sales representative.

The user can read the Device Revision ID (REVID) Register R3 to find the device revision in the TICS Pro

GUI or other serial host interface. See Table 2.

Table 2. Device Revision IDs

REVID REGISTER R3 VALUE DEVICE REVISION COMMENT

0x00 Pre-production device TI recommends to replace with a production device or EVM,

or contact TI Field Sales for technical support.

0x11 Production device Okay to use.

1.2 Default EVM Configuration

• Power Supplies:

– VIN1: 5 V (External supply to onboard LDO regulators)

– DUT VDD: 3.3 V from LDO1 (U3)

– DUT VDDO: 1.8 V from LDO2 (U3)

– XO: 3.3 V from LDO3 (U4)

– VDDGPIO: 3.3 V from VDD

• LMK05318 DUT (U5):

– Clock Inputs:

• PRIREF and SECREF: DC-coupled from SMA ports

– Clock Outputs:

• OUT[0:6]: AC-coupled to SMA ports

• OUT7: DC-coupled to SMA ports

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EVM Quick Start

SNAU236A–June 2018–Revised December 2018

LMK05318EVM User's Guide

• Oscillators onboard:

– XO (Y1), Default: 48.0048 MHz, 3.3 V, LVCMOS, low-jitter, ±25-ppm stability

– XO (U10), Alternate: LMK61E2, 10 to 1000 MHz (I2C-programmable), 3.3 V, Differential, low-jitter,

±50-ppm stability

NOTE: The EEPROM image of the LMK05318 was custom programmed to demonstrate the default

configuration in Table 3, which is different from the EEPROM image of generic factory-

programmed devices.

(1) Clock input frequency thresholds (ppm) are relative to the frequency accuracy of the XO input.

Table 3. Default Configuration - EEPROM Start-Up Modes

DEVICE START-UP MODE EEPROM + I2C MODE

(HW_SW_CTRL = 0) EEPROM + SPI MODE

(HW_SW_CTRL = Float)

HW_SW_CTRL (JP19)

Jumper Setting Tie pins 2-3 Tie pins 2-4 (open)

MCU I2C/SPI (JP20)

Jumper Settings Tie pins 1-2, 3-4, 11-12 and 13-14

MCU I2C interface to DUT Tie pins 7-8, 9-10, 11-12, and 13-14

MCU SPI interface to DUT

GPIO1/SCS (S6)

Jumper Settings S6[1] = OFF, S6[2:3] = ON

GPIO1 = 0: I2C Address = 0x64h S6[1] = OFF, S6[2:3] = ON

SPI SCS input to MCU

GPIO2/SDO/FINC (S7)

Jumper Settings S7[1] = OFF, S7[2:3] = ON

Not used by default S7[1] = OFF, S7[2:3] = ON

SPI SDO output to MCU

XO Input 48.0048-MHz DIFF or LVCMOS

(On-chip termination disabled)

PRIREF and SECREF Clock Inputs 25-MHz DIFF or LVCMOS

(On-chip termination disabled)

DPLL Clock Input Assignment PRIREF, SECREF

(Highest to lowest priority order)

DPLL Clock Input Selection Manual Fallback mode with Pin Select

PLL Mode DPLL Mode with APLL2 disabled

DPLL Loop Bandwidth 100 Hz

DPLL TDC Frequency 25 MHz

APLL1 VCO Frequency 2500 MHz

APLL2 VCO Frequency n/a (APLL2 disabled)

OUT[0:1] Output 156.25 MHz AC-LVPECL (from APLL1)

OUT[2:3] Output 156.25 MHz AC-LVPECL (from APLL1)

OUT[4] Output 156.25 MHz AC-LVPECL (from APLL1)

OUT[5] Output 156.25 MHz AC-LVPECL (from APLL1)

OUT[6] Output 156.25 MHz AC-LVPECL (from APLL1)

OUT[7] Output 156.25 MHz HCSL (from APLL1)

(On-chip termination disabled)

PRIREF and SECREF

Frequency Detector Thresholds (1) Not Enabled

PRIREF and SECREF

Window Detector Thresholds 33.6 ns (Early) < Valid REF Input Period < 46.4 ns (Late)

DPLL Frequency Lock

Detector Thresholds DPLL Locked < 1 ppm, DPLL Unlocked > 10 ppm

STATUS0 Output DPLL Loss of Lock (active high)

STATUS1 Output DPLL Holdover Active (active high)

Device Under Test

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LMK05318EVM User's Guide

2 Device Under Test

The evaluation module is shipped with the LMK05318 DUT (U5) soldered down. The pin 1 position of the

48-pin QFN package is indicated by a dot symbol in top silkscreen. Alternatively, the U5 can be

unmounted and a test socket (XU1) can be populated. See for the socket part number. TI recommends

populating the socket with the hinge on the left-hand side (towards OUT[0:3] ports) and the latch on the

right-hand side.

2.1 Device Start-Up Modes

The LMK05318 can start-up in one of three modes depending on the 3-level input level sampled on the

HW_SW_CTRL pin upon power-on reset (POR). The start-up modes are listed in Table 4 and determine

the following:

1. The memory bank (EEPROM or ROM) used to initialize the registers upon start-up.

2. The serial interface (I2C or SPI) used for register access.

3. The logic pin definitions.

The I2C or SPI interface allows for register access to configure the device after start-up and monitor its

status. The register map configurations are the same for I2C and SPI.

See Section 3.2 for detailed descriptions of the logic pins for each start-up mode.

(1) The input levels on these pins are sampled only during POR.

(2) FINC and FDEC pin controls are only available when DCO mode and GPIO pin control are enabled by registers.

Table 4. Device Start-Up Modes

HW_SW_CTRL(1)

INPUT LEVEL START-UP MODE MODE DESCRIPTION

0EEPROM + I2C

(Soft pin mode)

Registers are initialized from EEPROM, and I2C interface is enabled with slave

address 11001xxb. Logic pins:

• SDA/SDI, SCL/SCK: I2C Data, I2C Clock

• GPIO0/SYNCN: Output Sync (active low)

• GPIO1/SCS(1): I2C Address LSB Select (Low = 00b, Float = 01b, High = 10b)

• GPIO2/SDO/FINC(2): DPLL DCO Frequency Increment (active high)

• STATUS1/FDEC(2): DPLL DCO Frequency Decrement (active high), or Status

output

Float

(VIM)EEPROM + SPI

(Soft pin mode)

Registers are initialized from EEPROM, and SPI interface is enabled. Logic pins:

• SDA/SDI, SCL/SCK: SPI Data In (SDI), SPI Clock (SCK)

• GPIO0/SYNCN: Output Sync (active low)

• GPIO1/SCS: SPI Chip Select (SCS)

• GPIO2/SDO/FINC: SPI Data Out (SDO)

1ROM + I2C

(Hard pin mode)

Registers are initialized from the ROM page selected by GPIO pins, and I2C interface

is enabled with the 7-bit slave address of 0x64. Logic pins:

• SDA/SDI, SCL/SCK: I2C Data, I2C Clock

• GPIO[2:0](1): ROM page select at POR

• After POR, GPIO2/SDO/FINC and STATUS1/FDEC pins can function the same

as for HW_SW_CTRL = 0 if enabled by registers.

TI suggests to use the EEPROM mode when either of the following is true:

• A single custom start-up frequency configuration is required from a single OPN.

• A host device is able to program the registers (and EEPROM, if needed) with a new configuration after

power-up through I2C or SPI. SPI is not supported by ROM mode.

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