Texas Instruments LMK00725EVM Manuel utilisateur

LMK00725EVM User’s Guide

User's Guide

Literature Number: SNOU126

September 2013

Contents

1 Introduction ........................................................................................................................ 4

2 Features ............................................................................................................................. 4

3 Setup ................................................................................................................................. 4

3.1 Input/ Output Connector Description .................................................................................. 4

4 Operation ........................................................................................................................... 5

5 PCB Layout ........................................................................................................................ 7

6 Schematic ......................................................................................................................... 11

7 Bill of Materials ................................................................................................................. 12

2Table of Contents SNOU126–September 2013

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List of Figures

1 LMK00725 Input Structure and Default Input Termination ............................................................ 5

2 Top Layer .................................................................................................................... 7

3 Inner Layer 2 (Ground Plane, Inverted).................................................................................. 8

4 Inner Layer 3 (Supply Plane, Inverted)................................................................................... 9

5 Bottom Layer............................................................................................................... 10

6 LMK00725EVM Schematic............................................................................................... 11

List of Tables

1 Device and Package Configurations ..................................................................................... 4

2 LMK00725EVM Bill of Materials ........................................................................................ 12

SNOU126–September 2013 List of Figures

User's Guide

SNOU126–September 2013

LMK00725EVM User’s Guide

1 Introduction

The LMK00725 is a low skew, high performance clock fanout buffer, which distributes up to five 3.3 V

LVPECL outputs. The clocks are derived from one of two selectable inputs, which can accept differential

or single-ended input signals.

This evaluation module (EVM) is designed to demonstrate the functionality and electrical performance of

the LMK00725 device. For optimum performance, the board is equipped with 50-ohm SMA connectors

and 50-ohm controlled impedance traces.

Table 1. Device and Package Configurations

DESIGNATOR IC PACKAGE

U1 LMK00725 PW-20 (TSSOP 20 pin)

2 Features

• Easy to use evaluation board to fan-out up to five LVPECL clocks with low phase noise/jitter

• Accepts differential or single-ended/LVCMOS input clock

• Device control pins configurable through jumpers

• Board power at 3.3-V for VCC

3 Setup

This section describes the jumpers and connectors on the EVM as well and how to properly connect, set

up and use the LMK00725EVM.

With this EVM, one could distribute one of two input clocks to up to 5 LVPECL outputs. Therefore, a

minimum of one clock source is needed and appropriate test equipment to observe or measure the

outputs.

3.1 Input/ Output Connector Description

Connectors:

•CLK0 and nCLK0 SMA connectors are used to interface an external AC-coupled clock input to the first

of the two differential input pairs (CLK0, nCLK0) of the device.

•CLK1 and nCLK1 SMA connectors are used to interface an external AC-coupled clock input to the

second of the two differential input pairs (CLK1, nCLK1) of the device..

•Q1,nQ1 and Q3,nQ3 SMA connectors are used to distribute two of the five differential clock outputs.

The other three differential clock outputs are not connected to the traces, so their SMA connectors are

not populated by default.

•PWR is a 3-pin header used to 3.3-V supply power to the board/device. VCC and GND pins are

labeled on the top side of the board. The center pin is not connected (N/C).

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Operation

Jumpers:

•CLK-SEL selects between one of two inputs.

– 0 (position 1-2) = Select CLK0, nCLK0 inputs

– 1 (position 2-3) = Select CLK1, nCLK1 inputs

•CLK-EN selects between U1 clock enabled or disabled modes.

– 0 (position 1-2) = Clock Disabled

– 1 (position 2-3) = Clock Enabled (normal operation)

4 Operation

Power:

Before, applying any clock inputs, supply the board with 3.3 V and ground at VCC and GND pins of the

PWR header. Make sure the supply current being drawn is less than 115 mA.

Inputs:

Figure 1 shows the LMK00725 input structure. The internal 51 kΩpull-up and pull-down resistors work

with the external 50 Ωtermination resistors, which bias the device inputs to mid-rail. Therefore, AC-

coupled clock sources from 0.15Vpp to 1.3Vpp (50 Ωterminated) can be tied to either of the two

differential clock inputs. With the default input termination shown in Figure 1, the input SMAs expect a 10

0Ωdifferential clock source. Note that with the default input configuration, the differential input has only

very small offset voltage (~3.2 mV) so that when the selected clock inputs are left open/floating, the

outputs could have the tendency to chatter.

With DC-coupled clock sources, use a “DC-block” at the input SMAs to ensure DUT input voltage range

compliance. Alternatively, adjust the clock source DC bias (if available) to make sure the LMK00725 input

voltage range is not violated.

Figure 1. LMK00725 Input Structure and Default Input Termination

The clock inputs can accommodate a differential input or single-ended input signal with the proper

external input termination using the various component options on the board. Refer to the datasheet for

input interface application circuits.

To achieve the best possible additive jitter and noise floor performance, it is recommended to drive the

CLK/nCLK pair using an input signal with fast slew rate of 3 V/ns (differential) or higher. Driving the input

with a lower slew rate can degrade the additive jitter and noise floor performance. For this reason, a

differential input signal (e.g. LVPECL), is recommended because it typically provides higher slew rate and

common-mode noise rejection compared to a single-ended input (LVCMOS/LVTTL or sine-wave, for

example).

SNOU126–September 2013 LMK00725EVM User’s Guide

Operation

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Outputs:

By default, two of the five LVPECL output pairs are connected to the traces and SMA connectors via

series 0-Ωresistors. The remaining three LVPECL pairs are not connected to the traces (0-Ωresistors not

installed) and thus do not have SMA connectors installed. The routed outputs have 180-Ωbias resistors to

ground and are AC-coupled to the SMA connectors to allow direct connections to RF instruments via SMA

cables for test and evaluation. The AC-coupled outputs should be terminated with single-ended 50 Ωor

100 Ωdifferential loads.

To minimize reflections and signal integrity issues, it is recommended to terminate any driven output trace

with a 50-ΩSMA load termination, or otherwise disconnect any unused output from the trace by removing

the 0-Ωseries resistor (R30 to R39).

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PCB Layout

5 PCB Layout

Figure 2. Top Layer

SNOU126–September 2013 LMK00725EVM User’s Guide

PCB Layout

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Figure 3. Inner Layer 2 (Ground Plane, Inverted)

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PCB Layout

Figure 4. Inner Layer 3 (Supply Plane, Inverted)

SNOU126–September 2013 LMK00725EVM User’s Guide

PCB Layout

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Figure 5. Bottom Layer

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