Texas Instruments TAS5086-5186V6EVM Manuel utilisateur
TAS5086-5186V6EVM User’s GuideEvaluation Module for the TAS5086 6-Channel DigitalAudio PWM Processor and Power Output StageTAS5186A Digital Amplifier
User's Guide
JULY 2006
SLEU073
Contents
1 Overview ................................................................................................................... 51.1 TAS5086-5186V6EVM Features.................................................................................. 61.2 PCB Key Map ....................................................................................................... 6
2 System Interfaces ...................................................................................................... 72.1 Power Supply (PSU) Interface (J901) ............................................................................ 72.2 Loudspeaker Connectors (J101 …J106) ....................................................................... 82.3 Control Interface (J40) ............................................................................................. 82.4 Digital Audio Interface (J60) ..................................................................................... 10
3 Protection ................................................................................................................ 113.1 Short-Circuit Protection and Fault-Reporting Circuitry ....................................................... 113.2 Device Fault Reporting ........................................................................................... 11
4 Related Documentation from Texas Instruments .......................................................... 134.1 Trademarks ........................................................................................................ 13
Important Notices ............................................................................................................... 14
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List of Figures
1-1 Integrated PurePath Digital™ Amplifier System ......................................................................... 61-2 Physical Structure for TAS5086-5186V6EVM (Rough Outline) ....................................................... 62-1 Recommended Power-Up Sequence ..................................................................................... 72-2 J901 Pin Numbers ........................................................................................................... 72-3 J101 . . . J106 Pin Numbers ................................................................................................ 8
List of Tables
2-1 Recommended Supply Voltages ........................................................................................... 72-2 J901 Pin Description ........................................................................................................ 82-3 J101 . . . J106 Pin Description ............................................................................................. 82-4 J40 Pin Description .......................................................................................................... 82-5 J60 Pin Description ........................................................................................................ 103-1 TAS5142 Warning/Error Signal Decoding .............................................................................. 11
4List of Figures SLEU073 – JULY 2006Submit Documentation Feedback
Chapter 1SLEU073 – JULY 2006
Overview
The TAS5086-5186V6EVM PurePath Digital™ customer evaluation amplifier moduledemonstrates two audio integrated circuits, TAS5086 and TAS5186ADDV, from TexasInstruments (TI).
The TAS5086DBT is a high-performance 32-bit (24-bit input) multichannel PurePathDigital pulse width modulator (PWM) based on Equibit™ technology, with a fullysymmetrical AD modulation scheme. It accepts input sample rates from 32 kHz to192 kHz.
The TAS5186ADDV is a high-performance, 6-channel, digital-amplifier power stage,with an improved protection system. The TAS5186A used in standard PowerPAD™packages is capable of driving a 6R single-ended load up to 30 W per eachfront/satellite channel, and a 3R single-ended subwoofer greater than 60 W at 10%THD+N performance.
This EVM, together with a TI input-USB board, is a complete 5.1-channel digital audioamplifier system, which includes digital input (S/PDIF), analog inputs, interface to PC,and DAP features, such as digital volume control, input and output multiplexers, automute, and simple bass management.
This system is designed for home-theater applications, such as flatscreen TVs, DVDminicomponent systems, home theater in a box (HTIB), or DVD receivers.
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1.1 TAS5086-5186V6EVM Features
Input-USB board TAS5086-5186V6EVM Module
6 Channel
Analog Input
USB
Interface
Optical
and
Coaxial
S/PDIF Input
I2C Bus
Control Interface
I2S Bus
Channel 1 (SE)
Channel 3 (SE)
Channel 5 (SE)
Channel 4 (SE)
Channel 2 (SE)
TAS5186A
TAS5086
POWER SUPPLY
Channel 6 (SE)
1.2 PCB Key Map
SPEAKER OUTPUTS
6 CHANNEL
POWER STAGE
TAS5186A
INPUT SIGNAL
INTERFACE (J60)
CONTROL
INTERFACE (J40)
J104
PSU
INTERFACE
(J901)
5V
Regulator
Gate Drive
Regulator
J103 J105 J106 J102 J101
TAS5086
3.3V
Regulator
TAS5086-5186V6EVM Features
•5.1-channel PurePath Digital evaluation module•Self-contained protection system (short circuit and thermal)•Standard I
2
S and I
2
C/control connector for TI input-USB board•Double-sided plated-through PCB layout
Figure 1-1. Integrated PurePath Digital™ Amplifier System
Physical structure for the TAS5086-5186V6EVM is shown in Figure 1-2 .
Figure 1-2. Physical Structure for TAS5086-5186V6EVM (Rough Outline)
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2.1 Power Supply (PSU) Interface (J901)
Output stage power supply
RESET
>1ms
System power supply
4
1
2
3
(PCB connector top view)
Chapter 2SLEU073 – JULY 2006
System Interfaces
This chapter describes the TAS5086-5186V6EVM board in regards to power suppliesand system interfaces.
The TAS5086-5186V6EVM module must be powered from external power supplies. High-end audioperformance requires a stabilized power supply, with low ripple voltage and low output impedance.
Note: The length of power-supply cable must be minimized. Increasing length of PSU cable isequal to increasing the distortion for the amplifier at high output levels and lowfrequencies.
Maximum output-stage supply voltage depends of the speaker load resistance. Please check therecommended maximum supply voltage in the TAS5186A data sheet.
Table 2-1. Recommended Supply Voltages
DESCRIPTION VOLTAGE LIMITATIONS CURRENT RECOMMENDATIONS
System power supply 15 V to 20 V 0.2 AOutput-stage power supply 0 V to 32 V 2 A
(1)
(1)
The rated current correspond to 2-channel full scale (30 W each), which most likely is adequate fora standard 2.1-channel amplifier design.
The recommended TAS5186A power-up sequence is shown in Figure 2-1 . For proper TAS5186Aoperation, the RESET signal should be kept low during power up. RESET is pulled low during power upfor 200 ms by the onboard reset generator (U908).
Figure 2-1. Recommended Power-Up Sequence
Figure 2-2. J901 Pin Numbers
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2.2 Loudspeaker Connectors (J101 …J106)
1
2
(PCB connector top view)
2.3 Control Interface (J40)
Loudspeaker Connectors (J101 …J106)
Table 2-2. J901 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 PVDD Output-stage power supply2 — System power supply3 GND Ground4 GND Ground
CAUTION
Both positive and negative speaker outputs are floating and may not beconnected to ground (e.g., through an oscilloscope).
Figure 2-3. J101 . . . J106 Pin Numbers
Table 2-3. J101 . . . J106 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 OUT-1 Speaker negative output2 OUT-2 Speaker positive output
This interface connects the TAS5086-5186V6EVM board to a TI input-USB board.
Table 2-4. J40 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 GND Ground2 RESERVED —3 GND Ground4 RESET System reset (bidirectional). ActivateMUTE before RESET for quiet reset.5 BKND-ERR Backend error (or soft reset) providesreduced click and pop reset, withoutresetting I
2
C volume register settings.6 MUTE Ramp volume from any setting tonoiseless soft mute. Mute can also beactivated by I
2
C.7 PDN Power down. TAS5086 will go topower-down state when activated.8 RESERVED —9 RESERVED —10 SDA I
2
C data clock11 GND Ground12 SCL I
2
C bit clock13 RESERVED —
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Control Interface (J40)
Table 2-4. J40 Pin Description (continued)
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
14 RESERVED —15 RESERVED —16 RESERVED —17 GND Ground18 RESERVED —19 RESERVED —20 SD Shutdown error reporting for allchannels. Activated if TAS5186A hashigh current or high temperature. SeeChapter 3, Protection.21 RESERVED —22 OTW Temperature warning. Activated ifTAS5186A has reached temperaturewarning level.23 RESERVED —24 RESERVED —25 GND Ground26 GND Ground27 RESERVED —28 RESERVED —29 RESERVED —30 RESERVED —31 GND Ground32 GND Ground33 +5V +5Vdc power supply (output)34 +5V +5Vdc power supply (output)
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2.4 Digital Audio Interface (J60)
Digital Audio Interface (J60)
The digital audio interface contains digital audio signal data (I
2
S), clocks, etc. Please see the TAS5086Data Manual for signal timing and details not explained in this document.
Table 2-5. J60 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 GND Ground2 MCLK Master clock input. Low-jitter systemclock for PWM generation andreclocking. Ground connection fromsource to TAS5086 must be a lowimpedance connection.3 GND Ground4 SDIN1 I
2
S data 1, channel 1 & 25 SDIN2 I
2
S data 2, channel 3 & 46 SDIN3 I
2
S data 37 SDIN4 I
2
S data 48 — Reserved9 — Reserved10 GND Ground11 SCLK I
2
S bit clock12 GND Ground13 LRCLK I
2
S left-right clock14 GND Ground15 — Reserved16 GND Ground
System Interfaces10 SLEU073 – JULY 2006Submit Documentation Feedback
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