Texas Instruments LMG3410R150-031 EVM Manuel utilisateur

SNOU168–June 2019

LMG3410R150-031 EVM User Guide

User's Guide

SNOU168–June 2019

LMG3410R150-031 EVM User Guide

The LMG3410EVM-031 features two LMG3410R150 600V GaN power transistors with integrated drivers

that are configured in a half bridge with all the required bias circuit and logic/power level shifting. Essential

power stage and gate driving high frequency current loops are fully enclosed on the board to minimize

parasitic inductances, reducing voltage overshoots and improving performance. The LMG3410EVM-031 is

configured to have a socket style external connection for easy interface with external power stages to run

the LMG3410R150 in various applications.

Contents

1 LMG3410EVM-031 User's Guide General TI High Voltage Evaluation User Safety Guidelines.................. 3

2 Description.................................................................................................................... 5

3 Schematic..................................................................................................................... 9

4 Test Setup................................................................................................................... 12

5 Test Procedure ............................................................................................................. 15

6 Typical Characteristics..................................................................................................... 16

7 EVM Assembly Drawing and PCB Layout .............................................................................. 18

8 Bill of Materials ............................................................................................................. 21

List of Figures

1 Simplified LMG3410EVM-031 Schematic ................................................................................ 5

2 Top Side View of LMG3410EVM-031..................................................................................... 6

3 Back Side View of LMG3410EVM-031 ................................................................................... 6

4 Top Side View of LMG3410EVM-031 in Isolated Power Supply Configuration ..................................... 7

5 Back Side View of LMG3410EVM-031 in Isolated Power Supply Configuration.................................... 7

6 LMG3410EVM-031 Schematic............................................................................................. 9

7 Recommended Footprint for LMG3410EVM-031 ...................................................................... 10

8 LMG34XX-BB-EVM Schematic .......................................................................................... 11

9 LMG3410EVM-031 Connected with LMG34XX-BB-EVM ............................................................ 12

10 Recommended Connection Points....................................................................................... 13

11 Recommended Probe Connection for Logic Signals.................................................................. 16

12 Recommended Probe Connection for High Voltage Switch Node................................................... 16

13 Recommended Configuration for Heatsink and Fan................................................................... 16

14 Switching Waveforms with 400V Input, 100kHz, 30% Duty Cycle, 4A Output..................................... 16

15 Low to High Transition Waveform with 400V Input, 100kHz, 30% Duty Cycle, 4A Output....................... 16

16 High to Low Transition Waveform with 400V Input, 100kHz, 30% Duty Cycle, 4A Output....................... 16

17 LMG3410EVM-031 Top Layer and Components ...................................................................... 18

18 LMG3410EVM-031 Inner Copper Layer 1 .............................................................................. 18

19 LMG3410EVM-031 Inner Copper Layer 2 .............................................................................. 19

20 LMG3410EVM-031 Bottom Layer and Components .................................................................. 19

21 LMG34XX-BB-EVM Top Layer and Components...................................................................... 20

22 LMG34XX-BB-EVM Bottom Layer and Components.................................................................. 20

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List of Tables

1 Logic Pin Function Description............................................................................................. 5

2 Power Pin Function Description ........................................................................................... 5

3 Test Point Functional Description........................................................................................ 14

4 List of Terminals............................................................................................................ 14

5 LMG3410EVM-031 List of Materials..................................................................................... 21

6 LMG34XX-BB-EVM List of Materials .................................................................................... 22

Trademarks

All trademarks are the property of their respective owners.

WARNING

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LMG3410EVM-031 User's Guide General TI High Voltage Evaluation User Safety Guidelines

SNOU168–June 2019

LMG3410R150-031 EVM User Guide

1 LMG3410EVM-031 User's Guide

General TI High Voltage Evaluation User Safety Guidelines

Always follow TI’s set-up and application instructions, including use of all interface components within their

recommended electrical rated voltage and power limits. Always use electrical safety precautions to help

ensure your personal safety and the safety of those working around you. Contact TI’s Product Information

Center http://support/ti./com for further information.

Save all warnings and instructions for future reference.

Failure to follow warnings and instructions may result in personal injury, property damage, or

death due to electrical shock and/or burn hazards.

The term TI HV EVM refers to an electronic device typically provided as an open framed, unenclosed

printed circuit board assembly. It is intended strictly for use in development laboratory environments,

solely for qualified professional users having training, expertise, and knowledge of electrical safety risks in

development and application of high-voltage electrical circuits. Any other use and/or application are strictly

prohibited by Texas Instruments. If you are not suitably qualified, you must immediately stop from further

use of the HV EVM.

•Work Area Safety:

– Maintain a clean and orderly work area .

– Qualified observer(s) must be present anytime circuits are energized.

– Effective barriers and signage must be present in the area where the TI HV EVM and its interface

electronics are energized, indicating operation of accessible high voltages may be present, for the

purpose of protecting inadvertent access.

– All interface circuits, power supplies, evaluation modules, instruments, meters, scopes and other

related apparatus used in a development environment exceeding 50 VRMS/75 VDC must be

electrically located within a protected Emergency Power Off (EPO) protected power strip.

– Use a stable and non-conductive work surface.

– Use adequately insulated clamps and wires to attach measurement probes and instruments. No

freehand testing whenever possible.

•Electrical Safety:

As a precautionary measure, it is always a good engineering practice to assume that the entire

EVM may have fully accessible and active high voltages.

– De-energize the TI HV EVM and all its inputs, outputs, and electrical loads before performing any

electrical or other diagnostic measurements. Confirm that TI HV EVM power has been safely de-

energized.

– With the EVM confirmed de-energized, proceed with required electrical circuit configurations, wiring,

measurement equipment hook-ups and other application needs, while still assuming the EVM circuit

and measuring instruments are electrically live.

– When EVM readiness is complete, energize the EVM as intended.

WARNING: While the EVM is energized, never touch the EVM or its electrical circuits as they

could be at high voltages capable of causing electrical shock hazard.

•Personal Safety:

– Wear personal protective equipment, for example, latex gloves and/or safety glasses with side

shields or protect EVM in an adequate lucent plastic box with interlocks from accidental touch.

•Limitation for Safe Use:

– EVMs are not to be used as all or part of a production unit.

LMG3410EVM-031 User's Guide General TI High Voltage Evaluation User Safety Guidelines

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Safety and Precautions

The EVM is designed for professionals who have received the appropriate technical training, and is

designed to operate from an AC power supply or a high-voltage DC supply. Please read this user guide

and the safety-related documents that come with the EVM package before operating this EVM.

CAUTION

Do not leave the EVM powered when unattended.

WARNING

Hot surface! Contact may cause burns. Do not touch!

WARNING

High Voltage! Electric shock is possible when connecting board to

live wire. Board must be handled with care by a professional.

For safety, use of isolated test equipment with overvoltage and

overcurrent protection is highly recommended.

12V

VDD

FAULT

FA_1

12V

VDD

FAULT

FA_2

VDC

PGND

VSW

LMG3410

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Description

SNOU168–June 2019

LMG3410R150-031 EVM User Guide

2 Description

The LMG3410EVM-031 operates as a daughter card as part of a larger custom designed system or with

the LMG34XX-BB-EVM breakout motherboard.

2.1 LMG3410EVM-031

The LMG3410EVM-031 configures two LMG3410R150 GaN FETs in a half bridge. All the bias and level

shifting components are included, allowing low side referenced signals to control both FETs. High

frequency bypass capacitors are included on the power stage in an optimized layout to minimize parasitic

inductance and reduce voltage overshoot.

There are 7 logic pins on the FET card.

Table 1. Logic Pin Function Description

PIN DESCRIPTION

AGND Logic and bias power ground return pin. Functionally isolated from PGND.

12V Auxiliary power input for Q2. Used as auxiliary power input for Q1 when the LMG3410EVM-031 is

configured in bootstrap mode.

5V Auxiliary power input for the LMG3410EVM-031. Used to power logic isolators. Used as input bias power

of LMG3410R050 devices when configured in isolated power mode.

FA_2 FAULT signal from bottom LMG3410R150 Q2. Pin is either pulled to AGND or 5V.

FA_1 FAULT signal from top LMG3410R150 Q1 Pin is either pulled to AGND or 5V.

Q2 AGND referenced logic gate signal input for bottom LMG3410R150 Q2. Compatible with both 3.3V and

5V logic.

Q1 AGND referenced logic gate signal input for top LMG3410R150 Q1. Compatible with both 3.3V and 5V

logic.

There are 3 power pins on the FET card.

Table 2. Power Pin Function Description

PIN DESCRIPTION

VSW Switch node of the half bridge

VDC Input DC voltage of the half bridge

PGND Power ground of the half bridge. Connected to AGND.

Figure 1. Simplified LMG3410EVM-031 Schematic

Description

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WARNING

To minimize the risk of electrical shock hazard caused by high-

voltage levels on the evaluation module whenever it is energized,

proper precautions must be taken when working with the EVM.

Refer Section 1 for high voltage evaluation user safety guidelines.

2.1.1 FAULT

The FA_1 and FA_2 are the fault signal for top and bottom LMG3410EVM-031 respectively. They are

active low when an under voltage lockout on an auxiliary voltage rail, over temperature or overcurrent

even occurs on the LMG3410R150. The fault signal FA_1 for the top LMG3410R150 device is level

shifted to AGND and the fault signal FA_2 for the bottom LMG3410R150 device is referenced to AGND.

CAUTION

Please do NOT ignore fault signal when using LMG3410EVM-031. Turn off

both top and bottom devices, if any device is generating fault signal. The device

under fault condition may operate in undesired 3rd-quadrant mode and may be

over heated and damaged due to the high source-drain voltage drop if the other

device is still switching.

2.1.2 Power Pins

While there are some power stage bypass capacitors on the LMG3410EVM-031 from VDC to PGND to

minimize voltage overshoot during switching, more bulk capacitance is required to hold up the DC voltage

during operation. It is highly recommended to minimize, and ideally prevent, any overlap and parasitic

capacitance from VSW to VDC, PGND and any logic pins. The two grounds PGND and AGND are

connected to each other on the LMG3410EVM-031.

2.1.3 Bootstrap Mode

The LMG3410EVM-031 operates in bootstrap mode, where the 12V bias voltage is used to power both

LMG3410R150 devices. The isolated power supply board can be separated from the main board along

the score line to save the space. The isolated power supply board must not be connected to the main

board under the bootstrap mode.

2.1.4 Isolated Power Supply Mode

The LMG3410EVM-031 card can be modified to enable the top LMG3410R150 Q1 to operate in the

isolated power supply mode. This can be achieved by populating a 0 Ωresistor on R1 and two 2-position

sockets with 1.27 mm pitch mating such as M50-3140245 on J4 and J5. The isolated power supply board

needs to be separated from the main board along the score line and placed on the main board though J4

and J5, shown in Figure 4 and Figure 5. Make sure the direction of the isolated power supply following the

illustration in Figure 5. To disconnect from the boostrap mode, D1 and R2 needs to be removed. Do NOT

power up the LMG3410EVM-031 when R1, R2 and D1 are all populated with the isolated power supply

board connected.

2.1.5 Heatsink

The heatsink is installed to help with heat dissipation of the LMG3410R150. Exposed copper pads that are

attached to the die attach pad (DAP) of both the high and low side devices are provided for a low thermal

impedance point to a heatsink. The two copper pads have high voltage potential difference between them

so an electrically isolative thermal interface material (TIM) is required. Please refer to Section 8 for the

recommended TIM and mechanical fixture.

Isolated power

supply board

Main board

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Description

SNOU168–June 2019

LMG3410R150-031 EVM User Guide

Figure 2. Top Side View of LMG3410EVM-031

Figure 3. Back Side View of LMG3410EVM-031

Figure 4. Top Side View of LMG3410EVM-031 in Isolated

Power Supply Configuration Figure 5. Back Side View of LMG3410EVM-031 in Isolated

Power Supply Configuration

Description

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2.2 LMG34XX-BB-EVM

To allow for quick operation the LMG34XX-BB-EVM is available to interface with the LMG3410EVM-031.

This mother board is designed to operate the LMG3410R150 as a synchronous open loop buck converter.

Easy probe locations are provided for measurement of logic and power stage voltages.

2.2.1 Bias Supply

The motherboard requires one 12V bias supply. When the LMG3410EVM-031 is configured in bootstrap

mode the 12V input is used to power the two LMG3410R150 devices. A linear drop off regulator steps the

voltage down to a tightly regulated 5V for logic power of the LMG3410R150. When the LMG3410EVM-031

is configured in isolated power supply mode the 5V is also used for auxiliary power for the top

LMG3410R150 Q1.

2.2.2 Logic PWM Input

The LMG34XX-BB-EVM supports a single PWM, with complimentary signal and corresponding dead time

generated on board. A 0 V to 5 V magnitude input square wave is required. The complementary PWM

generation circuit creates 50 ns of dead time between both transitions of the PWM signals.

2.2.3 Fault Protection

There is an option to disable PWM input to the FET card in the event of a fault signal from the

LMG3410EVM-031. When the FAULT Protect jumper is placed in the EN mode PWM is disabled when

either LMG3410R050 has an active fault. This disable is not latching, so when the fault clears PWM

immediately resumes. If FAULT Protect mode is not desired it can be disabled by placing the jumper in

the DIS position. The FAULT LED will still illuminate when either LMG3410R150 has an active fault,

regardless of the position of FAULT Protect jumper.

2.3 Typical Applications

The LMG3410EVM-031 is designed for use in AC/DC, DC/DC and DC/AC applications.

• Totem-Pole PFC converters

• Phase-Shifted Full Bridge or LLC Converter

• Buck converter such as the LMG34XX-BB-EVM

2.4 Features

The LMG3410EVM-031 has the following features and specifications:

• Two options to bias the LMG3410, from bootstrap diode or using isolated power

• Over temperature, overcurrent, and under voltage lockout protection with FAULT indication that is level

shifted to an AGND referenced signal

• Gate logic input support of either 3.3V or 5V logic

• Maximum recommended operating voltage of 480V and absolute maximum voltage of 600V

The LMG34XX-BB-EVM has the following features and specifications:

• Requires only a single 12V bias supply

• Requires only a single 0V to 5V PWM input to generate gate drive signal

• PWM disable in the event of a fault from the LMG3410EVM-031

• Maximum recommended operating voltage of 480V and absolute maximum voltage of 600V

• Maximum recommended operating inductor current of 5A

ISO7731DBQR

VCC1

GND1

INA

INB

OUTC

EN1

GND1

8GND2 9

EN2 10

NC 11

INC 12

OUTB 13

OUTA 14

GND2 15

VCC2 16

AGND

TP3

TP2

TP1

5V_H

VM12V_H

VM12V_L

IN_L

AGND

Aux Connector

Power Connector

HVBUS

ISO_RET_H

HVBUS

600V

68pF

ISO_12V_H

AGND

ISONC1

ISONC2

ISONC3

68pF

C17

5V_H

5V_L

SW_L

FAULT_L

5V_L

ISO_RET_H

5V_H

SW_H

IN_H

49.9

R4 22pF

49.9

22pF

C18

5V-AI

20V

DIODE_SCHOTTKY

20V

DIODE_SCHOTTKY

16V

49.9

0.1uF

C20

ISONC4

4.7uF

C21

4.7uF

C23

4.7uF

C22

4.7uF

C24

ISO_12V_H_AO

ISO_12V_H_B

15k 100V/ns

15k 100v/ns

15k

40.2k 60V/ns

0.1uF

1uF

475uH

4 3

D1 1

D2 3

VCC

GND 4

CLK

SN6505

ISO_RET_H

ISO_RET_L

ISO_RET_H_B

-ISO_RET_H_AO

0.022µF

C10

0.022µF

C11

FAULT_H

15k

12V

4.7uF

C15

1uF

C19

1uF

C14

Bot_FET

IN Pin on daughter board

OUT Pin on daughter board

Pin to J1

AGND

Pin for J3

ISO_RET_H

ISO_12V_H

AGND

12V

Bot_FET

Top_FET

AGND

10µH

4.7uF

FAULT_H

FAULT_L

0.047uF

C12

0.047uF

C13

40.2k 60V/ns

0.1uF

C16

1 2

3 4

5 6

7 8

ISO_RET_H

ISO_RET_L

DRAIN 1

DRAIN 2

DRAIN 3

DRAIN 4

DRAIN 5

DRAIN 6

DRAIN 7

DRAIN 8

DRAIN 9

DRAIN 10

DRAIN 11

SOURCE 12

SOURCE 13

SOURCE 14

SOURCE 15

SOURCE 16

SOURCE 18

SOURCE 19

SOURCE 20

SOURCE 21

SOURCE 22

SOURCE 23

SOURCE 24

LDO5V

VNEG

VDD

BBSW

LPM

RDRV

FAULT

PAD 33

LMG3410R150RWHT

DRAIN 1

DRAIN 2

DRAIN 3

DRAIN 4

DRAIN 5

DRAIN 6

DRAIN 7

DRAIN 8

DRAIN 9

DRAIN 10

DRAIN 11

SOURCE 12

SOURCE 13

SOURCE 14

SOURCE 15

SOURCE 16

SOURCE 18

SOURCE 19

SOURCE 20

SOURCE 21

SOURCE 22

SOURCE 23

SOURCE 24

LDO5V

VNEG

VDD

BBSW

LPM

RDRV

FAULT

PAD 33

LMG3410R150RWHT

AGND_AI

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Schematic

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LMG3410R150-031 EVM User Guide

3 Schematic

Figure 6. LMG3410EVM-031 Schematic

Schematic

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LMG3410R150-031 EVM User Guide

Figure 7. Recommended Footprint for LMG3410EVM-031

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